[PATCH] ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz

[Patrice CHOTARD]

Hi Marek

On 8/9/21 2:33 PM, Patrice CHOTARD wrote:
> Hi Marek
> 
> On 8/9/21 2:06 PM, Marek Vasut wrote:
>> The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
>> which causes additional signal delay. At 108 MHz, this delay triggers
>> a sporadic issue where the first bit of RX data is not received by the
>> QSPI controller.
>>
>> There are two options of addressing this problem, either by using the
>> DLYB block to compensate the extra delay, or by reducing the QSPI bus
>> clock frequency. The former requires calibration and that is overly
>> complex for SPL, so opt for the second option. This incurs 20ms delay
>> during boot, when SPL loads U-Boot to DRAM.
>>
>> Signed-off-by: Marek Vasut <marex at denx.de>
>> Cc: Patrice Chotard <patrice.chotard at foss.st.com>
>> Cc: Patrick Delaunay <patrick.delaunay at foss.st.com>
>> ---
>>  arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi
>> index 64299df8166..94cf80dbede 100644
>> --- a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi
>> +++ b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi
>> @@ -198,7 +198,7 @@
>>  		compatible = "jedec,spi-nor";
>>  		reg = <0>;
>>  		spi-rx-bus-width = <4>;
>> -		spi-max-frequency = <108000000>;
>> +		spi-max-frequency = <50000000>;
>>  		#address-cells = <1>;
>>  		#size-cells = <1>;
>>  	};
>>
> Reviewed-by: Patrice Chotard <patrice.chotard at foss.st.com>
> 
> Thanks
> Patrice
> 
Applied to u-boot-stm/master

Thanks
Patrice