[PATCH v2 4/6] vexpress64: Add BASER_FVP vexpress board variant
Peter Hoyes
peter.hoyes at arm.com
Thu Aug 19 17:53:12 CEST 2021
From: Peter Hoyes <Peter.Hoyes at arm.com>
The BASER_FVP board variant is implemented on top of the BASE_FVP board
config (which, in turn, is based on the Juno Versatile Express board
config). They all share a similar memory map - for BASER_FVP the map is
inverted from the BASE_FVP
(https://developer.arm.com/documentation/100964/1114/Base-Platform/Base---memory/BaseR-Platform-memory-map)
* Create new TARGET_VEXPRESS64_BASER_FVP target, which uses the same
board config as BASE_FVP and JUNO
* Adapt vexpress_aemv8a.h header file to support BASER_FVP (and rename
to vexpress_aemv8.h)
* Enable config to switch to EL1 for the BASER_FVP
* Create vexpress_aemv8r defconfig
* Provide an MPU memory map for the BASER_FVP
For now, only single core boot is supported.
Signed-off-by: Peter Hoyes <Peter.Hoyes at arm.com>
---
arch/arm/Kconfig | 7 +++
board/armltd/vexpress64/Kconfig | 5 +-
board/armltd/vexpress64/vexpress64.c | 22 +++++++
configs/vexpress_aemv8r_defconfig | 18 ++++++
doc/README.semihosting | 2 +-
.../{vexpress_aemv8a.h => vexpress_aemv8.h} | 63 ++++++++++++-------
6 files changed, 93 insertions(+), 24 deletions(-)
create mode 100644 configs/vexpress_aemv8r_defconfig
rename include/configs/{vexpress_aemv8a.h => vexpress_aemv8.h} (83%)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e935c60bd7..c96d89b655 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1168,6 +1168,13 @@ config TARGET_VEXPRESS64_BASE_FVP
select PL01X_SERIAL
select SEMIHOSTING
+config TARGET_VEXPRESS64_BASER_FVP
+ bool "Support Versatile Express ARMv8r64 FVP BASE model"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ select PL01X_SERIAL
+
config TARGET_VEXPRESS64_JUNO
bool "Support Versatile Express Juno Development Platform"
select ARM64
diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
index 1d13f542e6..1f0c7ad969 100644
--- a/board/armltd/vexpress64/Kconfig
+++ b/board/armltd/vexpress64/Kconfig
@@ -1,4 +1,5 @@
-if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO
+if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO || \
+ TARGET_VEXPRESS64_BASER_FVP
config SYS_BOARD
default "vexpress64"
@@ -7,7 +8,7 @@ config SYS_VENDOR
default "armltd"
config SYS_CONFIG_NAME
- default "vexpress_aemv8a"
+ default "vexpress_aemv8"
config JUNO_DTB_PART
string "NOR flash partition holding DTB"
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 2e4260286b..eb4951d07c 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -18,6 +18,7 @@
#include <dm/platform_data/serial_pl01x.h>
#include "pcie.h"
#include <asm/armv8/mmu.h>
+#include <asm/armv8/mpu.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -54,6 +55,27 @@ static struct mm_region vexpress64_mem_map[] = {
struct mm_region *mem_map = vexpress64_mem_map;
+static struct mpu_region vexpress64_aemv8r_mem_map[] = {
+ {
+ .start = 0x0UL,
+ .end = 0x7fffffffUL,
+ .attrs = PRLAR_ATTRIDX(MT_NORMAL)
+ }, {
+ .start = 0x80000000UL,
+ .end = 0xffffffffUL,
+ .attrs = PRLAR_ATTRIDX(MT_DEVICE_NGNRNE)
+ }, {
+ .start = 0x100000000UL,
+ .end = 0xffffffffffUL,
+ .attrs = PRLAR_ATTRIDX(MT_NORMAL)
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mpu_region *mpu_mem_map = vexpress64_aemv8r_mem_map;
+
/* This function gets replaced by platforms supporting PCIe.
* The replacement function, eg. on Juno, initialises the PCIe bus.
*/
diff --git a/configs/vexpress_aemv8r_defconfig b/configs/vexpress_aemv8r_defconfig
new file mode 100644
index 0000000000..9b4cd1aa2b
--- /dev/null
+++ b/configs/vexpress_aemv8r_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_TARGET_VEXPRESS64_BASER_FVP=y
+CONFIG_SYS_TEXT_BASE=0x00001000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xff000000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_IDENT_STRING=" vexpress_aemv8r64"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x9c090000 rootfstype=ext4 root=/dev/vda1 rw rootwait"
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="VExpress64# "
+CONFIG_OF_LIBFDT=y
diff --git a/doc/README.semihosting b/doc/README.semihosting
index c019999bed..f382d0131e 100644
--- a/doc/README.semihosting
+++ b/doc/README.semihosting
@@ -25,7 +25,7 @@ or turning on CONFIG_BASE_FVP for the more full featured model.
Rather than create a new armv8 board similar to armltd/vexpress64, add
semihosting calls to the existing one, enabled with CONFIG_SEMIHOSTING
and CONFIG_BASE_FVP both set. Also reuse the existing board config file
-vexpress_aemv8a.h but differentiate the two models by the presence or
+vexpress_aemv8.h but differentiate the two models by the presence or
absence of CONFIG_BASE_FVP. This change is tested and works on both the
Foundation and Base fastmodel simulators.
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8.h
similarity index 83%
rename from include/configs/vexpress_aemv8a.h
rename to include/configs/vexpress_aemv8.h
index 54b5967a89..a51bb29e8a 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8.h
@@ -10,30 +10,36 @@
#define CONFIG_REMAKE_ELF
/* Link Definitions */
-#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#else
/* ATF loads u-boot here for BASE_FVP model */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
-#elif CONFIG_TARGET_VEXPRESS64_JUNO
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#endif
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
/* CS register bases for the original memory map. */
-#define V2M_PA_CS0 0x00000000
-#define V2M_PA_CS1 0x14000000
-#define V2M_PA_CS2 0x18000000
-#define V2M_PA_CS3 0x1c000000
-#define V2M_PA_CS4 0x0c000000
-#define V2M_PA_CS5 0x10000000
+#ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP
+#define V2M_BASE 0x00000000
+#define V2M_PA_BASE 0x80000000
+#else
+#define V2M_BASE 0x80000000
+#define V2M_PA_BASE 0x00000000
+#endif
+
+#define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000)
+#define V2M_PA_CS1 (V2M_PA_BASE + 0x14000000)
+#define V2M_PA_CS2 (V2M_PA_BASE + 0x18000000)
+#define V2M_PA_CS3 (V2M_PA_BASE + 0x1c000000)
+#define V2M_PA_CS4 (V2M_PA_BASE + 0x0c000000)
+#define V2M_PA_CS5 (V2M_PA_BASE + 0x10000000)
#define V2M_PERIPH_OFFSET(x) (x << 16)
#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
-#define V2M_BASE 0x80000000
-
/* Common peripherals relative to CS7. */
#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
@@ -68,20 +74,20 @@
#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 24000000 /* 24MHz */
+#define COUNTER_FREQUENCY 100000000 /* 100MHz */
/* Generic Interrupt Controller Definitions */
#ifdef CONFIG_GICV3
-#define GICD_BASE (0x2f000000)
-#define GICR_BASE (0x2f100000)
+#define GICD_BASE (V2M_PA_BASE + 0x2f000000)
+#define GICR_BASE (V2M_PA_BASE + 0x2f100000)
#else
-#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
-#define GICD_BASE (0x2f000000)
-#define GICC_BASE (0x2c000000)
-#elif CONFIG_TARGET_VEXPRESS64_JUNO
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define GICD_BASE (0x2C010000)
#define GICC_BASE (0x2C02f000)
+#else
+#define GICD_BASE (V2M_PA_BASE + 0x2f000000)
+#define GICC_BASE (V2M_PA_BASE + 0x2c000000)
#endif
#endif /* !CONFIG_GICV3 */
@@ -91,7 +97,7 @@
#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
/* The Vexpress64 simulators use SMSC91C111 */
#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE (0x01A000000)
+#define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000)
#endif
/* PL011 Serial Configuration */
@@ -117,7 +123,7 @@
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define PHYS_SDRAM_2 (0x880000000)
#define PHYS_SDRAM_2_SIZE 0x180000000
-#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2
+#elif CONFIG_NR_DRAM_BANKS == 2
#define PHYS_SDRAM_2 (0x880000000)
#define PHYS_SDRAM_2_SIZE 0x80000000
#endif
@@ -204,6 +210,17 @@
" booti $kernel_addr - $fdt_addr; " \
"fi"
#endif
+
+#elif CONFIG_TARGET_VEXPRESS64_BASER_FVP
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr=0x00800000\0" \
+ "fdt_addr=0x03000000\0" \
+ "boot_addr=0x0007f800\0"
+
+#ifndef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND "fdt addr ${fdt_addr}; fdt resize; " \
+ "booti $kernel_addr - $fdt_addr; "
+#endif
#endif
/* Monitor Command Prompt */
@@ -217,7 +234,7 @@
/* Store environment at top of flash in the same location as blank.img */
/* in the Juno firmware. */
#else
-#define CONFIG_SYS_FLASH_BASE 0x0C000000
+#define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000)
/* 256 x 256KiB sectors */
#define CONFIG_SYS_MAX_FLASH_SECT 256
/* Store environment at top of flash */
@@ -234,4 +251,8 @@
#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
#define FLASH_MAX_SECTOR_SIZE 0x00040000
+#ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP
+#define CONFIG_ARMV8_SWITCH_TO_EL1
+#endif
+
#endif /* __VEXPRESS_AEMV8A_H */
--
2.25.1
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