[PATCH] arm: Migrate GICV2 / GICV3 to Kconfig
Tom Rini
trini at konsulko.com
Thu Aug 19 20:19:39 CEST 2021
Migrate CONFIG_GICV2 and CONFIG_GICV3 to Kconfig. We still have the GIC
related registers that need to be handled more cleanly but start by
moving this symbol to Kconfig.
Signed-off-by: Tom Rini <trini at konsulko.com>
---
arch/arm/Kconfig | 10 ++++++++++
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 ++++++++
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 --
arch/arm/mach-rmobile/Kconfig.64 | 12 ++++++++++++
arch/arm/mach-tegra/Kconfig | 2 ++
arch/arm/mach-versal/Kconfig | 3 ---
include/configs/falcon.h | 9 ++++-----
include/configs/ls1012a_common.h | 2 --
include/configs/ls1043a_common.h | 1 -
include/configs/ls1046a_common.h | 1 -
include/configs/ls2080a_common.h | 1 -
include/configs/lx2160a_common.h | 1 -
include/configs/presidio_asic.h | 1 -
include/configs/rcar-gen3-common.h | 1 -
include/configs/socfpga_soc64_common.h | 5 -----
include/configs/tegra186-common.h | 3 ---
include/configs/tegra210-common.h | 3 ---
include/configs/xilinx_zynqmp.h | 1 -
18 files changed, 36 insertions(+), 30 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d692139199c4..55e6c73eef50 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -63,6 +63,12 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE
endif
endif
+config GICV2
+ bool
+
+config GICV3
+ bool
+
config GIC_V3_ITS
bool "ARM GICV3 ITS"
select REGMAP
@@ -952,6 +958,7 @@ config ARCH_SOCFPGA
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
+ select GICV2
select GPIO_EXTRA_HEADER
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
@@ -1062,6 +1069,7 @@ config ARCH_VERSAL
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
+ select GICV3
select GPIO_EXTRA_HEADER
select OF_CONTROL
imply BOARD_LATE_INIT
@@ -1130,6 +1138,7 @@ config ARCH_ZYNQMP
select DM_SPI if SPI
select DM_SPI_FLASH if DM_SPI
select FIRMWARE
+ select GICV2
select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPL_BOARD_INIT if SPL
@@ -1878,6 +1887,7 @@ config TARGET_DURIAN
config TARGET_PRESIDIO_ASIC
bool "Support Cortina Presidio ASIC Platform"
select ARM64
+ select GICV2
config TARGET_XENGUEST_ARM64
bool "Xen guest ARM64"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 9c58f69dbd0d..5c7ec9ccab57 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -4,6 +4,7 @@ config ARCH_LS1012A
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
@@ -25,6 +26,7 @@ config ARCH_LS1028A
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
select NXP_LSCH3_2
select SYS_FSL_HAS_CCI400
select SYS_FSL_SRDS_1
@@ -58,6 +60,7 @@ config ARCH_LS1043A
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@@ -89,6 +92,7 @@ config ARCH_LS1046A
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@@ -124,6 +128,7 @@ config ARCH_LS1088A
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@@ -168,6 +173,7 @@ config ARCH_LS2080A
select ARM_ERRATA_833471
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@@ -214,6 +220,7 @@ config ARCH_LX2162A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
+ select GICV3
select NXP_LSCH3_2
select SYS_HAS_SERDES
select SYS_FSL_SRDS_1
@@ -245,6 +252,7 @@ config ARCH_LX2160A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
+ select GICV3
select NXP_LSCH3_2
select SYS_HAS_SERDES
select SYS_FSL_SRDS_1
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 3675ce763d1d..f932db10c307 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -123,7 +123,6 @@
#elif defined(CONFIG_ARCH_LS1088A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_GICV3
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
@@ -239,7 +238,6 @@
#elif defined(CONFIG_ARCH_LS1028A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_TZASC_400
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index a6dcce180b4d..98549742e76b 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -4,61 +4,73 @@ menu "Select Target SoC"
config R8A774A1
bool "Renesas SoC R8A774A1"
+ select GICV2
imply CLK_R8A774A1
imply PINCTRL_PFC_R8A774A1
config R8A774B1
bool "Renesas SoC R8A774B1"
+ select GICV2
imply CLK_R8A774B1
imply PINCTRL_PFC_R8A774B1
config R8A774C0
bool "Renesas SoC R8A774C0"
+ select GICV2
imply CLK_R8A774C0
imply PINCTRL_PFC_R8A774C0
config R8A774E1
bool "Renesas SoC R8A774E1"
+ select GICV2
imply CLK_R8A774E1
imply PINCTRL_PFC_R8A774E1
config R8A7795
bool "Renesas SoC R8A7795"
+ select GICV2
imply CLK_R8A7795
imply PINCTRL_PFC_R8A7795
config R8A7796
bool "Renesas SoC R8A7796"
+ select GICV2
imply CLK_R8A7796
imply PINCTRL_PFC_R8A7796
config R8A77965
bool "Renesas SoC R8A77965"
+ select GICV2
imply CLK_R8A77965
imply PINCTRL_PFC_R8A77965
config R8A77970
bool "Renesas SoC R8A77970"
+ select GICV2
imply CLK_R8A77970
imply PINCTRL_PFC_R8A77970
config R8A77980
bool "Renesas SoC R8A77980"
+ select GICV2
imply CLK_R8A77980
imply PINCTRL_PFC_R8A77980
config R8A77990
bool "Renesas SoC R8A77990"
+ select GICV2
imply CLK_R8A77990
imply PINCTRL_PFC_R8A77990
config R8A77995
bool "Renesas SoC R8A77995"
+ select GICV2
imply CLK_R8A77995
imply PINCTRL_PFC_R8A77995
config R8A779A0
bool "Renesas SoC R8A779A0"
+ select GICV3
imply CLK_R8A779A0
imply PINCTRL_PFC_R8A779A0
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 478c7a9e388a..311266400df9 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -124,6 +124,7 @@ config TEGRA124
config TEGRA210
bool "Tegra210 family"
+ select GICV2
select TEGRA_ARMV8_COMMON
select TEGRA_CLKRST
select TEGRA_GPIO
@@ -137,6 +138,7 @@ config TEGRA210
config TEGRA186
bool "Tegra186 family"
select DM_MAILBOX
+ select GICV2
select TEGRA186_BPMP
select TEGRA186_CLOCK
select TEGRA186_GPIO
diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig
index ebd2da3887ec..0c6ad345ffda 100644
--- a/arch/arm/mach-versal/Kconfig
+++ b/arch/arm/mach-versal/Kconfig
@@ -21,9 +21,6 @@ config SYS_CONFIG_NAME
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
-config GICV3
- def_bool y
-
config SYS_MALLOC_LEN
default 0x2000000
diff --git a/include/configs/falcon.h b/include/configs/falcon.h
index 5ecbd1d3edd4..67931febf84f 100644
--- a/include/configs/falcon.h
+++ b/include/configs/falcon.h
@@ -11,14 +11,13 @@
#include "rcar-gen3-common.h"
-/* Generic Interrupt Controller Definitions */
-#ifdef CONFIG_GICV2
-#undef CONFIG_GICV2
+/*
+ * Generic Interrupt Controller Definitions. Undefine v2 locations and define
+ * v3 locations.
+ */
#undef GICD_BASE
#undef GICC_BASE
#undef GICR_BASE
-#endif
-#define CONFIG_GICV3
#define GICD_BASE 0xF1000000
#define GICR_BASE 0xF1060000
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 670b55de26b1..7c8fe7be000a 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -6,8 +6,6 @@
#ifndef __LS1012A_COMMON_H
#define __LS1012A_COMMON_H
-#define CONFIG_GICV2
-
#include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>
#include <linux/sizes.h>
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 834c3e6780af..22f1bb21c16d 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -27,7 +27,6 @@
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_GICV2
#include <asm/arch/stream_id_lsch2.h>
#include <asm/arch/config.h>
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 289acc02d380..cd2103270848 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -27,7 +27,6 @@
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_GICV2
#include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 45273364cf39..fd89133f4924 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -8,7 +8,6 @@
#define __LS2_COMMON_H
#define CONFIG_REMAKE_ELF
-#define CONFIG_GICV3
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 1338ee3cda3b..6fe25764975e 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -12,7 +12,6 @@
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
-#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_MEMAC
diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h
index 3f926212820a..646a496084aa 100644
--- a/include/configs/presidio_asic.h
+++ b/include/configs/presidio_asic.h
@@ -23,7 +23,6 @@
/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
* does not yet support DT. Thus define it here.
*/
-#define CONFIG_GICV2
#define GICD_BASE 0xf7011000
#define GICC_BASE 0xf7012000
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index 99ef27bccd5d..2bad3a9d1bd2 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -26,7 +26,6 @@
#define CONFIG_INITRD_TAG
/* Generic Interrupt Controller Definitions */
-#define CONFIG_GICV2
#define GICD_BASE 0xF1010000
#define GICC_BASE 0xF1020000
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 38fd775b5b6e..91f81503a9bf 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -116,11 +116,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
"then source ${scriptaddr}; fi\0" \
"socfpga_legacy_reset_compat=1\0"
-/*
- * Generic Interrupt Controller Definitions
- */
-#define CONFIG_GICV2
-
/*
* External memory configurations
*/
diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
index d5f21e090722..dbf42203de27 100644
--- a/include/configs/tegra186-common.h
+++ b/include/configs/tegra186-common.h
@@ -17,9 +17,6 @@
* Physical Memory Map
*/
-/* Generic Interrupt Controller */
-#define CONFIG_GICV2
-
#undef FDTFILE
#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \
"if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \
diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h
index 2226effe16ab..2817b1dac79a 100644
--- a/include/configs/tegra210-common.h
+++ b/include/configs/tegra210-common.h
@@ -14,9 +14,6 @@
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
-/* Generic Interrupt Controller */
-#define CONFIG_GICV2
-
/*
* Memory layout for where various images get loaded by boot scripts:
*
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 262154cdffdc..c62d751c1375 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -15,7 +15,6 @@
/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
/* Generic Interrupt Controller Definitions */
-#define CONFIG_GICV2
#define GICD_BASE 0xF9010000
#define GICC_BASE 0xF9020000
--
2.17.1
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