[PATCH] Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig

Sean Anderson seanga2 at gmail.com
Fri Aug 27 02:20:51 CEST 2021


On 8/26/21 11:47 AM, Tom Rini wrote:
> We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to
> arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16.
> Introduce select statements for other architectures based on current
> usage.  For MIPS, we take the existing arch-specific symbol and migrate
> to the generic symbol.  This lets us remove a little bit of otherwise
> unused code.
> 
> Cc: Alexey Brodkin <alexey.brodkin at synopsys.com>
> Cc: Anup Patel <anup.patel at wdc.com>
> Cc: Atish Patra <atish.patra at wdc.com>
> Cc: Bin Meng <bmeng.cn at gmail.com>
> Cc: Daniel Schwierzeck <daniel.schwierzeck at gmail.com>
> Cc: Leo <ycliang at andestech.com>
> Cc: Palmer Dabbelt <palmer at dabbelt.com>
> Cc: Paul Walmsley <paul.walmsley at sifive.com>
> Cc: Rick Chen <rick at andestech.com>
> Cc: Sean Anderson <seanga2 at gmail.com>
> Cc: Simon Glass <sjg at chromium.org>
> Signed-off-by: Tom Rini <trini at konsulko.com>
> ---
> I'm Cc'ing a bunch of RISC-V folks since that's where I'm least
> confident and just put it per-board for now.
> ---
>   arch/Kconfig                       | 25 +++++++++++++++++++++++++
>   arch/arc/include/asm/cache.h       |  3 ---
>   arch/arm/Kconfig                   | 15 ---------------
>   arch/mips/Kconfig                  | 26 +++-----------------------
>   arch/mips/include/asm/cache.h      | 12 +-----------
>   arch/mips/mach-bmips/Kconfig       | 20 ++++++++++----------
>   arch/mips/mach-mtmips/Kconfig      |  4 ++--
>   arch/mips/mach-pic32/Kconfig       |  2 +-
>   arch/powerpc/cpu/mpc83xx/Kconfig   |  6 ++++++
>   arch/powerpc/cpu/mpc85xx/Kconfig   | 15 +++++++++++++++
>   arch/powerpc/cpu/mpc8xx/Kconfig    |  2 ++
>   arch/powerpc/include/asm/cache.h   |  7 -------
>   arch/riscv/Kconfig                 |  2 ++
>   arch/sandbox/include/asm/cache.h   |  1 -
>   arch/x86/include/asm/cache.h       |  7 +------
>   include/configs/M5208EVBE.h        |  1 -
>   include/configs/M5235EVB.h         |  1 -
>   include/configs/M5249EVB.h         |  1 -
>   include/configs/M5253DEMO.h        |  1 -
>   include/configs/M5272C3.h          |  1 -
>   include/configs/M5275EVB.h         |  1 -
>   include/configs/M5282EVB.h         |  1 -
>   include/configs/M53017EVB.h        |  1 -
>   include/configs/M5329EVB.h         |  1 -
>   include/configs/M5373EVB.h         |  1 -
>   include/configs/amcore.h           |  1 -
>   include/configs/astro_mcf5373l.h   |  1 -
>   include/configs/cobra5272.h        |  1 -
>   include/configs/eb_cpu5282.h       |  1 -
>   include/configs/mx7ulp_evk.h       |  2 --
>   include/configs/rk3188_common.h    |  2 --
>   include/configs/rk3368_common.h    |  2 --
>   include/configs/sifive-unmatched.h |  2 --
>   include/configs/sipeed-maix.h      |  1 -
>   include/configs/stmark2.h          |  1 -
>   35 files changed, 68 insertions(+), 103 deletions(-)
> 
> diff --git a/arch/Kconfig b/arch/Kconfig
> index b6f9e177b645..25f4a15b19f9 100644
> --- a/arch/Kconfig
> +++ b/arch/Kconfig
> @@ -7,6 +7,27 @@ config HAVE_ARCH_IOREMAP
>   config NEEDS_MANUAL_RELOC
>   	bool
>   
> +config SYS_CACHE_SHIFT_4
> +	bool
> +
> +config SYS_CACHE_SHIFT_5
> +	bool
> +
> +config SYS_CACHE_SHIFT_6
> +	bool
> +
> +config SYS_CACHE_SHIFT_7
> +	bool
> +
> +config SYS_CACHELINE_SIZE
> +	int
> +	default 128 if SYS_CACHE_SHIFT_7
> +	default 64 if SYS_CACHE_SHIFT_6
> +	default 32 if SYS_CACHE_SHIFT_5
> +	default 16 if SYS_CACHE_SHIFT_4
> +	# Fall-back for MIPS
> +	default 32 if MIPS
> +
>   config LINKER_LIST_ALIGN
>   	int
>   	default 32 if SANDBOX
> @@ -29,6 +50,7 @@ config ARC
>   	select DM
>   	select HAVE_PRIVATE_LIBGCC
>   	select SUPPORT_OF_CONTROL
> +	select SYS_CACHE_SHIFT_7
>   	select TIMER
>   
>   config ARM
> @@ -44,6 +66,7 @@ config M68K
>   	select NEEDS_MANUAL_RELOC
>   	select SYS_BOOT_GET_CMDLINE
>   	select SYS_BOOT_GET_KBD
> +	select SYS_CACHE_SHIFT_4
>   	select SUPPORT_OF_CONTROL
>   
>   config MICROBLAZE
> @@ -122,6 +145,7 @@ config SANDBOX
>   	select SPI
>   	select SUPPORT_OF_CONTROL
>   	select SYSRESET_CMD_POWEROFF
> +	select SYS_CACHE_SHIFT_4
>   	select IRQ
>   	select SUPPORT_EXTENSION_SCAN
>   	imply BITREVERSE
> @@ -188,6 +212,7 @@ config X86
>   	select OF_CONTROL
>   	select PCI
>   	select SUPPORT_OF_CONTROL
> +	select SYS_CACHE_SHIFT_6
>   	select TIMER
>   	select USE_PRIVATE_LIBGCC
>   	select X86_TSC_TIMER
> diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
> index ab61846b5ab9..a48e1aec6889 100644
> --- a/arch/arc/include/asm/cache.h
> +++ b/arch/arc/include/asm/cache.h
> @@ -16,9 +16,6 @@
>    */
>   #define ARCH_DMA_MINALIGN	128
>   
> -/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */
> -#define CONFIG_SYS_CACHELINE_SIZE	ARCH_DMA_MINALIGN
> -
>   #if defined(ARC_MMU_ABSENT)
>   #define CONFIG_ARC_MMU_VER 0
>   #elif defined(CONFIG_ARC_MMU_V2)
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index d692139199c4..e478b9088a09 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -332,21 +332,6 @@ config SYS_ARM_ARCH
>   	default 4 if CPU_SA1100
>   	default 8 if ARM64
>   
> -config SYS_CACHE_SHIFT_5
> -	bool
> -
> -config SYS_CACHE_SHIFT_6
> -	bool
> -
> -config SYS_CACHE_SHIFT_7
> -	bool
> -
> -config SYS_CACHELINE_SIZE
> -	int
> -	default 128 if SYS_CACHE_SHIFT_7
> -	default 64 if SYS_CACHE_SHIFT_6
> -	default 32 if SYS_CACHE_SHIFT_5
> -
>   choice
>   	prompt "Select the ARM data write cache policy"
>   	default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 6b1f10d9a0eb..fa221f1d042c 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -22,7 +22,7 @@ config TARGET_MALTA
>   	select DYNAMIC_IO_PORT_BASE
>   	select MIPS_CM
>   	select MIPS_INSERT_BOOT_CONFIG
> -	select MIPS_L1_CACHE_SHIFT_6
> +	select SYS_CACHE_SHIFT_6
>   	select MIPS_L2_CACHE
>   	select OF_CONTROL
>   	select OF_ISA_BUS
> @@ -132,7 +132,7 @@ config TARGET_BOSTON
>   	select DM
>   	select DM_SERIAL
>   	select MIPS_CM
> -	select MIPS_L1_CACHE_SHIFT_6
> +	select SYS_CACHE_SHIFT_6
>   	select MIPS_L2_CACHE
>   	select OF_BOARD_SETUP
>   	select OF_CONTROL
> @@ -153,7 +153,7 @@ config TARGET_XILFPGA
>   	select DM_ETH
>   	select DM_GPIO
>   	select DM_SERIAL
> -	select MIPS_L1_CACHE_SHIFT_4
> +	select SYS_CACHE_SHIFT_4
>   	select OF_CONTROL
>   	select ROM_EXCEPTION_VECTORS
>   	select SUPPORTS_CPU_MIPS32_R1
> @@ -566,26 +566,6 @@ config SYS_CACHE_SIZE_AUTO
>   	  so if you know the cache configuration for your system at compile
>   	  time it would be beneficial to configure it.
>   
> -config MIPS_L1_CACHE_SHIFT_4
> -	bool
> -
> -config MIPS_L1_CACHE_SHIFT_5
> -	bool
> -
> -config MIPS_L1_CACHE_SHIFT_6
> -	bool
> -
> -config MIPS_L1_CACHE_SHIFT_7
> -	bool
> -
> -config MIPS_L1_CACHE_SHIFT
> -	int
> -	default "7" if MIPS_L1_CACHE_SHIFT_7
> -	default "6" if MIPS_L1_CACHE_SHIFT_6
> -	default "5" if MIPS_L1_CACHE_SHIFT_5
> -	default "4" if MIPS_L1_CACHE_SHIFT_4
> -	default "5"
> -
>   config MIPS_L2_CACHE
>   	bool
>   	help
> diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
> index 00696e672de0..d3e8a8cd414f 100644
> --- a/arch/mips/include/asm/cache.h
> +++ b/arch/mips/include/asm/cache.h
> @@ -6,17 +6,7 @@
>   #ifndef __MIPS_CACHE_H__
>   #define __MIPS_CACHE_H__
>   
> -#define L1_CACHE_SHIFT		CONFIG_MIPS_L1_CACHE_SHIFT
> -#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
> -
> -#define ARCH_DMA_MINALIGN	(L1_CACHE_BYTES)
> -
> -/*
> - * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
> - * DMA buffer alignment. Satisfy those drivers by providing it as a synonym
> - * of ARCH_DMA_MINALIGN for now.
> - */
> -#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
> +#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
>   
>   #ifndef __ASSEMBLY__
>   /**
> diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
> index b259a931c9fb..01d919f2dbe9 100644
> --- a/arch/mips/mach-bmips/Kconfig
> +++ b/arch/mips/mach-bmips/Kconfig
> @@ -21,7 +21,7 @@ choice
>   
>   config SOC_BMIPS_BCM3380
>   	bool "BMIPS BCM3380 family"
> -	select MIPS_L1_CACHE_SHIFT_4
> +	select SYS_CACHE_SHIFT_4
>   	select MIPS_TUNE_4KC
>   	select SUPPORTS_BIG_ENDIAN
>   	select SUPPORTS_CPU_MIPS32_R1
> @@ -31,7 +31,7 @@ config SOC_BMIPS_BCM3380
>   
>   config SOC_BMIPS_BCM6318
>   	bool "BMIPS BCM6318 family"
> -	select MIPS_L1_CACHE_SHIFT_4
> +	select SYS_CACHE_SHIFT_4
>   	select MIPS_TUNE_4KC
>   	select SUPPORTS_BIG_ENDIAN
>   	select SUPPORTS_CPU_MIPS32_R1
> @@ -41,7 +41,7 @@ config SOC_BMIPS_BCM6318
>   
>   config SOC_BMIPS_BCM6328
>   	bool "BMIPS BCM6328 family"
> -	select MIPS_L1_CACHE_SHIFT_4
> +	select SYS_CACHE_SHIFT_4
>   	select MIPS_TUNE_4KC
>   	select SUPPORTS_BIG_ENDIAN
>   	select SUPPORTS_CPU_MIPS32_R1
> @@ -51,7 +51,7 @@ config SOC_BMIPS_BCM6328
>   
>   config SOC_BMIPS_BCM6338
>   	bool "BMIPS BCM6338 family"
> -	select MIPS_L1_CACHE_SHIFT_4
> +	select SYS_CACHE_SHIFT_4
>   	select MIPS_TUNE_4KC
>   	select SUPPORTS_BIG_ENDIAN
>   	select SUPPORTS_CPU_MIPS32_R1
> @@ -61,7 +61,7 @@ config SOC_BMIPS_BCM6338
>   
>   config SOC_BMIPS_BCM6348
>   	bool "BMIPS BCM6348 family"
> -	select MIPS_L1_CACHE_SHIFT_4
> +	select SYS_CACHE_SHIFT_4
>   	select MIPS_TUNE_4KC
>   	select SUPPORTS_BIG_ENDIAN
>   	select SUPPORTS_CPU_MIPS32_R1
> @@ -71,7 +71,7 @@ config SOC_BMIPS_BCM6348
>   
>   config SOC_BMIPS_BCM6358
>   	bool "BMIPS BCM6358 family"
> -	select MIPS_L1_CACHE_SHIFT_4
> +	select SYS_CACHE_SHIFT_4
>   	select MIPS_TUNE_4KC
>   	select SUPPORTS_BIG_ENDIAN
>   	select SUPPORTS_CPU_MIPS32_R1
> @@ -81,7 +81,7 @@ config SOC_BMIPS_BCM6358
>   
>   config SOC_BMIPS_BCM6368
>   	bool "BMIPS BCM6368 family"
> -	select MIPS_L1_CACHE_SHIFT_4
> +	select SYS_CACHE_SHIFT_4
>   	select MIPS_TUNE_4KC
>   	select SUPPORTS_BIG_ENDIAN
>   	select SUPPORTS_CPU_MIPS32_R1
> @@ -91,7 +91,7 @@ config SOC_BMIPS_BCM6368
>   
>   config SOC_BMIPS_BCM6362
>   	bool "BMIPS BCM6362 family"
> -	select MIPS_L1_CACHE_SHIFT_4
> +	select SYS_CACHE_SHIFT_4
>   	select MIPS_TUNE_4KC
>   	select SUPPORTS_BIG_ENDIAN
>   	select SUPPORTS_CPU_MIPS32_R1
> @@ -101,7 +101,7 @@ config SOC_BMIPS_BCM6362
>   
>   config SOC_BMIPS_BCM63268
>   	bool "BMIPS BCM63268 family"
> -	select MIPS_L1_CACHE_SHIFT_4
> +	select SYS_CACHE_SHIFT_4
>   	select MIPS_TUNE_4KC
>   	select SUPPORTS_BIG_ENDIAN
>   	select SUPPORTS_CPU_MIPS32_R1
> @@ -112,7 +112,7 @@ config SOC_BMIPS_BCM63268
>   
>   config SOC_BMIPS_BCM6838
>   	bool "BMIPS BCM6838 family"
> -	select MIPS_L1_CACHE_SHIFT_4
> +	select SYS_CACHE_SHIFT_4
>   	select MIPS_TUNE_4KC
>   	select SUPPORTS_BIG_ENDIAN
>   	select SUPPORTS_CPU_MIPS32_R1
> diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig
> index 8756cadb0b63..747988aed74c 100644
> --- a/arch/mips/mach-mtmips/Kconfig
> +++ b/arch/mips/mach-mtmips/Kconfig
> @@ -39,7 +39,7 @@ choice
>   
>   config SOC_MT7620
>   	bool "MT7620"
> -	select MIPS_L1_CACHE_SHIFT_5
> +	select SYS_CACHE_SHIFT_5
>   	select SYS_MIPS_CACHE_INIT_RAM_LOAD
>   	select PINCTRL_MT7620
>   	select MT7620_SERIAL
> @@ -54,7 +54,7 @@ config SOC_MT7620
>   
>   config SOC_MT7628
>   	bool "MT7628"
> -	select MIPS_L1_CACHE_SHIFT_5
> +	select SYS_CACHE_SHIFT_5
>   	select MIPS_INIT_STACK_IN_SRAM
>   	select MIPS_SRAM_INIT
>   	select SYS_MIPS_CACHE_INIT_RAM_LOAD
> diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
> index 5f13bf14ed6b..2afa972074c1 100644
> --- a/arch/mips/mach-pic32/Kconfig
> +++ b/arch/mips/mach-pic32/Kconfig
> @@ -9,7 +9,7 @@ choice
>   
>   config SOC_PIC32MZDA
>   	bool "Microchip PIC32MZ[DA] family"
> -	select MIPS_L1_CACHE_SHIFT_4
> +	select SYS_CACHE_SHIFT_4
>   	select ROM_EXCEPTION_VECTORS
>   	select SUPPORTS_CPU_MIPS32_R1
>   	select SUPPORTS_CPU_MIPS32_R2
> diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
> index 083febe5bb3d..7c922b230964 100644
> --- a/arch/powerpc/cpu/mpc83xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc83xx/Kconfig
> @@ -131,6 +131,7 @@ config MPC83XX_LDP_PIN
>   config ARCH_MPC830X
>   	bool
>   	select MPC83XX_SDHC_SUPPORT
> +	select SYS_CACHE_SHIFT_5
>   
>   config ARCH_MPC8308
>   	bool
> @@ -154,6 +155,7 @@ config ARCH_MPC831X
>   	select MPC83XX_PCI_SUPPORT
>   	select MPC83XX_TSEC1_SUPPORT
>   	select MPC83XX_TSEC2_SUPPORT
> +	select SYS_CACHE_SHIFT_5
>   
>   config ARCH_MPC8313
>   	bool
> @@ -165,9 +167,11 @@ config ARCH_MPC832X
>   	bool
>   	select MPC83XX_QUICC_ENGINE
>   	select MPC83XX_PCI_SUPPORT
> +	select SYS_CACHE_SHIFT_5
>   
>   config ARCH_MPC834X
>   	bool
> +	select SYS_CACHE_SHIFT_5
>   
>   config ARCH_MPC8349
>   	bool
> @@ -184,6 +188,7 @@ config ARCH_MPC8360
>   	select MPC83XX_PCI_SUPPORT
>   	select MPC83XX_LDP_PIN
>   	select MPC83XX_SECOND_I2C
> +	select SYS_CACHE_SHIFT_5
>   
>   config ARCH_MPC837X
>   	bool
> @@ -196,6 +201,7 @@ config ARCH_MPC837X
>   	select MPC83XX_SATA_SUPPORT
>   	select MPC83XX_LDP_PIN
>   	select MPC83XX_SECOND_I2C
> +	select SYS_CACHE_SHIFT_5
>   	select FSL_ELBC
>   
>   config SYS_IMMR
> diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
> index 395423582a8e..dfa0902aae8f 100644
> --- a/arch/powerpc/cpu/mpc85xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc85xx/Kconfig
> @@ -48,6 +48,7 @@ config TARGET_MPC8548CDS
>   	bool "Support MPC8548CDS"
>   	select ARCH_MPC8548
>   	select FSL_VIA
> +	select SYS_CACHE_SHIFT_5
>   
>   config TARGET_P1010RDB_PA
>   	bool "Support P1010RDB_PA"
> @@ -322,6 +323,7 @@ config ARCH_MPC8540
>   config ARCH_MPC8544
>   	bool
>   	select FSL_LAW
> +	select SYS_CACHE_SHIFT_5
>   	select SYS_FSL_ERRATUM_A005125
>   	select FSL_PCIE_RESET
>   	select SYS_FSL_HAS_DDR2
> @@ -356,6 +358,7 @@ config ARCH_MPC8560
>   config ARCH_P1010
>   	bool
>   	select FSL_LAW
> +	select SYS_CACHE_SHIFT_5
>   	select SYS_FSL_ERRATUM_A004477
>   	select SYS_FSL_ERRATUM_A004508
>   	select SYS_FSL_ERRATUM_A005125
> @@ -401,6 +404,7 @@ config ARCH_P1011
>   config ARCH_P1020
>   	bool
>   	select FSL_LAW
> +	select SYS_CACHE_SHIFT_5
>   	select SYS_FSL_ERRATUM_A004508
>   	select SYS_FSL_ERRATUM_A005125
>   	select SYS_FSL_ERRATUM_ELBC_A001
> @@ -496,6 +500,7 @@ config ARCH_P1025
>   config ARCH_P2020
>   	bool
>   	select FSL_LAW
> +	select SYS_CACHE_SHIFT_5
>   	select SYS_FSL_ERRATUM_A004477
>   	select SYS_FSL_ERRATUM_A004508
>   	select SYS_FSL_ERRATUM_A005125
> @@ -516,6 +521,7 @@ config ARCH_P2041
>   	bool
>   	select E500MC
>   	select FSL_LAW
> +	select SYS_CACHE_SHIFT_6
>   	select SYS_FSL_ERRATUM_A004510
>   	select SYS_FSL_ERRATUM_A004849
>   	select SYS_FSL_ERRATUM_A005275
> @@ -540,6 +546,7 @@ config ARCH_P3041
>   	bool
>   	select E500MC
>   	select FSL_LAW
> +	select SYS_CACHE_SHIFT_6
>   	select SYS_FSL_DDR_VER_44
>   	select SYS_FSL_ERRATUM_A004510
>   	select SYS_FSL_ERRATUM_A004849
> @@ -569,6 +576,7 @@ config ARCH_P4080
>   	bool
>   	select E500MC
>   	select FSL_LAW
> +	select SYS_CACHE_SHIFT_6
>   	select SYS_FSL_DDR_VER_44
>   	select SYS_FSL_ERRATUM_A004510
>   	select SYS_FSL_ERRATUM_A004580
> @@ -607,6 +615,7 @@ config ARCH_P5040
>   	bool
>   	select E500MC
>   	select FSL_LAW
> +	select SYS_CACHE_SHIFT_6
>   	select SYS_FSL_DDR_VER_44
>   	select SYS_FSL_ERRATUM_A004510
>   	select SYS_FSL_ERRATUM_A004699
> @@ -630,11 +639,13 @@ config ARCH_P5040
>   
>   config ARCH_QEMU_E500
>   	bool
> +	select SYS_CACHE_SHIFT_5
>   
>   config ARCH_T1024
>   	bool
>   	select E500MC
>   	select FSL_LAW
> +	select SYS_CACHE_SHIFT_6
>   	select SYS_FSL_DDR_VER_50
>   	select SYS_FSL_ERRATUM_A008378
>   	select SYS_FSL_ERRATUM_A008109
> @@ -657,6 +668,7 @@ config ARCH_T1040
>   	bool
>   	select E500MC
>   	select FSL_LAW
> +	select SYS_CACHE_SHIFT_6
>   	select SYS_FSL_DDR_VER_50
>   	select SYS_FSL_ERRATUM_A008044
>   	select SYS_FSL_ERRATUM_A008378
> @@ -679,6 +691,7 @@ config ARCH_T1042
>   	bool
>   	select E500MC
>   	select FSL_LAW
> +	select SYS_CACHE_SHIFT_6
>   	select SYS_FSL_DDR_VER_50
>   	select SYS_FSL_ERRATUM_A008044
>   	select SYS_FSL_ERRATUM_A008378
> @@ -702,6 +715,7 @@ config ARCH_T2080
>   	select E500MC
>   	select E6500
>   	select FSL_LAW
> +	select SYS_CACHE_SHIFT_6
>   	select SYS_FSL_DDR_VER_47
>   	select SYS_FSL_ERRATUM_A006379
>   	select SYS_FSL_ERRATUM_A006593
> @@ -730,6 +744,7 @@ config ARCH_T4240
>   	select E500MC
>   	select E6500
>   	select FSL_LAW
> +	select SYS_CACHE_SHIFT_6
>   	select SYS_FSL_DDR_VER_47
>   	select SYS_FSL_ERRATUM_A004468
>   	select SYS_FSL_ERRATUM_A005871
> diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
> index f11231737656..936cbda11bc3 100644
> --- a/arch/powerpc/cpu/mpc8xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc8xx/Kconfig
> @@ -19,9 +19,11 @@ choice
>   
>   config MPC866
>   	bool "MPC866"
> +	select SYS_CACHE_SHIFT_4
>   
>   config MPC885
>   	bool "MPC885"
> +	select SYS_CACHE_SHIFT_4
>   
>   endchoice
>   
> diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
> index ac8eeb4caa5a..f753ddf799ee 100644
> --- a/arch/powerpc/include/asm/cache.h
> +++ b/arch/powerpc/include/asm/cache.h
> @@ -25,13 +25,6 @@
>    */
>   #define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
>   
> -/*
> - * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
> - */
> -#ifndef CONFIG_SYS_CACHELINE_SIZE
> -#define CONFIG_SYS_CACHELINE_SIZE	L1_CACHE_BYTES
> -#endif
> -
>   #define	L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
>   #define	L1_CACHE_PAGES		8
>   
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 4b0c3dffa6b1..691ed1138245 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -22,9 +22,11 @@ config TARGET_SIFIVE_UNLEASHED
>   
>   config TARGET_SIFIVE_UNMATCHED
>   	bool "Support SiFive Unmatched Board"
> +	select SYS_CACHE_SHIFT_6
>   
>   config TARGET_SIPEED_MAIX
>   	bool "Support Sipeed Maix Board"
> +	select SYS_CACHE_SHIFT_6
>   
>   config TARGET_OPENPITON_RISCV64
>   	bool "Support RISC-V cores on OpenPiton SoC"
> diff --git a/arch/sandbox/include/asm/cache.h b/arch/sandbox/include/asm/cache.h
> index 9348a13e73da..609a835967b8 100644
> --- a/arch/sandbox/include/asm/cache.h
> +++ b/arch/sandbox/include/asm/cache.h
> @@ -19,6 +19,5 @@
>   #else
>   #define ARCH_DMA_MINALIGN	16
>   #endif
> -#define CONFIG_SYS_CACHELINE_SIZE	ARCH_DMA_MINALIGN
>   
>   #endif /* __SANDBOX_CACHE_H__ */
> diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h
> index 145b8784de1e..256a3c01ed98 100644
> --- a/arch/x86/include/asm/cache.h
> +++ b/arch/x86/include/asm/cache.h
> @@ -7,13 +7,8 @@
>   #define __X86_CACHE_H__
>   
>   /*
> - * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment.  Otherwise
> - * use 64-bytes, a safe default for x86.
> + * Use CONFIG_SYS_CACHELINE_SIZE (which is set to 64-bytes) for DMA alignment.
>    */
> -#ifndef CONFIG_SYS_CACHELINE_SIZE
> -#define CONFIG_SYS_CACHELINE_SIZE	64
> -#endif
> -
>   #define ARCH_DMA_MINALIGN		CONFIG_SYS_CACHELINE_SIZE
>   
>   static inline void wbinvd(void)
> diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
> index 1b8312bbc07d..efd4d760ee74 100644
> --- a/include/configs/M5208EVBE.h
> +++ b/include/configs/M5208EVBE.h
> @@ -138,7 +138,6 @@
>   	env/embedded.o(.text*);
>   
>   /* Cache Configuration */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
> index d061f4587082..9a988540dfd4 100644
> --- a/include/configs/M5235EVB.h
> +++ b/include/configs/M5235EVB.h
> @@ -154,7 +154,6 @@
>   /*-----------------------------------------------------------------------
>    * Cache Configuration
>    */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
> index 1a1a11076543..eea718c5345e 100644
> --- a/include/configs/M5249EVB.h
> +++ b/include/configs/M5249EVB.h
> @@ -104,7 +104,6 @@
>   /*-----------------------------------------------------------------------
>    * Cache Configuration
>    */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
> index 8ac0086629da..ad310e84846d 100644
> --- a/include/configs/M5253DEMO.h
> +++ b/include/configs/M5253DEMO.h
> @@ -160,7 +160,6 @@
>   #endif
>   
>   /* Cache Configuration */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
> index 2cdd4369da00..e0dd5b42f4e6 100644
> --- a/include/configs/M5272C3.h
> +++ b/include/configs/M5272C3.h
> @@ -134,7 +134,6 @@
>   /*-----------------------------------------------------------------------
>    * Cache Configuration
>    */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
> index eb7823a98a58..072d44a80f5b 100644
> --- a/include/configs/M5275EVB.h
> +++ b/include/configs/M5275EVB.h
> @@ -147,7 +147,6 @@
>   /*-----------------------------------------------------------------------
>    * Cache Configuration
>    */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
> index 6a50a25d3254..7c0450d2a083 100644
> --- a/include/configs/M5282EVB.h
> +++ b/include/configs/M5282EVB.h
> @@ -142,7 +142,6 @@
>   /*-----------------------------------------------------------------------
>    * Cache Configuration
>    */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
> index a063b92a643f..349996e43c67 100644
> --- a/include/configs/M53017EVB.h
> +++ b/include/configs/M53017EVB.h
> @@ -158,7 +158,6 @@
>   /*-----------------------------------------------------------------------
>    * Cache Configuration
>    */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
> index 4fc6d3819249..169f0535ae30 100644
> --- a/include/configs/M5329EVB.h
> +++ b/include/configs/M5329EVB.h
> @@ -165,7 +165,6 @@
>   /*-----------------------------------------------------------------------
>    * Cache Configuration
>    */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
> index 7a9240a57171..7f3a39a697ec 100644
> --- a/include/configs/M5373EVB.h
> +++ b/include/configs/M5373EVB.h
> @@ -167,7 +167,6 @@
>   /*-----------------------------------------------------------------------
>    * Cache Configuration
>    */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/amcore.h b/include/configs/amcore.h
> index 641d8fdbd53d..1eb9e5f2aca8 100644
> --- a/include/configs/amcore.h
> +++ b/include/configs/amcore.h
> @@ -75,7 +75,6 @@
>    * This is a single unified instruction/data cache.
>    * sdram - single region - no masks
>    */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
> index 2ea33e5eff22..845dd5eb51e7 100644
> --- a/include/configs/astro_mcf5373l.h
> +++ b/include/configs/astro_mcf5373l.h
> @@ -272,7 +272,6 @@
>   #endif
>   
>   /* Cache Configuration */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
> index c859616c68cb..c4c7dcc0fe1e 100644
> --- a/include/configs/cobra5272.h
> +++ b/include/configs/cobra5272.h
> @@ -237,7 +237,6 @@ from which user programs will be started */
>   /*-----------------------------------------------------------------------
>    * Cache Configuration
>    */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
> index 77584fa7a5d2..2fa057c571d2 100644
> --- a/include/configs/eb_cpu5282.h
> +++ b/include/configs/eb_cpu5282.h
> @@ -135,7 +135,6 @@
>   /*-----------------------------------------------------------------------
>    * Cache Configuration
>    */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
> index 0c3103082cc8..f653742ce520 100644
> --- a/include/configs/mx7ulp_evk.h
> +++ b/include/configs/mx7ulp_evk.h
> @@ -33,8 +33,6 @@
>   /* UART */
>   #define LPUART_BASE			LPUART4_RBASE
>   
> -#define CONFIG_SYS_CACHELINE_SIZE      64
> -
>   /* Miscellaneous configurable options */
>   #define CONFIG_SYS_PROMPT		"=> "
>   #define CONFIG_SYS_CBSIZE		512
> diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
> index 3bcc04808a3c..b7c001a37eab 100644
> --- a/include/configs/rk3188_common.h
> +++ b/include/configs/rk3188_common.h
> @@ -6,8 +6,6 @@
>   #ifndef __CONFIG_RK3188_COMMON_H
>   #define __CONFIG_RK3188_COMMON_H
>   
> -#define CONFIG_SYS_CACHELINE_SIZE	64
> -
>   #include <asm/arch-rockchip/hardware.h>
>   #include "rockchip-common.h"
>   
> diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
> index fbbb8cf267e6..f83761a82782 100644
> --- a/include/configs/rk3368_common.h
> +++ b/include/configs/rk3368_common.h
> @@ -8,8 +8,6 @@
>   
>   #include "rockchip-common.h"
>   
> -#define CONFIG_SYS_CACHELINE_SIZE	64
> -
>   #include <asm/arch-rockchip/hardware.h>
>   #include <linux/sizes.h>
>   
> diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
> index d63a5f62fbc7..f13e95f342ef 100644
> --- a/include/configs/sifive-unmatched.h
> +++ b/include/configs/sifive-unmatched.h
> @@ -38,8 +38,6 @@
>   
>   #define CONFIG_SYS_PCI_64BIT		1	/* enable 64-bit resources */
>   
> -#define CONFIG_SYS_CACHELINE_SIZE	64
> -
>   /* Environment options */
>   
>   #ifndef CONFIG_SPL_BUILD
> diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h
> index 0fbe8a59058e..00cc4b80c9cb 100644
> --- a/include/configs/sipeed-maix.h
> +++ b/include/configs/sipeed-maix.h
> @@ -12,7 +12,6 @@
>   /* Start just below the second bank so we don't clobber it during reloc */
>   #define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF
>   #define CONFIG_SYS_MALLOC_LEN SZ_128K
> -#define CONFIG_SYS_CACHELINE_SIZE 64
>   
>   #define CONFIG_SYS_SDRAM_BASE 0x80000000
>   #define CONFIG_SYS_SDRAM_SIZE SZ_8M
> diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
> index da162cbb1140..a2c466e18551 100644
> --- a/include/configs/stmark2.h
> +++ b/include/configs/stmark2.h
> @@ -132,7 +132,6 @@
>   #endif
>   
>   /* Cache Configuration */
> -#define CONFIG_SYS_CACHELINE_SIZE	16
>   #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
>   					 CONFIG_SYS_INIT_RAM_SIZE - 8)
>   #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
> 

For maix:

Acked-by: Sean Anderson <seanga2 at gmail.com>


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