[PATCH v1 1/2] net: brcm: netXtreme driver
Ramon Fried
rfried.dev at gmail.com
Sat Aug 28 15:36:19 CEST 2021
On Mon, Aug 23, 2021 at 5:14 PM Bharat Kumar Reddy Gooty
<bharat.gooty at broadcom.com> wrote:
>
> From: Bharat Gooty <bharat.gooty at broadcom.com>
>
> Broadcom bnxt L2 driver support. Used by the Broadcom
> iproc platforms.
>
> Signed-off-by: Bharat Gooty <bharat.gooty at broadcom.com>
> ---
> drivers/net/Kconfig | 1 +
> drivers/net/Makefile | 1 +
> drivers/net/bnxt/Kconfig | 7 +
> drivers/net/bnxt/Makefile | 5 +
> drivers/net/bnxt/bnxt.c | 2025 +++++++++++++++++++++++++++++++++++
> drivers/net/bnxt/bnxt_dbg.h | 538 ++++++++++
> drivers/net/bnxt/pci_ids.h | 17 +
> include/broadcom/bnxt.h | 419 ++++++++
> include/broadcom/bnxt_hsi.h | 889 +++++++++++++++
> include/broadcom/bnxt_ver.h | 22 +
> 10 files changed, 3924 insertions(+)
> create mode 100644 drivers/net/bnxt/Kconfig
> create mode 100644 drivers/net/bnxt/Makefile
> create mode 100644 drivers/net/bnxt/bnxt.c
> create mode 100644 drivers/net/bnxt/bnxt_dbg.h
> create mode 100644 drivers/net/bnxt/pci_ids.h
> create mode 100644 include/broadcom/bnxt.h
> create mode 100644 include/broadcom/bnxt_hsi.h
> create mode 100644 include/broadcom/bnxt_ver.h
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 382639044b..ff2c1797b1 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -1,6 +1,7 @@
> source "drivers/net/phy/Kconfig"
> source "drivers/net/pfe_eth/Kconfig"
> source "drivers/net/fsl-mc/Kconfig"
> +source "drivers/net/bnxt/Kconfig"
>
> config DM_ETH
> bool "Enable Driver Model for Ethernet drivers"
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index a44a7d3f56..f739f1e157 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -96,3 +96,4 @@ obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
> obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
> obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
> obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o
> +obj-$(CONFIG_BNXT_ETH) += bnxt/
> diff --git a/drivers/net/bnxt/Kconfig b/drivers/net/bnxt/Kconfig
> new file mode 100644
> index 0000000000..c263616612
> --- /dev/null
> +++ b/drivers/net/bnxt/Kconfig
> @@ -0,0 +1,7 @@
> +config BNXT_ETH
> + bool "BNXT PCI support"
> + depends on DM_ETH && DM_PCI
> + help
> + This driver implements support for bnxt pci controller
> + driver of ethernet class.
> +
> diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile
> new file mode 100644
> index 0000000000..a9d6ce00d5
> --- /dev/null
> +++ b/drivers/net/bnxt/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +# Copyright 2019-2021 Broadcom.
> +
> +# Broadcom nxe Ethernet driver
> +obj-y += bnxt.o
> diff --git a/drivers/net/bnxt/bnxt.c b/drivers/net/bnxt/bnxt.c
> new file mode 100644
> index 0000000000..144df587f7
> --- /dev/null
> +++ b/drivers/net/bnxt/bnxt.c
> @@ -0,0 +1,2025 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 Broadcom.
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +
> +#include <asm/io.h>
> +#include <broadcom/bnxt.h>
> +#include <dm.h>
> +#include <dm/device-internal.h>
> +#include <env_flags.h>
> +#include <env_internal.h>
> +#include <errno.h>
> +#include <linux/ctype.h>
> +#include <linux/delay.h>
> +#include <linux/types.h>
> +#include <memalign.h>
> +#include <net.h>
> +
> +#include "bnxt_dbg.h"
> +#include "pci_ids.h"
> +
> +#define bnxt_down_chip(bp) bnxt_hwrm_run(down_chip, bp, 0)
> +#define bnxt_bring_chip(bp) bnxt_hwrm_run(bring_chip, bp, 1)
> +
> +static const char banner[] = DRV_MODULE_DESC " v" UBOOT_MODULE_VER ",";
> +static const char fw_ver[] = " FW v";
> +
> +static int num_cards; /* Number of bnxt devices seen so far */
> +
> +static void display_banner(struct bnxt *bp)
> +{
> + int i;
> +
> + printf(banner);
> + printf(fw_ver);
> + printf("%d.%d.", bp->fw_maj, bp->fw_min);
> + printf("%d.%d\n", bp->fw_bld, bp->fw_rsvd);
> + printf("ETH MAC: ");
> + for (i = 0; i < ETH_ALEN; i++) {
> + printf("%02x", bp->mac_set[i]);
> + if (i != (ETH_ALEN - 1))
> + printf(":");
> + }
> +
> + printf(", Port(%d), PF(%d)\n", bp->port_idx, bp->ordinal_value);
> +}
> +
> +/* Broadcom ethernet driver PCI APIs. */
> +static void bnxt_bring_pci(struct bnxt *bp)
> +{
> + u16 cmd_reg = 0;
> +
> + pci_read_word16(bp->pdev, PCI_VENDOR_ID, &bp->vendor_id);
> + pci_read_word16(bp->pdev, PCI_DEVICE_ID, &bp->device_id);
> + pci_read_word16(bp->pdev,
> + PCI_SUBSYSTEM_VENDOR_ID,
> + &bp->subsystem_vendor);
> + pci_read_word16(bp->pdev, PCI_SUBSYSTEM_ID, &bp->subsystem_device);
> + pci_read_word16(bp->pdev, PCI_COMMAND, &bp->cmd_reg);
> + pci_read_byte(bp->pdev, PCICFG_ME_REGISTER, &bp->pf_num);
> + pci_read_byte(bp->pdev, PCI_INTERRUPT_LINE, &bp->irq);
> + bp->bar0 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
> + bp->bar1 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
> + bp->bar2 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
> + cmd_reg = bp->cmd_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
> + cmd_reg |= PCI_COMMAND_INTX_DISABLE; /* disable intr */
> + pci_write_word(bp->pdev, PCI_COMMAND, cmd_reg);
> + pci_read_word16(bp->pdev, PCI_COMMAND, &cmd_reg);
> + dbg_pci(bp, __func__, cmd_reg);
> +}
> +
> +int bnxt_free_rx_iob(struct bnxt *bp)
> +{
> + unsigned int i;
> +
> + if (!(FLAG_TEST(bp->flag_hwrm, VALID_RX_IOB)))
> + return STATUS_SUCCESS;
> +
> + for (i = 0; i < bp->rx.buf_cnt; i++) {
> + if (bp->rx.iob[i]) {
> + free(bp->rx.iob[i]);
> + bp->rx.iob[i] = NULL;
> + }
> + }
> +
> + FLAG_RESET(bp->flag_hwrm, VALID_RX_IOB);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static void set_rx_desc(u8 *buf, void *iob, u16 cons_id, u32 iob_idx)
> +{
> + struct rx_prod_pkt_bd *desc;
> + u16 off = cons_id * sizeof(struct rx_prod_pkt_bd);
> +
> + desc = (struct rx_prod_pkt_bd *)&buf[off];
> + desc->flags_type = RX_PROD_PKT_BD_TYPE_RX_PROD_PKT;
> + desc->len = MAX_ETHERNET_PACKET_BUFFER_SIZE;
> + desc->opaque = iob_idx;
> + desc->dma.addr = virt_to_bus(iob);
> +}
> +
> +static int bnxt_alloc_rx_iob(struct bnxt *bp, u16 cons_id, u16 iob_idx)
> +{
> + void *iob;
> +
> + iob = memalign(BNXT_DMA_ALIGNMENT, RX_STD_DMA_ALIGNED);
> + if (!iob)
> + return -ENOMEM;
> +
> + dbg_rx_iob(iob, iob_idx, cons_id);
> + set_rx_desc((u8 *)bp->rx.bd_virt, iob, cons_id, (u32)iob_idx);
> + bp->rx.iob[iob_idx] = iob;
> +
> + return 0;
> +}
> +
> +void bnxt_mm_init(struct bnxt *bp, const char *func)
> +{
> + memset(bp->hwrm_addr_req, 0, REQ_BUFFER_SIZE);
> + memset(bp->hwrm_addr_resp, 0, RESP_BUFFER_SIZE);
> + memset(bp->cq.bd_virt, 0, CQ_RING_DMA_BUFFER_SIZE);
> + memset(bp->tx.bd_virt, 0, TX_RING_DMA_BUFFER_SIZE);
> + memset(bp->rx.bd_virt, 0, RX_RING_DMA_BUFFER_SIZE);
> +
> + bp->data_addr_mapping = virt_to_bus(bp->hwrm_addr_data);
> + bp->req_addr_mapping = virt_to_bus(bp->hwrm_addr_req);
> + bp->resp_addr_mapping = virt_to_bus(bp->hwrm_addr_resp);
> + bp->wait_link_timeout = LINK_DEFAULT_TIMEOUT;
> + bp->link_status = STATUS_LINK_DOWN;
> + bp->media_change = 1;
> + bp->mtu = MAX_ETHERNET_PACKET_BUFFER_SIZE;
> + bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
> + bp->rx.buf_cnt = NUM_RX_BUFFERS;
> + bp->rx.ring_cnt = MAX_RX_DESC_CNT;
> + bp->tx.ring_cnt = MAX_TX_DESC_CNT;
> + bp->cq.ring_cnt = MAX_CQ_DESC_CNT;
> + bp->cq.completion_bit = 0x1;
> + bp->link_set = LINK_SPEED_DRV_100G;
> + dbg_mem(bp, func);
> +}
> +
> +void bnxt_free_mem(struct bnxt *bp)
> +{
> + if (bp->cq.bd_virt) {
> + free(bp->cq.bd_virt);
> + bp->cq.bd_virt = NULL;
> + }
> +
> + if (bp->rx.bd_virt) {
> + free(bp->rx.bd_virt);
> + bp->rx.bd_virt = NULL;
> + }
> +
> + if (bp->tx.bd_virt) {
> + free(bp->tx.bd_virt);
> + bp->tx.bd_virt = NULL;
> + }
> +
> + if (bp->hwrm_addr_resp) {
> + free(bp->hwrm_addr_resp);
> + bp->resp_addr_mapping = 0;
> + bp->hwrm_addr_resp = NULL;
> + }
> +
> + if (bp->hwrm_addr_req) {
> + free(bp->hwrm_addr_req);
> + bp->req_addr_mapping = 0;
> + bp->hwrm_addr_req = NULL;
> + }
> +
> + if (bp->hwrm_addr_data) {
> + free(bp->hwrm_addr_data);
> + bp->data_addr_mapping = 0;
> + bp->hwrm_addr_data = NULL;
> + }
> +
> + dbg_mem_free_done(__func__);
> +}
> +
> +int bnxt_alloc_mem(struct bnxt *bp)
> +{
> + bp->hwrm_addr_data = memalign(BNXT_DMA_ALIGNMENT, DMA_BUF_SIZE_ALIGNED);
> + bp->hwrm_addr_req = memalign(BNXT_DMA_ALIGNMENT, REQ_BUF_SIZE_ALIGNED);
> + bp->hwrm_addr_resp = MEM_HWRM_RESP;
> +
> + memset(&bp->tx, 0, sizeof(struct lm_tx_info_t));
> + memset(&bp->rx, 0, sizeof(struct lm_rx_info_t));
> + memset(&bp->cq, 0, sizeof(struct lm_cmp_info_t));
> +
> + bp->tx.bd_virt = memalign(BNXT_DMA_ALIGNMENT, TX_RING_DMA_BUFFER_SIZE);
> + bp->rx.bd_virt = memalign(BNXT_DMA_ALIGNMENT, RX_RING_DMA_BUFFER_SIZE);
> + bp->cq.bd_virt = memalign(BNXT_DMA_ALIGNMENT, CQ_RING_DMA_BUFFER_SIZE);
> +
> + test_if(bp->hwrm_addr_req &&
> + bp->hwrm_addr_resp &&
> + bp->hwrm_addr_data &&
> + bp->tx.bd_virt &&
> + bp->rx.bd_virt &&
> + bp->cq.bd_virt) {
> + bnxt_mm_init(bp, __func__);
> + return STATUS_SUCCESS;
> + }
> +
> + dbg_mem_alloc_fail(__func__);
> + bnxt_free_mem(bp);
> +
> + return -ENOMEM;
> +}
> +
> +static void hwrm_init(struct bnxt *bp, struct input *req, u16 cmd, u16 len)
> +{
> + memset(req, 0, len);
> + req->req_type = cmd;
> + req->cmpl_ring = (u16)HWRM_NA_SIGNATURE;
> + req->target_id = (u16)HWRM_NA_SIGNATURE;
> + req->resp_addr = bp->resp_addr_mapping;
> + req->seq_id = bp->seq_id++;
> +}
> +
> +static void hwrm_write_req(struct bnxt *bp, void *req, u32 cnt)
> +{
> + u32 i = 0;
> +
> + for (i = 0; i < cnt; i++) {
> + write32(((u32 *)req)[i],
> + (bp->bar0 + GRC_COM_CHAN_BASE + (i * 4)));
> + }
> +
> + writel(0x1, (bp->bar0 + GRC_COM_CHAN_BASE + GRC_COM_CHAN_TRIG));
> +}
> +
> +static void short_hwrm_cmd_req(struct bnxt *bp, u16 len)
> +{
> + struct hwrm_short_input sreq;
> +
> + memset(&sreq, 0, sizeof(struct hwrm_short_input));
> + sreq.req_type = (u16)((struct input *)bp->hwrm_addr_req)->req_type;
> + sreq.signature = SHORT_REQ_SIGNATURE_SHORT_CMD;
> + sreq.size = len;
> + sreq.req_addr = bp->req_addr_mapping;
> + dbg_short_cmd((u8 *)&sreq, __func__, sizeof(struct hwrm_short_input));
> + hwrm_write_req(bp, &sreq, sizeof(struct hwrm_short_input) / 4);
> +}
> +
> +static int wait_resp(struct bnxt *bp, u32 tmo, u16 len, const char *func)
> +{
> + struct input *req = (struct input *)bp->hwrm_addr_req;
> + struct output *resp = (struct output *)bp->hwrm_addr_resp;
> + u8 *ptr = (u8 *)resp;
> + u32 idx;
> + u32 wait_cnt = HWRM_CMD_DEFAULT_MULTIPLAYER((u32)tmo);
> + u16 resp_len = 0;
> + u16 ret = STATUS_TIMEOUT;
> +
> + if (len > bp->hwrm_max_req_len)
> + short_hwrm_cmd_req(bp, len);
> + else
> + hwrm_write_req(bp, req, (u32)(len / 4));
> +
> + for (idx = 0; idx < wait_cnt; idx++) {
> + resp_len = resp->resp_len;
> + test_if(resp->seq_id == req->seq_id &&
> + resp->req_type == req->req_type &&
> + ptr[resp_len - 1] == 1) {
> + bp->last_resp_code = resp->error_code;
> + ret = resp->error_code;
> + break;
> + }
> +
> + udelay(HWRM_CMD_POLL_WAIT_TIME);
> + }
> +
> + dbg_hw_cmd(bp, func, len, resp_len, tmo, ret);
> +
> + return (int)ret;
> +}
> +
> +static void bnxt_db_cq(struct bnxt *bp)
> +{
> + writel(CQ_DOORBELL_KEY_IDX(bp->cq.cons_idx), bp->bar1);
> +}
> +
> +static void bnxt_db_rx(struct bnxt *bp, u32 idx)
> +{
> + writel(RX_DOORBELL_KEY_RX | idx, bp->bar1);
> +}
> +
> +static void bnxt_db_tx(struct bnxt *bp, u32 idx)
> +{
> + writel((u32)(TX_DOORBELL_KEY_TX | idx), bp->bar1);
> +}
> +
> +int iob_pad(void *packet, int length)
> +{
> + if (length >= ETH_ZLEN)
> + return length;
> +
> + memset(((u8 *)packet + length), 0x00, (ETH_ZLEN - length));
> +
> + return ETH_ZLEN;
> +}
> +
> +static inline u32 bnxt_tx_avail(struct bnxt *bp)
> +{
> + barrier();
> +
> + return TX_AVAIL(bp->tx.ring_cnt) -
> + ((bp->tx.prod_id - bp->tx.cons_id) &
> + (bp->tx.ring_cnt - 1));
> +}
> +
> +void set_txq(struct bnxt *bp, int entry, dma_addr_t mapping, int len)
> +{
> + struct tx_bd_short *prod_bd;
> +
> + prod_bd = (struct tx_bd_short *)BD_NOW(bp->tx.bd_virt,
> + entry,
> + sizeof(struct tx_bd_short));
> + if (len < 512)
> + prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_LT512;
> + else if (len < 1024)
> + prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_LT1K;
> + else if (len < 2048)
> + prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_LT2K;
> + else
> + prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_GTE2K;
> +
> + prod_bd->flags_type |= TX_BD_FLAGS;
> + prod_bd->dma.addr = mapping;
> + prod_bd->len = len;
> + prod_bd->opaque = (u32)entry;
> + dump_tx_bd(prod_bd, (u16)(sizeof(struct tx_bd_short)));
> +}
> +
> +static void bnxt_tx_complete(struct bnxt *bp)
> +{
> + bp->tx.cons_id = NEXT_IDX(bp->tx.cons_id, bp->tx.ring_cnt);
> + bp->tx.cnt++;
> + dump_tx_stat(bp);
> +}
> +
> +int post_rx_buffers(struct bnxt *bp)
> +{
> + u16 cons_id = (bp->rx.cons_idx % bp->rx.ring_cnt);
> + u16 iob_idx;
> +
> + while (bp->rx.iob_cnt < bp->rx.buf_cnt) {
> + iob_idx = (cons_id % bp->rx.buf_cnt);
> + if (!bp->rx.iob[iob_idx]) {
> + if (bnxt_alloc_rx_iob(bp, cons_id, iob_idx) < 0) {
> + dbg_rx_alloc_iob_fail(iob_idx, cons_id);
> + break;
> + }
> + }
> +
> + cons_id = NEXT_IDX(cons_id, bp->rx.ring_cnt);
> + bp->rx.iob_cnt++;
> + }
> +
> + if (cons_id != bp->rx.cons_idx) {
> + dbg_rx_cid(bp->rx.cons_idx, cons_id);
> + bp->rx.cons_idx = cons_id;
> + bnxt_db_rx(bp, (u32)cons_id);
> + }
> +
> + FLAG_SET(bp->flag_hwrm, VALID_RX_IOB);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +u8 bnxt_rx_drop(struct bnxt *bp, u8 *rx_buf, struct rx_pkt_cmpl_hi *rx_cmp_hi)
> +{
> + u8 chksum_err = 0;
> + u8 i;
> + u16 error_flags;
> +
> + error_flags = (rx_cmp_hi->errors_v2 >>
> + RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT);
> + if (rx_cmp_hi->errors_v2 == 0x20 || rx_cmp_hi->errors_v2 == 0x21)
> + chksum_err = 1;
> +
> + if (error_flags && !chksum_err) {
> + bp->rx.err++;
> + return 1;
> + }
> +
> + for (i = 0; i < 6; i++) {
> + if (rx_buf[6 + i] != bp->mac_set[i])
> + break;
> + }
> +
> + if (i == 6) {
> + bp->rx.dropped++;
> + return 2; /* Drop the loopback packets */
> + }
> +
> + return 0;
> +}
> +
> +static void bnxt_adv_cq_index(struct bnxt *bp, u16 count)
> +{
> + u16 cons_idx = bp->cq.cons_idx + count;
> +
> + if (cons_idx >= MAX_CQ_DESC_CNT) {
> + /* Toggle completion bit when the ring wraps. */
> + bp->cq.completion_bit ^= 1;
> + cons_idx = cons_idx - MAX_CQ_DESC_CNT;
> + }
> +
> + bp->cq.cons_idx = cons_idx;
> +}
> +
> +void bnxt_adv_rx_index(struct bnxt *bp, u8 *iob, u32 iob_idx)
> +{
> + u16 cons_id = (bp->rx.cons_idx % bp->rx.ring_cnt);
> +
> + set_rx_desc((u8 *)bp->rx.bd_virt, (void *)iob, cons_id, iob_idx);
> + cons_id = NEXT_IDX(cons_id, bp->rx.ring_cnt);
> + if (cons_id != bp->rx.cons_idx) {
> + dbg_rx_cid(bp->rx.cons_idx, cons_id);
> + bp->rx.cons_idx = cons_id;
> + bnxt_db_rx(bp, (u32)cons_id);
> + }
> +}
> +
> +void rx_process(struct bnxt *bp, struct rx_pkt_cmpl *rx_cmp,
> + struct rx_pkt_cmpl_hi *rx_cmp_hi)
> +{
> + u32 desc_idx = rx_cmp->opaque;
> + u8 *iob = bp->rx.iob[desc_idx];
> +
> + dump_rx_bd(rx_cmp, rx_cmp_hi, desc_idx);
> + bp->rx.iob_len = rx_cmp->len;
> + bp->rx.iob_rx = iob;
> + if (bnxt_rx_drop(bp, iob, rx_cmp_hi))
> + bp->rx.iob_recv = PKT_DROPPED;
> + else
> + bp->rx.iob_recv = PKT_RECEIVED;
> +
> + bp->rx.rx_cnt++;
> +
> + dbg_rxp(bp->rx.iob_rx, bp->rx.iob_len, bp->rx.iob_recv);
> + bnxt_adv_rx_index(bp, iob, desc_idx);
> + bnxt_adv_cq_index(bp, 2); /* Rx completion is 2 entries. */
> +}
> +
> +static int bnxt_rx_complete(struct bnxt *bp, struct rx_pkt_cmpl *rx_cmp)
> +{
> + struct rx_pkt_cmpl_hi *rx_cmp_hi;
> + u8 completion_bit = bp->cq.completion_bit;
> +
> + if (bp->cq.cons_idx == (bp->cq.ring_cnt - 1)) {
> + rx_cmp_hi = (struct rx_pkt_cmpl_hi *)bp->cq.bd_virt;
> + completion_bit ^= 0x1; /* Ring has wrapped. */
> + } else {
> + rx_cmp_hi = (struct rx_pkt_cmpl_hi *)(rx_cmp + 1);
> + }
> +
> + if (!((rx_cmp_hi->errors_v2 & RX_PKT_CMPL_V2) ^ completion_bit))
> + rx_process(bp, rx_cmp, rx_cmp_hi);
> +
> + return NO_MORE_CQ_BD_TO_SERVICE;
> +}
> +
> +static int bnxt_hwrm_ver_get(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_ver_get_input);
> + struct hwrm_ver_get_input *req;
> + struct hwrm_ver_get_output *resp;
> + int rc;
> +
> + req = (struct hwrm_ver_get_input *)bp->hwrm_addr_req;
> + resp = (struct hwrm_ver_get_output *)bp->hwrm_addr_resp;
> + hwrm_init(bp, (void *)req, (u16)HWRM_VER_GET, cmd_len);
> + req->hwrm_intf_maj = HWRM_VERSION_MAJOR;
> + req->hwrm_intf_min = HWRM_VERSION_MINOR;
> + req->hwrm_intf_upd = HWRM_VERSION_UPDATE;
> + rc = wait_resp(bp, HWRM_CMD_DEFAULT_TIMEOUT, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + bp->hwrm_spec_code =
> + resp->hwrm_intf_maj_8b << 16 |
> + resp->hwrm_intf_min_8b << 8 |
> + resp->hwrm_intf_upd_8b;
> + bp->hwrm_cmd_timeout = (u32)resp->def_req_timeout;
> + if (!bp->hwrm_cmd_timeout)
> + bp->hwrm_cmd_timeout = (u32)HWRM_CMD_DEFAULT_TIMEOUT;
> +
> + if (resp->hwrm_intf_maj_8b >= 1)
> + bp->hwrm_max_req_len = resp->max_req_win_len;
> +
> + bp->chip_id =
> + resp->chip_rev << 24 |
> + resp->chip_metal << 16 |
> + resp->chip_bond_id << 8 |
> + resp->chip_platform_type;
> + bp->chip_num = resp->chip_num;
> + test_if((resp->dev_caps_cfg & SHORT_CMD_SUPPORTED) &&
> + (resp->dev_caps_cfg & SHORT_CMD_REQUIRED))
> + FLAG_SET(bp->flags, BNXT_FLAG_HWRM_SHORT_CMD_SUPP);
> +
> + bp->hwrm_max_ext_req_len = resp->max_ext_req_len;
> + bp->fw_maj = resp->hwrm_fw_maj_8b;
> + bp->fw_min = resp->hwrm_fw_min_8b;
> + bp->fw_bld = resp->hwrm_fw_bld_8b;
> + bp->fw_rsvd = resp->hwrm_fw_rsvd_8b;
> + print_fw_ver(resp, bp->hwrm_cmd_timeout);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +/* Broadcom ethernet driver Function HW cmds APIs. */
> +static int bnxt_hwrm_func_resource_qcaps(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_func_resource_qcaps_input);
> + struct hwrm_func_resource_qcaps_input *req;
> + struct hwrm_func_resource_qcaps_output *resp;
> + int rc;
> +
> + req = (struct hwrm_func_resource_qcaps_input *)bp->hwrm_addr_req;
> + resp = (struct hwrm_func_resource_qcaps_output *)bp->hwrm_addr_resp;
> + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_RESOURCE_QCAPS, cmd_len);
> + req->fid = (u16)HWRM_NA_SIGNATURE;
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc != STATUS_SUCCESS)
> + return STATUS_SUCCESS;
> +
> + FLAG_SET(bp->flags, BNXT_FLAG_RESOURCE_QCAPS_SUPPORT);
> + /* VFs */
> + bp->max_vfs = resp->max_vfs;
> + bp->vf_res_strategy = resp->vf_reservation_strategy;
> + /* vNICs */
> + bp->min_vnics = resp->min_vnics;
> + bp->max_vnics = resp->max_vnics;
> + /* MSI-X */
> + bp->max_msix = resp->max_msix;
> + /* Ring Groups */
> + bp->min_hw_ring_grps = resp->min_hw_ring_grps;
> + bp->max_hw_ring_grps = resp->max_hw_ring_grps;
> + /* TX Rings */
> + bp->min_tx_rings = resp->min_tx_rings;
> + bp->max_tx_rings = resp->max_tx_rings;
> + /* RX Rings */
> + bp->min_rx_rings = resp->min_rx_rings;
> + bp->max_rx_rings = resp->max_rx_rings;
> + /* Completion Rings */
> + bp->min_cp_rings = resp->min_cmpl_rings;
> + bp->max_cp_rings = resp->max_cmpl_rings;
> + /* RSS Contexts */
> + bp->min_rsscos_ctxs = resp->min_rsscos_ctx;
> + bp->max_rsscos_ctxs = resp->max_rsscos_ctx;
> + /* L2 Contexts */
> + bp->min_l2_ctxs = resp->min_l2_ctxs;
> + bp->max_l2_ctxs = resp->max_l2_ctxs;
> + /* Statistic Contexts */
> + bp->min_stat_ctxs = resp->min_stat_ctx;
> + bp->max_stat_ctxs = resp->max_stat_ctx;
> + dbg_func_resource_qcaps(bp);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static u32 set_ring_info(struct bnxt *bp)
> +{
> + u32 enables = 0;
> +
> + bp->num_cmpl_rings = DEFAULT_NUMBER_OF_CMPL_RINGS;
> + bp->num_tx_rings = DEFAULT_NUMBER_OF_TX_RINGS;
> + bp->num_rx_rings = DEFAULT_NUMBER_OF_RX_RINGS;
> + bp->num_hw_ring_grps = DEFAULT_NUMBER_OF_RING_GRPS;
> + bp->num_stat_ctxs = DEFAULT_NUMBER_OF_STAT_CTXS;
> + if (bp->min_cp_rings <= DEFAULT_NUMBER_OF_CMPL_RINGS)
> + bp->num_cmpl_rings = bp->min_cp_rings;
> +
> + if (bp->min_tx_rings <= DEFAULT_NUMBER_OF_TX_RINGS)
> + bp->num_tx_rings = bp->min_tx_rings;
> +
> + if (bp->min_rx_rings <= DEFAULT_NUMBER_OF_RX_RINGS)
> + bp->num_rx_rings = bp->min_rx_rings;
> +
> + if (bp->min_hw_ring_grps <= DEFAULT_NUMBER_OF_RING_GRPS)
> + bp->num_hw_ring_grps = bp->min_hw_ring_grps;
> +
> + if (bp->min_stat_ctxs <= DEFAULT_NUMBER_OF_STAT_CTXS)
> + bp->num_stat_ctxs = bp->min_stat_ctxs;
> +
> + print_num_rings(bp);
> + enables = (FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
> + FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS |
> + FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS |
> + FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS |
> + FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS);
> +
> + return enables;
> +}
> +
> +static void bnxt_hwrm_assign_resources(struct bnxt *bp)
> +{
> + struct hwrm_func_cfg_input *req;
> + u32 enables = 0;
> +
> + if (FLAG_TEST(bp->flags, BNXT_FLAG_RESOURCE_QCAPS_SUPPORT))
> + enables = set_ring_info(bp);
> +
> + req = (struct hwrm_func_cfg_input *)bp->hwrm_addr_req;
> + req->num_cmpl_rings = bp->num_cmpl_rings;
> + req->num_tx_rings = bp->num_tx_rings;
> + req->num_rx_rings = bp->num_rx_rings;
> + req->num_stat_ctxs = bp->num_stat_ctxs;
> + req->num_hw_ring_grps = bp->num_hw_ring_grps;
> + req->enables = enables;
> +}
> +
> +int bnxt_hwrm_nvm_flush(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_nvm_flush_input);
> + struct hwrm_nvm_flush_input *req;
> + int rc;
> +
> + req = (struct hwrm_nvm_flush_input *)bp->hwrm_addr_req;
> +
> + hwrm_init(bp, (void *)req, (u16)HWRM_NVM_FLUSH, cmd_len);
> +
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_func_qcaps_req(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_func_qcaps_input);
> + struct hwrm_func_qcaps_input *req;
> + struct hwrm_func_qcaps_output *resp;
> + int rc;
> +
> + req = (struct hwrm_func_qcaps_input *)bp->hwrm_addr_req;
> + resp = (struct hwrm_func_qcaps_output *)bp->hwrm_addr_resp;
> + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_QCAPS, cmd_len);
> + req->fid = (u16)HWRM_NA_SIGNATURE;
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + bp->fid = resp->fid;
> + bp->port_idx = (u8)resp->port_id;
> +
> + /* Get MAC address for this PF */
> + memcpy(&bp->mac_addr[0], &resp->mac_address[0], ETH_ALEN);
> +
> + memcpy(&bp->mac_set[0], &bp->mac_addr[0], ETH_ALEN);
> +
> + print_func_qcaps(bp);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_func_qcfg_req(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_func_qcfg_input);
> + struct hwrm_func_qcfg_input *req;
> + struct hwrm_func_qcfg_output *resp;
> + int rc;
> +
> + req = (struct hwrm_func_qcfg_input *)bp->hwrm_addr_req;
> + resp = (struct hwrm_func_qcfg_output *)bp->hwrm_addr_resp;
> + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_QCFG, cmd_len);
> + req->fid = (u16)HWRM_NA_SIGNATURE;
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + if (resp->flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)
> + FLAG_SET(bp->flags, BNXT_FLAG_MULTI_HOST);
> +
> + if (resp->port_partition_type &
> + FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0)
> + FLAG_SET(bp->flags, BNXT_FLAG_NPAR_MODE);
> +
> + bp->ordinal_value = (u8)resp->pci_id & 0x0F;
> + bp->stat_ctx_id = resp->stat_ctx_id;
> + memcpy(&bp->mac_addr[0], &resp->mac_address[0], ETH_ALEN);
> + print_func_qcfg(bp);
> + dbg_flags(__func__, bp->flags);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_func_reset_req(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_func_reset_input);
> + struct hwrm_func_reset_input *req;
> +
> + req = (struct hwrm_func_reset_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_RESET, cmd_len);
> + req->func_reset_level = FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME;
> +
> + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> +}
> +
> +static int bnxt_hwrm_func_cfg_req(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_func_cfg_input);
> + struct hwrm_func_cfg_input *req;
> +
> + req = (struct hwrm_func_cfg_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_CFG, cmd_len);
> + req->fid = (u16)HWRM_NA_SIGNATURE;
> + bnxt_hwrm_assign_resources(bp);
> +
> + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> +}
> +
> +static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_func_drv_rgtr_input);
> + struct hwrm_func_drv_rgtr_input *req;
> + int rc;
> +
> + req = (struct hwrm_func_drv_rgtr_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_DRV_RGTR, cmd_len);
> + /* Register with HWRM */
> + req->enables = FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
> + FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD |
> + FUNC_DRV_RGTR_REQ_ENABLES_VER;
> + req->async_event_fwd[0] |= 0x01;
> + req->os_type = FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER;
> + req->ver_maj = UBOOT_VERSION_MAJOR;
> + req->ver_min = UBOOT_VERSION_MINOR;
> + req->ver_upd = UBOOT_VERSION_UPDATE;
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + FLAG_SET(bp->flag_hwrm, VALID_DRIVER_REG);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_func_drv_unrgtr_input);
> + struct hwrm_func_drv_unrgtr_input *req;
> + int rc;
> +
> + if (!(FLAG_TEST(bp->flag_hwrm, VALID_DRIVER_REG)))
> + return STATUS_SUCCESS;
> +
> + req = (struct hwrm_func_drv_unrgtr_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_DRV_UNRGTR, cmd_len);
> + req->flags = FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN;
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + FLAG_RESET(bp->flag_hwrm, VALID_DRIVER_REG);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_cfa_l2_filter_alloc(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_cfa_l2_filter_alloc_input);
> + struct hwrm_cfa_l2_filter_alloc_input *req;
> + struct hwrm_cfa_l2_filter_alloc_output *resp;
> + int rc;
> + u32 flags = CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX;
> + u32 enables;
> +
> + req = (struct hwrm_cfa_l2_filter_alloc_input *)bp->hwrm_addr_req;
> + resp = (struct hwrm_cfa_l2_filter_alloc_output *)bp->hwrm_addr_resp;
> + enables = CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
> + CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
> + CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK;
> +
> + hwrm_init(bp, (void *)req, (u16)HWRM_CFA_L2_FILTER_ALLOC, cmd_len);
> + req->flags = flags;
> + req->enables = enables;
> + memcpy((char *)&req->l2_addr[0], (char *)&bp->mac_set[0], ETH_ALEN);
> + memset((char *)&req->l2_addr_mask[0], 0xff, ETH_ALEN);
> + memcpy((char *)&req->t_l2_addr[0], (char *)&bp->mac_set[0], ETH_ALEN);
> + memset((char *)&req->t_l2_addr_mask[0], 0xff, ETH_ALEN);
> + req->src_type = CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT;
> + req->src_id = (u32)bp->port_idx;
> + req->dst_id = bp->vnic_id;
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + FLAG_SET(bp->flag_hwrm, VALID_L2_FILTER);
> + bp->l2_filter_id = resp->l2_filter_id;
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_cfa_l2_filter_free(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_cfa_l2_filter_free_input);
> + struct hwrm_cfa_l2_filter_free_input *req;
> + int rc;
> +
> + if (!(FLAG_TEST(bp->flag_hwrm, VALID_L2_FILTER)))
> + return STATUS_SUCCESS;
> +
> + req = (struct hwrm_cfa_l2_filter_free_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_CFA_L2_FILTER_FREE, cmd_len);
> + req->l2_filter_id = bp->l2_filter_id;
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + FLAG_RESET(bp->flag_hwrm, VALID_L2_FILTER);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +u32 bnxt_set_rx_mask(u32 rx_mask)
> +{
> + u32 mask = 0;
> +
> + if (!rx_mask)
> + return mask;
> + mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
> + if (rx_mask != RX_MASK_ACCEPT_NONE) {
> + if (rx_mask & RX_MASK_ACCEPT_MULTICAST)
> + mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
> +
> + if (rx_mask & RX_MASK_ACCEPT_ALL_MULTICAST)
> + mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
> +
> + if (rx_mask & RX_MASK_PROMISCUOUS_MODE)
> + mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
> + }
> +
> + return mask;
> +}
> +
> +static int bnxt_hwrm_set_rx_mask(struct bnxt *bp, u32 rx_mask)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_cfa_l2_set_rx_mask_input);
> + struct hwrm_cfa_l2_set_rx_mask_input *req;
> + u32 mask = bnxt_set_rx_mask(rx_mask);
> +
> + req = (struct hwrm_cfa_l2_set_rx_mask_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_CFA_L2_SET_RX_MASK, cmd_len);
> + req->vnic_id = bp->vnic_id;
> + req->mask = mask;
> +
> + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> +}
> +
> +static int bnxt_hwrm_port_mac_cfg(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_port_mac_cfg_input);
> + struct hwrm_port_mac_cfg_input *req;
> +
> + req = (struct hwrm_port_mac_cfg_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_PORT_MAC_CFG, cmd_len);
> + req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
> +
> + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> +}
> +
> +static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp, u16 idx)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_port_phy_qcfg_input);
> + struct hwrm_port_phy_qcfg_input *req;
> + struct hwrm_port_phy_qcfg_output *resp;
> + int rc;
> +
> + req = (struct hwrm_port_phy_qcfg_input *)bp->hwrm_addr_req;
> + resp = (struct hwrm_port_phy_qcfg_output *)bp->hwrm_addr_resp;
> + hwrm_init(bp, (void *)req, (u16)HWRM_PORT_PHY_QCFG, cmd_len);
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + if (idx & SUPPORT_SPEEDS)
> + bp->support_speeds = resp->support_speeds;
> +
> + if (idx & DETECT_MEDIA)
> + bp->media_detect = resp->module_status;
> +
> + if (idx & PHY_SPEED)
> + bp->current_link_speed = resp->link_speed;
> +
> + if (idx & PHY_STATUS) {
> + if (resp->link == PORT_PHY_QCFG_RESP_LINK_LINK)
> + bp->link_status = STATUS_LINK_ACTIVE;
> + else
> + bp->link_status = STATUS_LINK_DOWN;
> + }
> +
> + return STATUS_SUCCESS;
> +}
> +
> +u16 set_link_speed_mask(u16 link_cap)
> +{
> + u16 speed_mask = 0;
> +
> + if (link_cap & SPEED_CAPABILITY_DRV_100M)
> + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB;
> +
> + if (link_cap & SPEED_CAPABILITY_DRV_1G)
> + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB;
> +
> + if (link_cap & SPEED_CAPABILITY_DRV_10G)
> + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB;
> +
> + if (link_cap & SPEED_CAPABILITY_DRV_25G)
> + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB;
> +
> + if (link_cap & SPEED_CAPABILITY_DRV_40G)
> + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB;
> +
> + if (link_cap & SPEED_CAPABILITY_DRV_50G)
> + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB;
> +
> + if (link_cap & SPEED_CAPABILITY_DRV_100G)
> + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB;
> +
> + return speed_mask;
> +}
> +
> +static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_port_phy_cfg_input);
> + struct hwrm_port_phy_cfg_input *req;
> + u32 flags;
> + u32 enables = 0;
> + u16 force_link_speed = 0;
> + u16 auto_link_speed_mask = 0;
> + u8 auto_mode = 0;
> + u8 auto_pause = 0;
> + u8 auto_duplex = 0;
> +
> + /*
> + * If multi_host or NPAR is set to TRUE,
> + * do not issue hwrm_port_phy_cfg
> + */
> + if (FLAG_TEST(bp->flags, PORT_PHY_FLAGS)) {
> + dbg_flags(__func__, bp->flags);
> + return STATUS_SUCCESS;
> + }
> +
> + req = (struct hwrm_port_phy_cfg_input *)bp->hwrm_addr_req;
> + flags = PORT_PHY_CFG_REQ_FLAGS_FORCE |
> + PORT_PHY_CFG_REQ_FLAGS_RESET_PHY;
> +
> + switch (GET_MEDIUM_SPEED(bp->medium)) {
> + case MEDIUM_SPEED_1000MBPS:
> + force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
> + break;
> + case MEDIUM_SPEED_10GBPS:
> + force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
> + break;
> + case MEDIUM_SPEED_25GBPS:
> + force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
> + break;
> + case MEDIUM_SPEED_40GBPS:
> + force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
> + break;
> + case MEDIUM_SPEED_50GBPS:
> + force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
> + break;
> + case MEDIUM_SPEED_100GBPS:
> + force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
> + break;
> + default:
> + /* Enable AUTONEG by default */
> + auto_mode = PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
> + flags &= ~PORT_PHY_CFG_REQ_FLAGS_FORCE;
> + enables |= PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE |
> + PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK |
> + PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX |
> + PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE;
> + auto_pause = PORT_PHY_CFG_REQ_AUTO_PAUSE_TX |
> + PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
> + auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH;
> + auto_link_speed_mask = bp->support_speeds;
> + break;
> + }
> +
> + hwrm_init(bp, (void *)req, (u16)HWRM_PORT_PHY_CFG, cmd_len);
> + req->flags = flags;
> + req->enables = enables;
> + req->port_id = bp->port_idx;
> + req->force_link_speed = force_link_speed;
> + req->auto_mode = auto_mode;
> + req->auto_duplex = auto_duplex;
> + req->auto_pause = auto_pause;
> + req->auto_link_speed_mask = auto_link_speed_mask;
> +
> + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> +}
> +
> +static int bnxt_qphy_link(struct bnxt *bp)
> +{
> + u16 flag = QCFG_PHY_ALL;
> +
> + /* Query Link Status */
> + if (bnxt_hwrm_port_phy_qcfg(bp, flag) != STATUS_SUCCESS)
> + return STATUS_FAILURE;
> +
> + if (bp->link_status != STATUS_LINK_ACTIVE) {
> + /*
> + * Configure link if it is not up.
> + * try to bring link up, but don't return
> + * failure if port_phy_cfg() fails
> + */
> + bnxt_hwrm_port_phy_cfg(bp);
> + /* refresh link speed values after bringing link up */
> + if (bnxt_hwrm_port_phy_qcfg(bp, flag) != STATUS_SUCCESS)
> + return STATUS_FAILURE;
> + }
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_stat_ctx_alloc_input);
> + struct hwrm_stat_ctx_alloc_input *req;
> + struct hwrm_stat_ctx_alloc_output *resp;
> + int rc;
> +
> + req = (struct hwrm_stat_ctx_alloc_input *)bp->hwrm_addr_req;
> + resp = (struct hwrm_stat_ctx_alloc_output *)bp->hwrm_addr_resp;
> + hwrm_init(bp, (void *)req, (u16)HWRM_STAT_CTX_ALLOC, cmd_len);
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + FLAG_SET(bp->flag_hwrm, VALID_STAT_CTX);
> + bp->stat_ctx_id = (u16)resp->stat_ctx_id;
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_stat_ctx_free_input);
> + struct hwrm_stat_ctx_free_input *req;
> + int rc;
> +
> + if (!(FLAG_TEST(bp->flag_hwrm, VALID_STAT_CTX)))
> + return STATUS_SUCCESS;
> +
> + req = (struct hwrm_stat_ctx_free_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_STAT_CTX_FREE, cmd_len);
> + req->stat_ctx_id = (u32)bp->stat_ctx_id;
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + FLAG_RESET(bp->flag_hwrm, VALID_STAT_CTX);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_ring_free_grp(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_ring_grp_free_input);
> + struct hwrm_ring_grp_free_input *req;
> + int rc;
> +
> + if (!(FLAG_TEST(bp->flag_hwrm, VALID_RING_GRP)))
> + return STATUS_SUCCESS;
> +
> + req = (struct hwrm_ring_grp_free_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_RING_GRP_FREE, cmd_len);
> + req->ring_group_id = (u32)bp->ring_grp_id;
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + FLAG_RESET(bp->flag_hwrm, VALID_RING_GRP);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_ring_alloc_grp(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_ring_grp_alloc_input);
> + struct hwrm_ring_grp_alloc_input *req;
> + struct hwrm_ring_grp_alloc_output *resp;
> + int rc;
> +
> + req = (struct hwrm_ring_grp_alloc_input *)bp->hwrm_addr_req;
> + resp = (struct hwrm_ring_grp_alloc_output *)bp->hwrm_addr_resp;
> + hwrm_init(bp, (void *)req, (u16)HWRM_RING_GRP_ALLOC, cmd_len);
> + req->cr = bp->cq_ring_id;
> + req->rr = bp->rx_ring_id;
> + req->ar = (u16)HWRM_NA_SIGNATURE;
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + FLAG_SET(bp->flag_hwrm, VALID_RING_GRP);
> + bp->ring_grp_id = (u16)resp->ring_group_id;
> +
> + return STATUS_SUCCESS;
> +}
> +
> +int bnxt_hwrm_ring_free(struct bnxt *bp, u16 ring_id, u8 ring_type)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_ring_free_input);
> + struct hwrm_ring_free_input *req;
> +
> + req = (struct hwrm_ring_free_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_RING_FREE, cmd_len);
> + req->ring_type = ring_type;
> + req->ring_id = ring_id;
> +
> + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> +}
> +
> +static int bnxt_hwrm_ring_alloc(struct bnxt *bp,
> + dma_addr_t ring_map,
> + u16 length,
> + u16 ring_id,
> + u8 ring_type,
> + u8 int_mode)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_ring_alloc_input);
> + struct hwrm_ring_alloc_input *req;
> + struct hwrm_ring_alloc_output *resp;
> + int rc;
> +
> + req = (struct hwrm_ring_alloc_input *)bp->hwrm_addr_req;
> + resp = (struct hwrm_ring_alloc_output *)bp->hwrm_addr_resp;
> + hwrm_init(bp, (void *)req, (u16)HWRM_RING_ALLOC, cmd_len);
> + req->ring_type = ring_type;
> + req->page_tbl_addr = ring_map;
> + req->page_size = LM_PAGE_SIZE;
> + req->length = (u32)length;
> + req->cmpl_ring_id = ring_id;
> + req->int_mode = int_mode;
> + if (ring_type == RING_ALLOC_REQ_RING_TYPE_TX) {
> + req->queue_id = TX_RING_QID;
> + } else if (ring_type == RING_ALLOC_REQ_RING_TYPE_RX) {
> + req->queue_id = RX_RING_QID;
> + req->enables = RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID;
> + req->rx_buf_size = MAX_ETHERNET_PACKET_BUFFER_SIZE;
> + }
> +
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + if (ring_type == RING_ALLOC_REQ_RING_TYPE_L2_CMPL) {
> + FLAG_SET(bp->flag_hwrm, VALID_RING_CQ);
> + bp->cq_ring_id = resp->ring_id;
> + } else if (ring_type == RING_ALLOC_REQ_RING_TYPE_TX) {
> + FLAG_SET(bp->flag_hwrm, VALID_RING_TX);
> + bp->tx_ring_id = resp->ring_id;
> + } else if (ring_type == RING_ALLOC_REQ_RING_TYPE_RX) {
> + FLAG_SET(bp->flag_hwrm, VALID_RING_RX);
> + bp->rx_ring_id = resp->ring_id;
> + }
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_ring_alloc_cq(struct bnxt *bp)
> +{
> + return bnxt_hwrm_ring_alloc(bp,
> + virt_to_bus(bp->cq.bd_virt),
> + bp->cq.ring_cnt,
> + 0,
> + RING_ALLOC_REQ_RING_TYPE_L2_CMPL,
> + BNXT_CQ_INTR_MODE());
> +}
> +
> +static int bnxt_hwrm_ring_alloc_tx(struct bnxt *bp)
> +{
> + return bnxt_hwrm_ring_alloc(bp,
> + virt_to_bus(bp->tx.bd_virt),
> + bp->tx.ring_cnt, bp->cq_ring_id,
> + RING_ALLOC_REQ_RING_TYPE_TX,
> + BNXT_INTR_MODE());
> +}
> +
> +static int bnxt_hwrm_ring_alloc_rx(struct bnxt *bp)
> +{
> + return bnxt_hwrm_ring_alloc(bp,
> + virt_to_bus(bp->rx.bd_virt),
> + bp->rx.ring_cnt,
> + bp->cq_ring_id,
> + RING_ALLOC_REQ_RING_TYPE_RX,
> + BNXT_INTR_MODE());
> +}
> +
> +static int bnxt_hwrm_ring_free_cq(struct bnxt *bp)
> +{
> + int ret = STATUS_SUCCESS;
> +
> + if (!(FLAG_TEST(bp->flag_hwrm, VALID_RING_CQ)))
> + return ret;
> +
> + ret = RING_FREE(bp, bp->cq_ring_id, RING_FREE_REQ_RING_TYPE_L2_CMPL);
> + if (ret == STATUS_SUCCESS)
> + FLAG_RESET(bp->flag_hwrm, VALID_RING_CQ);
> +
> + return ret;
> +}
> +
> +static int bnxt_hwrm_ring_free_tx(struct bnxt *bp)
> +{
> + int ret = STATUS_SUCCESS;
> +
> + if (!(FLAG_TEST(bp->flag_hwrm, VALID_RING_TX)))
> + return ret;
> +
> + ret = RING_FREE(bp, bp->tx_ring_id, RING_FREE_REQ_RING_TYPE_TX);
> + if (ret == STATUS_SUCCESS)
> + FLAG_RESET(bp->flag_hwrm, VALID_RING_TX);
> +
> + return ret;
> +}
> +
> +static int bnxt_hwrm_ring_free_rx(struct bnxt *bp)
> +{
> + int ret = STATUS_SUCCESS;
> +
> + if (!(FLAG_TEST(bp->flag_hwrm, VALID_RING_RX)))
> + return ret;
> +
> + ret = RING_FREE(bp, bp->rx_ring_id, RING_FREE_REQ_RING_TYPE_RX);
> + if (ret == STATUS_SUCCESS)
> + FLAG_RESET(bp->flag_hwrm, VALID_RING_RX);
> +
> + return ret;
> +}
> +
> +static int bnxt_hwrm_vnic_alloc(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_vnic_alloc_input);
> + struct hwrm_vnic_alloc_input *req;
> + struct hwrm_vnic_alloc_output *resp;
> + int rc;
> +
> + req = (struct hwrm_vnic_alloc_input *)bp->hwrm_addr_req;
> + resp = (struct hwrm_vnic_alloc_output *)bp->hwrm_addr_resp;
> + hwrm_init(bp, (void *)req, (u16)HWRM_VNIC_ALLOC, cmd_len);
> + req->flags = VNIC_ALLOC_REQ_FLAGS_DEFAULT;
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + FLAG_SET(bp->flag_hwrm, VALID_VNIC_ID);
> + bp->vnic_id = resp->vnic_id;
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_vnic_free(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_vnic_free_input);
> + struct hwrm_vnic_free_input *req;
> + int rc;
> +
> + if (!(FLAG_TEST(bp->flag_hwrm, VALID_VNIC_ID)))
> + return STATUS_SUCCESS;
> +
> + req = (struct hwrm_vnic_free_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_VNIC_FREE, cmd_len);
> + req->vnic_id = bp->vnic_id;
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> + if (rc)
> + return STATUS_FAILURE;
> +
> + FLAG_RESET(bp->flag_hwrm, VALID_VNIC_ID);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_vnic_cfg(struct bnxt *bp)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_vnic_cfg_input);
> + struct hwrm_vnic_cfg_input *req;
> +
> + req = (struct hwrm_vnic_cfg_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_VNIC_CFG, cmd_len);
> + req->enables = VNIC_CFG_REQ_ENABLES_MRU;
> + req->mru = bp->mtu;
> + req->enables |= VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP;
> + req->dflt_ring_grp = bp->ring_grp_id;
> + req->vnic_id = bp->vnic_id;
> +
> + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> +}
> +
> +static int set_phy_speed(struct bnxt *bp)
> +{
> + char name[20];
> + char name1[30];
> + u16 flag = PHY_STATUS | PHY_SPEED | DETECT_MEDIA;
> +
> + /* Query Link Status */
> + if (bnxt_hwrm_port_phy_qcfg(bp, flag) != STATUS_SUCCESS)
> + return STATUS_FAILURE;
> +
> + switch (bp->current_link_speed) {
> + case PORT_PHY_QCFG_RESP_LINK_SPEED_100GB:
> + sprintf(name, "%s %s", str_100, str_gbps);
> + break;
> + case PORT_PHY_QCFG_RESP_LINK_SPEED_50GB:
> + sprintf(name, "%s %s", str_50, str_gbps);
> + break;
> + case PORT_PHY_QCFG_RESP_LINK_SPEED_40GB:
> + sprintf(name, "%s %s", str_40, str_gbps);
> + break;
> + case PORT_PHY_QCFG_RESP_LINK_SPEED_25GB:
> + sprintf(name, "%s %s", str_25, str_gbps);
> + break;
> + case PORT_PHY_QCFG_RESP_LINK_SPEED_20GB:
> + sprintf(name, "%s %s", str_20, str_gbps);
> + break;
> + case PORT_PHY_QCFG_RESP_LINK_SPEED_10GB:
> + sprintf(name, "%s %s", str_10, str_gbps);
> + break;
> + case PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB:
> + sprintf(name, "%s %s", str_2_5, str_gbps);
> + break;
> + case PORT_PHY_QCFG_RESP_LINK_SPEED_2GB:
> + sprintf(name, "%s %s", str_2, str_gbps);
> + break;
> + case PORT_PHY_QCFG_RESP_LINK_SPEED_1GB:
> + sprintf(name, "%s %s", str_1, str_gbps);
> + break;
> + case PORT_PHY_QCFG_RESP_LINK_SPEED_100MB:
> + sprintf(name, "%s %s", str_100, str_mbps);
> + break;
> + case PORT_PHY_QCFG_RESP_LINK_SPEED_10MB:
> + sprintf(name, "%s %s", str_10, str_mbps);
> + break;
> + default:
> + sprintf(name, "%s %x", str_unknown, bp->current_link_speed);
> + }
> +
> + sprintf(name1, "bnxt_eth%u_phy_speed", bp->cardnum);
> + env_set(name1, name);
> + dbg_phy_speed(bp, name);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int set_phy_link(struct bnxt *bp, u32 tmo)
> +{
> + char name[32];
> + int ret;
> +
> + set_phy_speed(bp);
> + dbg_link_status(bp);
> + if (bp->link_status == STATUS_LINK_ACTIVE) {
> + dbg_link_state(bp, tmo);
> + sprintf(name, "bnxt_eth%u_link", bp->cardnum);
> + env_set(name, "up");
> + sprintf(name, "bnxt_eth%u_media", bp->cardnum);
> + env_set(name, "connected");
> + ret = STATUS_SUCCESS;
> + } else {
> + sprintf(name, "bnxt_eth%u_link", bp->cardnum);
> + env_set(name, "down");
> + sprintf(name, "bnxt_eth%u_media", bp->cardnum);
> + env_set(name, "disconnected");
> + ret = STATUS_FAILURE;
> + }
> +
> + return ret;
> +}
> +
> +static int get_phy_link(struct bnxt *bp)
> +{
> + u16 flag = PHY_STATUS | PHY_SPEED | DETECT_MEDIA;
> +
> + dbg_chip_info(bp);
> + /* Query Link Status */
> + if (bnxt_hwrm_port_phy_qcfg(bp, flag) != STATUS_SUCCESS)
> + return STATUS_FAILURE;
> +
> + set_phy_link(bp, 100);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_hwrm_set_async_event(struct bnxt *bp)
> +{
> + int rc;
> + u16 cmd_len = (u16)sizeof(struct hwrm_func_cfg_input);
> + struct hwrm_func_cfg_input *req;
> +
> + req = (struct hwrm_func_cfg_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_CFG, cmd_len);
> + req->fid = (u16)HWRM_NA_SIGNATURE;
> + req->enables = FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR;
> + req->async_event_cr = bp->cq_ring_id;
> + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
> +
> + return rc;
> +}
> +
> +int bnxt_hwrm_get_nvmem(struct bnxt *bp,
> + u16 data_len,
> + u16 option_num,
> + u16 dimensions,
> + u16 index_0)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_nvm_get_variable_input);
> + struct hwrm_nvm_get_variable_input *req;
> +
> + req = (struct hwrm_nvm_get_variable_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_NVM_GET_VARIABLE, cmd_len);
> + req->dest_data_addr = bp->data_addr_mapping;
> + req->data_len = data_len;
> + req->option_num = option_num;
> + req->dimensions = dimensions;
> + req->index_0 = index_0;
> +
> + return wait_resp(bp,
> + HWRM_CMD_FLASH_MULTIPLAYER(bp->hwrm_cmd_timeout),
> + cmd_len,
> + __func__);
> +}
> +
> +static void set_medium(struct bnxt *bp)
> +{
> + switch (bp->link_set & LINK_SPEED_DRV_MASK) {
> + case LINK_SPEED_DRV_1G:
> + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_1000MBPS);
> + break;
> + case LINK_SPEED_DRV_2_5G:
> + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_2500MBPS);
> + break;
> + case LINK_SPEED_DRV_10G:
> + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_10GBPS);
> + break;
> + case LINK_SPEED_DRV_25G:
> + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_25GBPS);
> + break;
> + case LINK_SPEED_DRV_40G:
> + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_40GBPS);
> + break;
> + case LINK_SPEED_DRV_50G:
> + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_50GBPS);
> + break;
> + case LINK_SPEED_DRV_100G:
> + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_100GBPS);
> + break;
> + case LINK_SPEED_DRV_200G:
> + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_200GBPS);
> + break;
> + case LINK_SPEED_DRV_AUTONEG:
> + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_AUTONEG);
> + break;
> + default:
> + bp->medium = SET_MEDIUM_DUPLEX(bp, MEDIUM_FULL_DUPLEX);
> + break;
> + }
> +}
> +
> +static int bnxt_hwrm_get_link_speed(struct bnxt *bp)
> +{
> + u32 *ptr32 = (u32 *)bp->hwrm_addr_data;
> +
> + if (bnxt_hwrm_get_nvmem(bp,
> + 4,
> + (u16)LINK_SPEED_DRV_NUM,
> + 1,
> + (u16)bp->port_idx) != STATUS_SUCCESS)
> + return STATUS_FAILURE;
> +
> + bp->link_set = *ptr32;
> + bp->link_set &= SPEED_DRV_MASK;
> + set_medium(bp);
> +
> + return STATUS_SUCCESS;
> +}
> +
> +typedef int (*hwrm_func_t)(struct bnxt *bp);
> +
> +hwrm_func_t down_chip[] = {
> + bnxt_hwrm_cfa_l2_filter_free, /* Free l2 filter */
> + bnxt_free_rx_iob, /* Free rx iob */
> + bnxt_hwrm_vnic_free, /* Free vnic */
> + bnxt_hwrm_ring_free_grp, /* Free ring group */
> + bnxt_hwrm_ring_free_rx, /* Free rx ring */
> + bnxt_hwrm_ring_free_tx, /* Free tx ring */
> + bnxt_hwrm_ring_free_cq, /* Free CQ ring */
> + bnxt_hwrm_stat_ctx_free, /* Free Stat ctx */
> + bnxt_hwrm_func_drv_unrgtr, /* unreg driver */
> + NULL,
> +};
> +
> +hwrm_func_t bring_chip[] = {
> + bnxt_hwrm_ver_get, /* HWRM_VER_GET */
> + bnxt_hwrm_func_reset_req, /* HWRM_FUNC_RESET */
> + bnxt_hwrm_func_drv_rgtr, /* HWRM_FUNC_DRV_RGTR */
> + bnxt_hwrm_func_resource_qcaps, /* HWRM_FUNC_RESOURCE_QCAPS */
> + bnxt_hwrm_func_qcfg_req, /* HWRM_FUNC_QCFG */
> + bnxt_hwrm_func_qcaps_req, /* HWRM_FUNC_QCAPS */
> + bnxt_hwrm_get_link_speed, /* HWRM_NVM_GET_VARIABLE - 203 */
> + bnxt_hwrm_port_mac_cfg, /* HWRM_PORT_MAC_CFG */
> + bnxt_qphy_link, /* HWRM_PORT_PHY_QCFG */
> + bnxt_hwrm_func_cfg_req, /* HWRM_FUNC_CFG - ring resource*/
> + bnxt_hwrm_stat_ctx_alloc, /* Allocate Stat Ctx ID */
> + bnxt_hwrm_ring_alloc_cq, /* Allocate CQ Ring */
> + bnxt_hwrm_ring_alloc_tx, /* Allocate Tx ring */
> + bnxt_hwrm_ring_alloc_rx, /* Allocate Rx Ring */
> + bnxt_hwrm_ring_alloc_grp, /* Create Ring Group */
> + post_rx_buffers, /* Post RX buffers */
> + bnxt_hwrm_set_async_event, /* ENABLES_ASYNC_EVENT_CR */
> + bnxt_hwrm_vnic_alloc, /* Alloc VNIC */
> + bnxt_hwrm_vnic_cfg, /* Config VNIC */
> + bnxt_hwrm_cfa_l2_filter_alloc, /* Alloc L2 Filter */
> + get_phy_link, /* Get Physical Link */
> + NULL,
> +};
> +
> +int bnxt_hwrm_run(hwrm_func_t cmds[], struct bnxt *bp, int flag)
> +{
> + hwrm_func_t *ptr;
> + int ret;
> + int status = STATUS_SUCCESS;
> +
> + for (ptr = cmds; *ptr; ++ptr) {
> + ret = (*ptr)(bp);
> + if (ret) {
> + status = STATUS_FAILURE;
> + /* Continue till all cleanup routines are called */
> + if (flag)
> + return STATUS_FAILURE;
> + }
> + }
> +
> + return status;
> +}
> +
> +void print_mac(u8 *mac, u8 flag)
> +{
> + printf("bnxt ");
> + if (flag)
> + printf("Set");
> + else
> + printf("Get");
> +
> + printf(" MAC :");
> + printf(" %02x:%02x:%02x:", mac[0], mac[1], mac[2]);
> + printf("%02x:%02x:%02x\n", mac[3], mac[4], mac[5]);
> +}
> +
> +void bnxt_env_set_ethaddr(struct udevice *dev)
> +{
> + struct eth_pdata *plat = dev_get_plat(dev);
> + struct bnxt *bp = dev_get_priv(dev);
> + int secondary = 0;
> + char cmd[100];
> + char var[32];
> + u8 mac_env[ARP_HLEN];
> +
> + if (env_get("ethaddr"))
> + secondary = 1;
> +
> + eth_env_get_enetaddr_by_index("eth", bp->cardnum + secondary, mac_env);
> + if (!memcmp(plat->enetaddr, mac_env, ARP_HLEN))
> + return;
> +
> + sprintf(var, (bp->cardnum + secondary) ? "%s%daddr" : "%saddr", "eth",
> + bp->cardnum + secondary);
> + sprintf(cmd, "%s %s %pM", "env set -f", var, plat->enetaddr);
> + run_command(cmd, CMD_FLAG_ENV);
> + printf("\n");
> +}
> +
> +void bnxt_env_del_ethaddr(struct udevice *dev)
> +{
> + struct eth_pdata *plat = dev_get_plat(dev);
> + struct bnxt *bp = dev_get_priv(dev);
> + char cmd[100];
> + char var[32];
> + int secondary = 0;
> +
> + if (env_get("ethaddr"))
> + secondary = 1;
> +
> + sprintf(var, (bp->cardnum + secondary) ? "%s%daddr" : "%saddr", "eth",
> + bp->cardnum + secondary);
> + sprintf(cmd, "%s %s %pM", "env delete -f", var, plat->enetaddr);
> + run_command(cmd, CMD_FLAG_ENV);
> + printf("\n");
> +}
> +
> +int bnxt_get_mac(struct bnxt *bp)
> +{
> + print_mac(&bp->mac_set[0], 0);
> +
> + return CMD_RET_SUCCESS;
> +}
> +
> +void prn_link_speed(u32 speed, u8 flag)
> +{
> + u32 speed1 = ((speed & LINK_SPEED_DRV_MASK) >> LINK_SPEED_DRV_SHIFT);
> +
> + printf("bnxt ");
> + if (flag)
> + printf("Set");
> + else
> + printf("Get");
> +
> + printf(" Link Speed : ");
> + switch (speed & LINK_SPEED_DRV_MASK) {
> + case LINK_SPEED_DRV_1G:
> + printf("1 GBPS");
> + break;
> + case LINK_SPEED_DRV_2_5G:
> + printf("2.5 GBPS");
> + break;
> + case LINK_SPEED_DRV_10G:
> + printf("10 GBPS");
> + break;
> + case LINK_SPEED_DRV_25G:
> + printf("25 GBPS");
> + break;
> + case LINK_SPEED_DRV_40G:
> + printf("40 GBPS");
> + break;
> + case LINK_SPEED_DRV_50G:
> + printf("50 GBPS");
> + break;
> + case LINK_SPEED_DRV_100G:
> + printf("100 GBPS");
> + break;
> + case LINK_SPEED_DRV_200G:
> + printf("200 GBPS");
> + break;
> + case LINK_SPEED_DRV_AUTONEG:
> + printf("AUTONEG");
> + break;
> + default:
> + printf("%x", speed1);
> + break;
> + }
> +
> + printf("\n");
> +}
> +
> +int bnxt_get_link_speed(struct bnxt *bp)
> +{
> + if (bnxt_hwrm_get_link_speed(bp) == STATUS_SUCCESS)
> + prn_link_speed(bp->link_set, 0);
> +
> + return CMD_RET_SUCCESS;
> +}
> +
> +int bnxt_supported_speed(struct bnxt *bp)
> +{
> + if (bnxt_hwrm_port_phy_qcfg(bp, SUPPORT_SPEEDS) != STATUS_SUCCESS)
> + return CMD_RET_FAILURE;
> +
> + printf("bnxt - Supported speed\n\n");
> + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_1GB)
> + printf(" (1) - 1 GBPS\n");
> +
> + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_10GB)
> + printf(" (2) - 10 GBPS\n");
> +
> + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_25GB)
> + printf(" (3) - 25 GBPS\n");
> +
> + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_50GB)
> + printf(" (5) - 50 GBPS\n");
> +
> + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_100GB)
> + printf(" (6) - 100 GBPS\n");
> +
> + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_200GB)
> + printf(" (7) - 200 GBPS\n");
> +
> + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_2_5GB)
> + printf(" (E) - 2.5 GBPS\n");
> +
> + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_100MB)
> + printf(" (F) - 100 MBPS\n");
> +
> + return CMD_RET_SUCCESS;
> +}
> +
> +int bnxt_hwrm_set_nvmem(struct bnxt *bp,
> + u16 data_len,
> + u16 option_num,
> + u16 dimensions,
> + u16 index_0,
> + u8 flag)
> +{
> + u16 cmd_len = (u16)sizeof(struct hwrm_nvm_set_variable_input);
> + struct hwrm_nvm_set_variable_input *req;
> +
> + req = (struct hwrm_nvm_set_variable_input *)bp->hwrm_addr_req;
> + hwrm_init(bp, (void *)req, (u16)HWRM_NVM_SET_VARIABLE, cmd_len);
> + req->src_data_addr = bp->data_addr_mapping;
> + req->data_len = data_len;
> + req->option_num = option_num;
> + req->dimensions = dimensions;
> + req->index_0 = index_0;
> + req->flags = flag;
> +
> + return wait_resp(bp,
> + HWRM_CMD_FLASH_MULTIPLAYER(bp->hwrm_cmd_timeout),
> + cmd_len,
> + __func__);
> +}
> +
> +int bnxt_set_link_speed(struct bnxt *bp)
> +{
> + u32 *dma_buf32 = (u32 *)bp->hwrm_addr_data;
> +
> + memset(bp->hwrm_addr_data, 0, 8);
> + dma_buf32[0] = bp->link_set;
> + dma_buf32[1] = 0;
> + if (bnxt_hwrm_set_nvmem(bp,
> + 4,
> + (u16)LINK_SPEED_DRV_NUM,
> + 1,
> + (u16)bp->port_idx,
> + 0) != STATUS_SUCCESS)
> + return CMD_RET_FAILURE;
> +
> + memset(bp->hwrm_addr_data, 0, 8);
> + dma_buf32[0] = bp->link_set;
> + dma_buf32[1] = 0;
> + if (bnxt_hwrm_set_nvmem(bp,
> + 4,
> + (u16)LINK_SPEED_FW_NUM,
> + 1,
> + (u16)bp->port_idx,
> + 0) != STATUS_SUCCESS)
> + return CMD_RET_FAILURE;
> +
> + bnxt_hwrm_nvm_flush(bp);
> +
> + return CMD_RET_SUCCESS;
> +}
> +
> +int bnxt_set_mac(struct bnxt *bp)
> +{
> + u32 *dma_buf32 = (u32 *)bp->hwrm_addr_data;
> + u8 *dma_buf = (u8 *)bp->hwrm_addr_data;
> +
> + memset(bp->hwrm_addr_data, 0, 8);
> + memcpy(&dma_buf[2], &bp->mac_set[0], ETH_ALEN);
> + dma_buf32[0] = cpu_to_be32(dma_buf32[0]);
> + dma_buf32[1] = cpu_to_be32(dma_buf32[1]);
> + if (bnxt_hwrm_set_nvmem(bp,
> + 64,
> + (u16)FUNC_MAC_ADDR_NUM,
> + 1,
> + (u16)bp->ordinal_value,
> + 0) != STATUS_SUCCESS)
> + return CMD_RET_FAILURE;
> +
> + return CMD_RET_SUCCESS;
> +}
> +
> +/* Broadcom ethernet driver Network interface APIs. */
> +static int bnxt_start(struct udevice *dev)
> +{
> + struct bnxt *bp = dev_get_priv(dev);
> +
> + if (bnxt_hwrm_set_rx_mask(bp, RX_MASK) != STATUS_SUCCESS)
> + return STATUS_FAILURE;
> +
> + bp->card_en = true;
> + return STATUS_SUCCESS;
> +}
> +
> +static int bnxt_send(struct udevice *dev, void *packet, int length)
> +{
> + struct bnxt *bp = dev_get_priv(dev);
> + int len;
> + u16 entry;
> + dma_addr_t mapping;
> +
> + if (bnxt_tx_avail(bp) < 1) {
> + dbg_no_tx_bd();
> + return -ENOBUFS;
> + }
> +
> + entry = bp->tx.prod_id;
> + len = iob_pad(packet, length);
> + mapping = virt_to_bus(packet);
> + set_txq(bp, entry, mapping, len);
> + entry = NEXT_IDX(entry, bp->tx.ring_cnt);
> + dump_tx_pkt(packet, mapping, len);
> + bnxt_db_tx(bp, (u32)entry);
> + bp->tx.prod_id = entry;
> + bp->tx.cnt_req++;
> + bnxt_tx_complete(bp);
> +
> + return 0;
> +}
> +
> +static void bnxt_link_evt(struct bnxt *bp, struct cmpl_base *cmp)
> +{
> + struct hwrm_async_event_cmpl *evt;
> +
> + evt = (struct hwrm_async_event_cmpl *)cmp;
> + switch (evt->event_id) {
> + case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
> + if (evt->event_data1 & 0x01)
> + bp->link_status = STATUS_LINK_ACTIVE;
> + else
> + bp->link_status = STATUS_LINK_DOWN;
> +
> + set_phy_link(bp, 0);
> + break;
> + default:
> + break;
> + }
> +}
> +
> +static int bnxt_recv(struct udevice *dev, int flags, uchar **packetp)
> +{
> + struct bnxt *bp = dev_get_priv(dev);
> + struct cmpl_base *cmp;
> + u16 old_cons_idx = bp->cq.cons_idx;
> + int done = SERVICE_NEXT_CQ_BD;
> + u32 cq_type;
> +
> + while (done == SERVICE_NEXT_CQ_BD) {
> + cmp = (struct cmpl_base *)BD_NOW(bp->cq.bd_virt,
> + bp->cq.cons_idx,
> + sizeof(struct cmpl_base));
> + if ((cmp->info3_v & CMPL_BASE_V) ^ bp->cq.completion_bit)
> + break;
> +
> + cq_type = cmp->type & CMPL_BASE_TYPE_MASK;
> + dump_evt((u8 *)cmp, cq_type, bp->cq.cons_idx);
> + dump_CQ(cmp, bp->cq.cons_idx);
> + switch (cq_type) {
> + case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
> + bnxt_link_evt(bp, cmp);
> + fallthrough;
> + case CMPL_BASE_TYPE_TX_L2:
> + case CMPL_BASE_TYPE_STAT_EJECT:
> + bnxt_adv_cq_index(bp, 1);
> + break;
> + case CMPL_BASE_TYPE_RX_L2:
> + done = bnxt_rx_complete(bp, (struct rx_pkt_cmpl *)cmp);
> + break;
> + default:
> + done = NO_MORE_CQ_BD_TO_SERVICE;
> + break;
> + }
> + }
> +
> + if (bp->cq.cons_idx != old_cons_idx)
> + bnxt_db_cq(bp);
> +
> + if (bp->rx.iob_recv == PKT_RECEIVED) {
> + *packetp = bp->rx.iob_rx;
> + return bp->rx.iob_len;
> + }
> +
> + return -EAGAIN;
> +}
> +
> +static void bnxt_stop(struct udevice *dev)
> +{
> + struct bnxt *bp = dev_get_priv(dev);
> +
> + if (bp->card_en) {
> + bnxt_hwrm_set_rx_mask(bp, 0);
> + bp->card_en = false;
> + }
> +}
> +
> +static int bnxt_free_pkt(struct udevice *dev, uchar *packet, int length)
> +{
> + struct bnxt *bp = dev_get_priv(dev);
> +
> + dbg_rx_pkt(bp, __func__, packet, length);
> + bp->rx.iob_recv = PKT_DONE;
> + bp->rx.iob_len = 0;
> + bp->rx.iob_rx = NULL;
> +
> + return 0;
> +}
> +
> +static const struct eth_ops bnxt_eth_ops = {
> + .start = bnxt_start,
> + .send = bnxt_send,
> + .recv = bnxt_recv,
> + .stop = bnxt_stop,
> + .free_pkt = bnxt_free_pkt,
> +};
> +
> +static const struct udevice_id bnxt_eth_ids[] = {
> + { .compatible = "broadcom,nxe" },
> + { }
> +};
> +
> +static int bnxt_eth_bind(struct udevice *dev)
> +{
> + char name[20];
> +
> + sprintf(name, "bnxt_eth%u", num_cards++);
> +
> + return device_set_name(dev, name);
> +}
> +
> +static int bnxt_eth_probe(struct udevice *dev)
> +{
> + struct eth_pdata *plat = dev_get_plat(dev);
> + struct bnxt *bp = dev_get_priv(dev);
> + int err;
> + int secondary = 0;
> +
> + bp->name = dev->name;
> + bp->pdev = (struct udevice *)dev;
> + bp->cardnum = trailing_strtol(dev->name);
> + bnxt_bring_pci(bp);
> + err = bnxt_alloc_mem(bp);
> + if (err)
> + goto down_pci;
> +
> + if (env_get("ethaddr"))
> + secondary = 1;
> +
> + eth_env_get_enetaddr_by_index("eth", bp->cardnum + secondary,
> + bp->mac_set);
> + err = bnxt_bring_chip(bp);
> + if (err)
> + goto down_chip;
> +
> + display_banner(bp);
> + memcpy(plat->enetaddr, bp->mac_set, ETH_ALEN);
> + /*
> + * Now, driver probe /remove manually called.
> + * Avoid reentrant of probe / remove command.
> + */
> + bp->drv_load = 1;
> +
> + dev->flags_ = DM_FLAG_ACTIVATED;
> + return 0;
> +down_chip:
> + bnxt_down_chip(bp);
> + bnxt_free_mem(bp);
> +down_pci:
> + return err;
> +}
> +
> +static int bnxt_eth_remove(struct udevice *dev)
> +{
> + struct bnxt *bp = dev_get_priv(dev);
> +
> + if (!bp->drv_load)
> + return 0;
> +
> + bnxt_down_chip(bp); /* Down chip */
> + bnxt_free_mem(bp);
> + bp->drv_load = 0;
> +
> + return 0;
> +}
> +
> +static int bnxt_eth_drv_remove(struct udevice *dev)
> +{
> + struct bnxt *bp = dev_get_priv(dev);
> +
> + if (!bp->drv_load)
> + return 0;
> +
> + bnxt_down_chip(bp); /* Down chip */
> + dev->flags_ &= ~DM_FLAG_ACTIVATED;
> + bnxt_free_mem(bp);
> + bp->drv_load = 0;
> +
> + return 0;
> +}
> +
> +int bnxt_drv_probe(struct udevice *dev)
> +{
> + int ret;
> +
> + ret = bnxt_eth_probe(dev);
> + if (ret)
> + return CMD_RET_FAILURE;
> +
> + /* copy ROM MAC to environment. */
> + bnxt_env_set_ethaddr(dev);
> +
> + return CMD_RET_SUCCESS;
> +}
> +
> +int bnxt_drv_remove(struct udevice *dev)
> +{
> + struct bnxt *bp = dev_get_priv(dev);
> +
> + bnxt_env_del_ethaddr(dev);
> + bnxt_eth_drv_remove(dev);
> + printf("bnxt_eth%d - Device removed\n", bp->cardnum);
> +
> + return CMD_RET_SUCCESS;
> +}
> +
> +U_BOOT_DRIVER(eth_bnxt) = {
> + .name = "eth_bnxt",
> + .id = UCLASS_ETH,
> + .of_match = bnxt_eth_ids,
> + .bind = bnxt_eth_bind,
> + .remove = bnxt_eth_remove,
> + .ops = &bnxt_eth_ops,
> + .priv_auto = sizeof(struct bnxt),
> + .plat_auto = sizeof(struct eth_pdata),
> + .flags = DM_FLAG_ACTIVE_DMA,
> +};
> +
> +U_BOOT_PCI_DEVICE(eth_bnxt, bnxt_nics);
> diff --git a/drivers/net/bnxt/bnxt_dbg.h b/drivers/net/bnxt/bnxt_dbg.h
> new file mode 100644
> index 0000000000..ddf2f566b0
> --- /dev/null
> +++ b/drivers/net/bnxt/bnxt_dbg.h
> @@ -0,0 +1,538 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019-2021 Broadcom.
> + */
> +
> +#ifndef _BXNT_DBG_H_
> +#define _BXNT_DBG_H_
> +
> +/* Adjust commented out lines below to enable debug. */
> +/* #define DEBUG_PCI */
> +/* #define DEBUG_MEMORY */
> +/* #define DEBUG_LINK */
> +/* #define DEBUG_CHIP */
> +/* #define DEBUG_FAIL */
> +/* #define DEBUG_HWRM_CMDS */
> +/* #define DEBUG_HWRM_DUMP */
> +/* #define DEBUG_CQ */
> +/* #define DEBUG_CQ_DUMP */
> +/* #define DEBUG_TX */
> +/* #define DEBUG_TX_DUMP */
> +/* #define DEBUG_RX */
> +/* #define DEBUG_RX_DUMP */
> +
> +#if \
> + defined(DEBUG_PCI) || \
> + defined(DEBUG_MEMORY) || \
> + defined(DEBUG_LINK) || \
> + defined(DEBUG_CHIP) || \
> + defined(DEBUG_FAIL) || \
> + defined(DEBUG_HWRM_CMDS) || \
> + defined(DEBUG_HWRM_DUMP) || \
> + defined(DEBUG_CQ) || \
> + defined(DEBUG_CQ_DUMP) || \
> + defined(DEBUG_TX) || \
> + defined(DEBUG_TX_DUMP) || \
> + defined(DEBUG_RX) || \
> + defined(DEBUG_RX_DUMP)
> +#define DEBUG_DEFAULT
> +#endif
> +
> +#if defined(DEBUG_DEFAULT)
> +#define dbg_prn printf
> +#define MAX_CHAR_SIZE(a) (u32)((1 << (a)) - 1)
> +#define DISP_U8 0x00
> +#define DISP_U16 0x01
> +#define DISP_U32 0x02
> +#define DISP_U64 0x03
> +
> +void dumpmemory1(u8 *buffer, u32 length, u8 flag)
> +{
> + u32 jj = 0;
> + u8 i, c;
> +
> + printf("\n %p:", buffer);
> + for (jj = 0; jj < 16; jj++) {
> + if (!(jj & MAX_CHAR_SIZE(flag)))
> + printf(" ");
> + if (jj < length)
> + printf("%02x", buffer[jj]);
> + else
> + printf(" ");
> + if ((jj & 0xF) == 0xF) {
> + printf(" ");
> + for (i = 0; i < 16; i++) {
> + if (i < length) {
> + c = buffer[jj + i - 15];
> + if (c >= 0x20 && c < 0x7F)
> + ;
> + else
> + c = '.';
> + printf("%c", c);
> + }
> + }
> + }
> + }
> +}
> +
> +void dump_mem(u8 *buffer, u32 length, u8 flag)
> +{
> + u32 length16, remlen, jj;
> +
> + length16 = length & 0xFFFFFFF0;
> + remlen = length & 0xF;
> + for (jj = 0; jj < length16; jj += 16)
> + dumpmemory1((u8 *)&buffer[jj], 16, flag);
> + if (remlen)
> + dumpmemory1((u8 *)&buffer[length16], remlen, flag);
> + if (length16 || remlen)
> + printf("\n");
> +}
> +#endif
> +
> +#if defined(DEBUG_PCI)
> +void dbg_pci(struct bnxt *bp, const char *func, u16 cmd_reg)
> +{
> + printf("- %s()\n", func);
> + printf(" Vendor id : %04X\n", bp->vendor_id);
> + printf(" Device id : %04X\n", bp->device_id);
> + printf(" Irq : %d\n", bp->irq);
> + printf(" PCI Command Reg : %04X %04X\n", bp->cmd_reg, cmd_reg);
> + printf(" Sub Vendor id : %04X\n", bp->subsystem_vendor);
> + printf(" Sub Device id : %04X\n", bp->subsystem_device);
> + printf(" PF Number : %X\n", bp->pf_num);
> + printf(" BAR (0) : %p\n", bp->bar0);
> + printf(" BAR (1) : %p\n", bp->bar1);
> + printf(" BAR (2) : %p\n", bp->bar2);
> +}
> +#else
> +#define dbg_pci(bp, func, creg)
> +#endif
> +
> +#if defined(DEBUG_MEMORY)
> +void dbg_mem(struct bnxt *bp, const char *func)
> +{
> + printf("- %s()\n", func);
> + printf(" bp Addr : %p", bp);
> + printf(" Len %4d", (u16)sizeof(struct bnxt));
> + printf(" phy %llx\n", virt_to_bus(bp));
> + printf(" bp->hwrm_req_addr : %p", bp->hwrm_addr_req);
> + printf(" Len %4d", (u16)REQ_BUFFER_SIZE);
> + printf(" phy %llx\n", bp->req_addr_mapping);
> + printf(" bp->hwrm_resp_addr : %p", bp->hwrm_addr_resp);
> + printf(" Len %4d", (u16)RESP_BUFFER_SIZE);
> + printf(" phy %llx\n", bp->resp_addr_mapping);
> + printf(" bp->tx.bd_virt : %p", bp->tx.bd_virt);
> + printf(" Len %4d", (u16)TX_RING_DMA_BUFFER_SIZE);
> + printf(" phy %llx\n", virt_to_bus(bp->tx.bd_virt));
> + printf(" bp->rx.bd_virt : %p", bp->rx.bd_virt);
> + printf(" Len %4d", (u16)RX_RING_DMA_BUFFER_SIZE);
> + printf(" phy %llx\n", virt_to_bus(bp->rx.bd_virt));
> + printf(" bp->cq.bd_virt : %p", bp->cq.bd_virt);
> + printf(" Len %4d", (u16)CQ_RING_DMA_BUFFER_SIZE);
> + printf(" phy %llx\n", virt_to_bus(bp->cq.bd_virt));
> +}
> +#else
> +#define dbg_mem(bp, func)
> +#endif
> +
> +#if defined(DEBUG_CHIP)
> +void print_fw_ver(struct hwrm_ver_get_output *resp, u32 tmo)
> +{
> + if (resp->hwrm_intf_maj_8b < 1) {
> + dbg_prn(" HWRM interface %d.%d.%d is older than 1.0.0.\n",
> + resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
> + resp->hwrm_intf_upd_8b);
> + dbg_prn(" Update FW with HWRM interface 1.0.0 or newer.\n");
> + }
> + dbg_prn(" FW Version : %d.%d.%d.%d\n",
> + resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
> + resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
> + printf(" cmd timeout : %d\n", tmo);
> +}
> +
> +void dbg_func_resource_qcaps(struct bnxt *bp)
> +{
> + /* Ring Groups */
> + printf(" min_hw_ring_grps : %d\n", bp->min_hw_ring_grps);
> + printf(" max_hw_ring_grps : %d\n", bp->max_hw_ring_grps);
> + /* TX Rings */
> + printf(" min_tx_rings : %d\n", bp->min_tx_rings);
> + printf(" max_tx_rings : %d\n", bp->max_tx_rings);
> + /* RX Rings */
> + printf(" min_rx_rings : %d\n", bp->min_rx_rings);
> + printf(" max_rx_rings : %d\n", bp->max_rx_rings);
> + /* Completion Rings */
> + printf(" min_cq_rings : %d\n", bp->min_cp_rings);
> + printf(" max_cq_rings : %d\n", bp->max_cp_rings);
> + /* Statistic Contexts */
> + printf(" min_stat_ctxs : %d\n", bp->min_stat_ctxs);
> + printf(" max_stat_ctxs : %d\n", bp->max_stat_ctxs);
> +}
> +
> +void print_func_qcaps(struct bnxt *bp)
> +{
> + printf(" Port Number : %d\n", bp->port_idx);
> + printf(" fid : 0x%04x\n", bp->fid);
> + dbg_prn(" PF MAC : %02x:%02x:%02x:%02x:%02x:%02x\n",
> + bp->mac_addr[0],
> + bp->mac_addr[1],
> + bp->mac_addr[2],
> + bp->mac_addr[3],
> + bp->mac_addr[4],
> + bp->mac_addr[5]);
> +}
> +
> +void print_func_qcfg(struct bnxt *bp)
> +{
> + printf(" ordinal_value : %d\n", bp->ordinal_value);
> + printf(" stat_ctx_id : %x\n", bp->stat_ctx_id);
> + dbg_prn(" FW MAC : %02x:%02x:%02x:%02x:%02x:%02x\n",
> + bp->mac_addr[0],
> + bp->mac_addr[1],
> + bp->mac_addr[2],
> + bp->mac_addr[3],
> + bp->mac_addr[4],
> + bp->mac_addr[5]);
> +}
> +
> +void dbg_set_speed(u32 speed)
> +{
> + u32 speed1 = ((speed & LINK_SPEED_DRV_MASK) >> LINK_SPEED_DRV_SHIFT);
> +
> + printf(" Set Link Speed : ");
> + switch (speed & LINK_SPEED_DRV_MASK) {
> + case LINK_SPEED_DRV_1G:
> + printf("1 GBPS");
> + break;
> + case LINK_SPEED_DRV_10G:
> + printf("10 GBPS");
> + break;
> + case LINK_SPEED_DRV_25G:
> + printf("25 GBPS");
> + break;
> + case LINK_SPEED_DRV_40G:
> + printf("40 GBPS");
> + break;
> + case LINK_SPEED_DRV_50G:
> + printf("50 GBPS");
> + break;
> + case LINK_SPEED_DRV_100G:
> + printf("100 GBPS");
> + break;
> + case LINK_SPEED_DRV_AUTONEG:
> + printf("AUTONEG");
> + break;
> + default:
> + printf("%x", speed1);
> + break;
> + }
> + printf("\n");
> +}
> +
> +void dbg_chip_info(struct bnxt *bp)
> +{
> + printf(" Stat Ctx ID : %d\n", bp->stat_ctx_id);
> + printf(" Grp ID : %d\n", bp->ring_grp_id);
> + printf(" CQ Ring Id : %d\n", bp->cq_ring_id);
> + printf(" Tx Ring Id : %d\n", bp->tx_ring_id);
> + printf(" Rx ring Id : %d\n", bp->rx_ring_id);
> +}
> +
> +void print_num_rings(struct bnxt *bp)
> +{
> + printf(" num_cmpl_rings : %d\n", bp->num_cmpl_rings);
> + printf(" num_tx_rings : %d\n", bp->num_tx_rings);
> + printf(" num_rx_rings : %d\n", bp->num_rx_rings);
> + printf(" num_ring_grps : %d\n", bp->num_hw_ring_grps);
> + printf(" num_stat_ctxs : %d\n", bp->num_stat_ctxs);
> +}
> +
> +void dbg_flags(const char *func, u32 flags)
> +{
> + printf("- %s()\n", func);
> + printf(" bp->flags : 0x%04x\n", flags);
> +}
> +#else
> +#define print_fw_ver(resp, tmo)
> +#define dbg_func_resource_qcaps(bp)
> +#define print_func_qcaps(bp)
> +#define print_func_qcfg(bp)
> +#define dbg_set_speed(speed)
> +#define dbg_chip_info(bp)
> +#define print_num_rings(bp)
> +#define dbg_flags(func, flags)
> +#endif
> +
> +#if defined(DEBUG_HWRM_CMDS) || defined(DEBUG_FAIL)
> +void dump_hwrm_req(struct bnxt *bp, const char *func, u32 len, u32 tmo)
> +{
> + dbg_prn("- %s(0x%04x) cmd_len %d cmd_tmo %d",
> + func, (u16)((struct input *)bp->hwrm_addr_req)->req_type,
> + len, tmo);
> +#if defined(DEBUG_HWRM_DUMP)
> + dump_mem((u8 *)bp->hwrm_addr_req, len, DISP_U8);
> +#else
> + printf("\n");
> +#endif
> +}
> +
> +void debug_resp(struct bnxt *bp, const char *func, u32 resp_len, u16 err)
> +{
> + dbg_prn("- %s(0x%04x) - ",
> + func, (u16)((struct input *)bp->hwrm_addr_req)->req_type);
> + if (err == STATUS_SUCCESS)
> + printf("Done");
> + else if (err != STATUS_TIMEOUT)
> + printf("Fail err 0x%04x", err);
> + else
> + printf("timedout");
> +#if defined(DEBUG_HWRM_DUMP)
> + if (err != STATUS_TIMEOUT)
> + dump_mem((u8 *)bp->hwrm_addr_resp, resp_len, DISP_U8);
> + else
> + printf("\n");
> +#else
> + resp_len = resp_len;
> + printf("\n");
> +#endif
> +}
> +
> +void dbg_hw_cmd(struct bnxt *bp,
> + const char *func, u16 cmd_len,
> + u16 resp_len, u32 cmd_tmo, u16 err)
> +{
> +#if !defined(DEBUG_HWRM_CMDS)
> + if (err && err != STATUS_TIMEOUT)
> +#endif
> + {
> + dump_hwrm_req(bp, func, cmd_len, cmd_tmo);
> + debug_resp(bp, func, resp_len, err);
> + }
> +}
> +#else
> +#define dbg_hw_cmd(bp, func, cmd_len, resp_len, cmd_tmo, err)
> +#endif
> +
> +#if defined(DEBUG_HWRM_CMDS)
> +void dbg_short_cmd(u8 *req, const char *func, u32 len)
> +{
> + struct hwrm_short_input *sreq;
> +
> + sreq = (struct hwrm_short_input *)req;
> + dbg_prn("- %s(0x%04x) short_cmd_len %d",
> + func,
> + sreq->req_type,
> + (int)len);
> +#if defined(DEBUG_HWRM_DUMP)
> + dump_mem((u8 *)sreq, len, DISP_U8);
> +#else
> + printf("\n");
> +#endif
> +}
> +#else
> +#define dbg_short_cmd(sreq, func, len)
> +#endif
> +
> +#if defined(DEBUG_RX)
> +void dump_rx_bd(struct rx_pkt_cmpl *rx_cmp,
> + struct rx_pkt_cmpl_hi *rx_cmp_hi,
> + u32 desc_idx)
> +{
> + printf(" RX desc_idx %d\n", desc_idx);
> + printf("- rx_cmp %llx", virt_to_bus(rx_cmp));
> +#if defined(DEBUG_RX_DUMP)
> + dump_mem((u8 *)rx_cmp, (u32)sizeof(struct rx_pkt_cmpl), DISP_U8);
> +#else
> + printf("\n");
> +#endif
> + printf("- rx_cmp_hi %llx", virt_to_bus(rx_cmp_hi));
> +#if defined(DEBUG_RX_DUMP)
> + dump_mem((u8 *)rx_cmp_hi, (u32)sizeof(struct rx_pkt_cmpl_hi), DISP_U8);
> +#else
> + printf("\n");
> +#endif
> +}
> +
> +void dbg_rxp(u8 *iob, u16 rx_len, u16 flag)
> +{
> + printf("- RX iob %llx Len %d ", virt_to_bus(iob), rx_len);
> + if (flag == PKT_RECEIVED)
> + printf(" PKT RECEIVED");
> + else if (flag == PKT_DROPPED)
> + printf(" PKT DROPPED");
> +#if defined(DEBUG_RX_DUMP)
> + dump_mem(iob, (u32)rx_len, DISP_U8);
> +#else
> + printf("\n");
> +#endif
> +}
> +
> +void dbg_rx_cid(u16 idx, u16 cid)
> +{
> + dbg_prn("- RX old cid %d new cid %d\n", idx, cid);
> +}
> +
> +void dbg_rx_alloc_iob_fail(u16 idx, u16 cid)
> +{
> + dbg_prn(" Rx alloc_iob (%d) failed", idx);
> + dbg_prn(" for cons_id %d\n", cid);
> +}
> +
> +void dbg_rx_iob(void *iob, u16 idx, u16 cid)
> +{
> + dbg_prn(" Rx alloc_iob (%d) %p bd_virt (%d)\n",
> + idx, iob, cid);
> +}
> +
> +void dbg_rx_pkt(struct bnxt *bp, const char *func, uchar *pkt, int len)
> +{
> + if (bp->rx.iob_recv == PKT_RECEIVED) {
> + dbg_prn("- %s: %llx %d\n", func,
> + virt_to_bus(pkt), len);
> + }
> +}
> +#else
> +#define dump_rx_bd(rx_cmp, rx_cmp_hi, desc_idx)
> +#define dbg_rxp(iob, rx_len, flag)
> +#define dbg_rx_cid(idx, cid)
> +#define dbg_rx_alloc_iob_fail(idx, cid)
> +#define dbg_rx_iob(iob, idx, cid)
> +#define dbg_rx_pkt(bp, func, pkt, len)
> +#endif
> +
> +#if defined(DEBUG_CQ)
> +void dump_CQ(struct cmpl_base *cmp, u16 cons_idx)
> +{
> + printf("- CQ Type ");
> +
> + switch (cmp->type & CMPL_BASE_TYPE_MASK) {
> + case CMPL_BASE_TYPE_STAT_EJECT:
> + printf("(se)");
> + break;
> + case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
> + printf("(ae)");
> + break;
> + case CMPL_BASE_TYPE_TX_L2:
> + printf("(tx)");
> + break;
> + case CMPL_BASE_TYPE_RX_L2:
> + printf("(rx)");
> + break;
> + default:
> + printf("%04x", (u16)(cmp->type & CMPL_BASE_TYPE_MASK));
> + break;
> + }
> + printf(" cid %d", cons_idx);
> +#if defined(DEBUG_CQ_DUMP)
> + dump_mem((u8 *)cmp, (u32)sizeof(struct cmpl_base), DISP_U8);
> +#else
> + printf("\n");
> +#endif
> +}
> +#else
> +#define dump_CQ(cq, id)
> +#endif
> +
> +#if defined(DEBUG_TX)
> +void dump_tx_stat(struct bnxt *bp)
> +{
> + printf(" TX stats cnt %d req_cnt %d", bp->tx.cnt, bp->tx.cnt_req);
> + printf(" prod_id %d cons_id %d\n", bp->tx.prod_id, bp->tx.cons_id);
> +}
> +
> +void dump_tx_pkt(void *packet, dma_addr_t mapping, int len)
> +{
> + printf(" TX Addr %llx Size %d", mapping, len);
> +#if defined(DEBUG_TX_DUMP)
> + dump_mem((u8 *)packet, len, DISP_U8);
> +#else
> + printf("\n");
> +#endif
> +}
> +
> +void dump_tx_bd(struct tx_bd_short *tx_bd, u16 len)
> +{
> + printf(" Tx BD Addr %llx Size %d", virt_to_bus(tx_bd), len);
> +#if defined(DEBUG_TX_DUMP)
> + dump_mem((u8 *)tx_bd, (u32)len, DISP_U8);
> +#else
> + printf("\n");
> +#endif
> +}
> +
> +void dbg_no_tx_bd(void)
> +{
> + printf(" Tx ring full\n");
> +}
> +#else
> +#define dump_tx_stat(bp)
> +#define dump_tx_pkt(packet, mapping, len)
> +#define dump_tx_bd(prod_bd, len)
> +#define dbg_no_tx_bd()
> +#endif
> +
> +#if defined(DEBUG_MEMORY)
> +void dbg_mem_free_done(const char *func)
> +{
> + printf("- %s - Done\n", func);
> +}
> +#else
> +#define dbg_mem_free_done(func)
> +#endif
> +
> +#if defined(DEBUG_FAIL)
> +void dbg_mem_alloc_fail(const char *func)
> +{
> + printf("- %s() Fail\n", func);
> +}
> +#else
> +#define dbg_mem_alloc_fail(func)
> +#endif
> +
> +#if defined(DEBUG_LINK)
> +static void dump_evt(u8 *cmp, u32 type, u16 cid)
> +{
> + u32 size = sizeof(struct cmpl_base);
> + u8 c = 'C';
> +
> + switch (type) {
> + case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
> + break;
> + default:
> + return;
> + }
> + dbg_prn("- %cQ Type (ae) cid %d", c, cid);
> + dump_mem(cmp, size, DISP_U8);
> +}
> +
> +void dbg_link_status(struct bnxt *bp)
> +{
> + dbg_prn(" Port(%d) : Link", bp->port_idx);
> + if (bp->link_status == STATUS_LINK_ACTIVE) {
> + dbg_prn("Up");
> + } else {
> + dbg_prn("Down\n");
> + dbg_prn(" media_detect : %x", bp->media_detect);
> + }
> + dbg_prn("\n");
> +}
> +
> +void dbg_link_state(struct bnxt *bp, u32 tmo)
> +{
> + if (bp->link_status == STATUS_LINK_ACTIVE)
> + printf(" Link wait time : %d ms\n", tmo);
> +}
> +
> +void dbg_phy_speed(struct bnxt *bp, char *name)
> +{
> + printf(" Current Speed : %s\n", name);
> +}
> +#else
> +#define dump_evt(cmp, ty, cid)
> +#define dbg_link_status(bp)
> +#define dbg_link_state(bp, tmo)
> +#define dbg_phy_speed(bp, name)
> +#endif
> +
> +#endif /* _BXNT_DBG_H_ */
> diff --git a/drivers/net/bnxt/pci_ids.h b/drivers/net/bnxt/pci_ids.h
> new file mode 100644
> index 0000000000..e9312be5ac
> --- /dev/null
> +++ b/drivers/net/bnxt/pci_ids.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019-2021 Broadcom.
> + */
> +
> +#ifndef _PCI_IDS_H_
> +#define _PCI_IDS_H_
> +
> +#define PCI_VID_BROADCOM 0x14e4
> +#define PCI_DID_NXT_57320_1 0x16F0
> +
> +static struct pci_device_id bnxt_nics[] = {
> + {PCI_DEVICE(PCI_VID_BROADCOM, PCI_DID_NXT_57320_1)},
> + {}
> +};
> +
> +#endif /* _PCI_IDS_H_ */
> diff --git a/include/broadcom/bnxt.h b/include/broadcom/bnxt.h
> new file mode 100644
> index 0000000000..688898c1d0
> --- /dev/null
> +++ b/include/broadcom/bnxt.h
> @@ -0,0 +1,419 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019-2021 Broadcom.
> + */
> +
> +#ifndef _BNXT_H_
> +#define _BNXT_H_
> +
> +#include <broadcom/bnxt_ver.h>
> +#include <broadcom/bnxt_hsi.h>
> +#include <linux/if_ether.h>
> +#include <pci.h>
> +
> +union dma_addr64_t {
> + dma_addr_t addr;
> + u64 as_u64;
> +};
> +
> +/* Broadcom ethernet driver defines. */
> +#define FLAG_SET(f, b) ((f) |= (b))
> +#define FLAG_TEST(f, b) ((f) & (b))
> +#define FLAG_RESET(f, b) ((f) &= ~(b))
> +#define BNXT_FLAG_HWRM_SHORT_CMD_SUPP BIT(0)
> +#define BNXT_FLAG_HWRM_SHORT_CMD_REQ BIT(1)
> +#define BNXT_FLAG_RESOURCE_QCAPS_SUPPORT BIT(2)
> +#define BNXT_FLAG_MULTI_HOST BIT(3)
> +#define BNXT_FLAG_NPAR_MODE BIT(4)
> +/*******************************************************************************
> + * Status codes.
> + ******************************************************************************/
> +#define STATUS_SUCCESS 0
> +#define STATUS_FAILURE 1
> +#define STATUS_LINK_ACTIVE 4
> +#define STATUS_LINK_DOWN 5
> +#define STATUS_TIMEOUT 0xffff
> +/*******************************************************************************
> + * Receive filter masks.
> + ******************************************************************************/
> +#define RX_MASK_ACCEPT_NONE 0x0000
> +#define RX_MASK_ACCEPT_MULTICAST 0x0002
> +#define RX_MASK_ACCEPT_ALL_MULTICAST 0x0004
> +#define RX_MASK_ACCEPT_BROADCAST 0x0008
> +#define RX_MASK_PROMISCUOUS_MODE 0x10000
> +/*******************************************************************************
> + * media speed.
> + ******************************************************************************/
> +#define MEDIUM_SPEED_AUTONEG 0x0000L
> +#define MEDIUM_SPEED_1000MBPS 0x0300L
> +#define MEDIUM_SPEED_2500MBPS 0x0400L
> +#define MEDIUM_SPEED_10GBPS 0x0600L
> +#define MEDIUM_SPEED_25GBPS 0x0800L
> +#define MEDIUM_SPEED_40GBPS 0x0900L
> +#define MEDIUM_SPEED_50GBPS 0x0a00L
> +#define MEDIUM_SPEED_100GBPS 0x0b00L
> +#define MEDIUM_SPEED_200GBPS 0x0c00L
> +#define MEDIUM_SPEED_MASK 0xff00L
> +#define GET_MEDIUM_SPEED(m) ((m) & MEDIUM_SPEED_MASK)
> +#define SET_MEDIUM_SPEED(bp, s) (((bp)->medium & ~MEDIUM_SPEED_MASK) | (s))
> +#define MEDIUM_UNKNOWN_DUPLEX 0x00000L
> +#define MEDIUM_FULL_DUPLEX 0x00000L
> +#define MEDIUM_HALF_DUPLEX 0x10000L
> +#define GET_MEDIUM_DUPLEX(m) ((m) & MEDIUM_HALF_DUPLEX)
> +#define SET_MEDIUM_DUPLEX(bp, d) (((bp)->medium & ~MEDIUM_HALF_DUPLEX) | (d))
> +#define MEDIUM_SELECTIVE_AUTONEG 0x01000000L
> +#define GET_MEDIUM_AUTONEG_MODE(m) ((m) & 0xff000000L)
> +#define PCICFG_ME_REGISTER 0x98
> +#define GRC_COM_CHAN_BASE 0
> +#define GRC_COM_CHAN_TRIG 0x100
> +#define HWRM_CMD_DEFAULT_TIMEOUT 500 /* in Miliseconds */
> +#define HWRM_CMD_POLL_WAIT_TIME 100 /* In MicroeSconds */
> +#define HWRM_CMD_DEFAULT_MULTIPLAYER(a) ((a) * 10)
> +#define HWRM_CMD_FLASH_MULTIPLAYER(a) ((a) * 100)
> +#define HWRM_CMD_FLASH_ERASE_MULTIPLAYER(a) ((a) * 1000)
> +#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536
> +#define DEFAULT_NUMBER_OF_CMPL_RINGS 0x01
> +#define DEFAULT_NUMBER_OF_TX_RINGS 0x01
> +#define DEFAULT_NUMBER_OF_RX_RINGS 0x01
> +#define DEFAULT_NUMBER_OF_RING_GRPS 0x01
> +#define DEFAULT_NUMBER_OF_STAT_CTXS 0x01
> +#define NUM_RX_BUFFERS 512
> +#define MAX_RX_DESC_CNT 1024
> +#define MAX_TX_DESC_CNT 512
> +#define MAX_CQ_DESC_CNT 2048
> +#define TX_RING_DMA_BUFFER_SIZE (MAX_TX_DESC_CNT * sizeof(struct tx_bd_short))
> +#define RX_RING_DMA_BUFFER_SIZE \
> + (MAX_RX_DESC_CNT * sizeof(struct rx_prod_pkt_bd))
> +#define CQ_RING_DMA_BUFFER_SIZE (MAX_CQ_DESC_CNT * sizeof(struct cmpl_base))
> +#define BNXT_DMA_ALIGNMENT 256 //64
> +#define REQ_BUFFER_SIZE 1024
> +#define RESP_BUFFER_SIZE 1024
> +#define DMA_BUFFER_SIZE 1024
> +#define LM_PAGE_BITS 8
> +#define BNXT_RX_STD_DMA_SZ 1536
> +#define NEXT_IDX(N, S) (((N) + 1) & ((S) - 1))
> +#define BD_NOW(bd, entry, len) (&((u8 *)(bd))[(entry) * (len)])
> +#define BNXT_CQ_INTR_MODE() RING_ALLOC_REQ_INT_MODE_POLL
> +#define BNXT_INTR_MODE() RING_ALLOC_REQ_INT_MODE_POLL
> +/* Set default link timeout period to 500 millseconds */
> +#define LINK_DEFAULT_TIMEOUT 500
> +#define RX_MASK \
> + (RX_MASK_ACCEPT_BROADCAST | \
> + RX_MASK_ACCEPT_ALL_MULTICAST | \
> + RX_MASK_ACCEPT_MULTICAST)
> +#define TX_RING_QID ((u16)bp->port_idx * 10)
> +#define RX_RING_QID 0
> +#define LM_PAGE_SIZE LM_PAGE_BITS
> +#define virt_to_bus(a) ((dma_addr_t)(a))
> +#define REQ_BUF_SIZE_ALIGNED ALIGN(REQ_BUFFER_SIZE, BNXT_DMA_ALIGNMENT)
> +#define RESP_BUF_SIZE_ALIGNED ALIGN(RESP_BUFFER_SIZE, BNXT_DMA_ALIGNMENT)
> +#define DMA_BUF_SIZE_ALIGNED ALIGN(DMA_BUFFER_SIZE, BNXT_DMA_ALIGNMENT)
> +#define RX_STD_DMA_ALIGNED ALIGN(BNXT_RX_STD_DMA_SZ, BNXT_DMA_ALIGNMENT)
> +#define PCI_COMMAND_INTX_DISABLE 0x0400 /* Interrupt disable */
> +#define TX_AVAIL(r) ((r) - 1)
> +#define NO_MORE_CQ_BD_TO_SERVICE 1
> +#define SERVICE_NEXT_CQ_BD 0
> +#define PHY_STATUS 0x0001
> +#define PHY_SPEED 0x0002
> +#define DETECT_MEDIA 0x0004
> +#define SUPPORT_SPEEDS 0x0008
> +#define str_1 "1"
> +#define str_2 "2"
> +#define str_2_5 "2.5"
> +#define str_10 "10"
> +#define str_20 "20"
> +#define str_25 "25"
> +#define str_40 "40"
> +#define str_50 "50"
> +#define str_100 "100"
> +#define str_gbps "Gbps"
> +#define str_mbps "Mbps"
> +#define str_unknown "Unknown"
> +/* Broadcom ethernet driver nvm defines. */
> +/* nvm cfg 1 - MAC settings */
> +#define FUNC_MAC_ADDR_NUM 1
> +/* nvm cfg 203 - u32 link_settings */
> +#define LINK_SPEED_DRV_NUM 203
> +#define LINK_SPEED_DRV_MASK 0x0000000F
> +#define LINK_SPEED_DRV_SHIFT 0
> +#define LINK_SPEED_DRV_AUTONEG 0x0
> +#define LINK_SPEED_DRV_1G 0x1
> +#define LINK_SPEED_DRV_10G 0x2
> +#define LINK_SPEED_DRV_25G 0x3
> +#define LINK_SPEED_DRV_40G 0x4
> +#define LINK_SPEED_DRV_50G 0x5
> +#define LINK_SPEED_DRV_100G 0x6
> +#define LINK_SPEED_DRV_200G 0x7
> +#define LINK_SPEED_DRV_2_5G 0xE
> +#define LINK_SPEED_DRV_100M 0xF
> +/* nvm cfg 201 - u32 speed_cap_mask */
> +#define SPEED_CAPABILITY_DRV_1G 0x1
> +#define SPEED_CAPABILITY_DRV_10G 0x2
> +#define SPEED_CAPABILITY_DRV_25G 0x4
> +#define SPEED_CAPABILITY_DRV_40G 0x8
> +#define SPEED_CAPABILITY_DRV_50G 0x10
> +#define SPEED_CAPABILITY_DRV_100G 0x20
> +#define SPEED_CAPABILITY_DRV_100M 0x8000
> +/* nvm cfg 202 */
> +/* nvm cfg 205 */
> +#define LINK_SPEED_FW_NUM 205
> +/* nvm cfg 210 */
> +/* nvm cfg 211 */
> +/* nvm cfg 213 */
> +#define SPEED_DRV_MASK LINK_SPEED_DRV_MASK
> +/******************************************************************************
> + * Doorbell info.
> + *****************************************************************************/
> +#define RX_DOORBELL_KEY_RX (0x1UL << 28)
> +#define TX_DOORBELL_KEY_TX (0x0UL << 28)
> +
> +#define CMPL_DOORBELL_IDX_VALID 0x4000000UL
> +#define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28)
> +
> +/******************************************************************************
> + * Transmit info.
> + *****************************************************************************/
> +struct tx_bd_short {
> + u16 flags_type;
> +#define TX_BD_SHORT_TYPE_TX_BD_SHORT 0x0UL
> +#define TX_BD_SHORT_FLAGS_PACKET_END 0x40UL
> +#define TX_BD_SHORT_FLAGS_NO_CMPL 0x80UL
> +#define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
> +#define TX_BD_SHORT_FLAGS_LHINT_LT512 (0x0UL << 13)
> +#define TX_BD_SHORT_FLAGS_LHINT_LT1K (0x1UL << 13)
> +#define TX_BD_SHORT_FLAGS_LHINT_LT2K (0x2UL << 13)
> +#define TX_BD_SHORT_FLAGS_LHINT_GTE2K (0x3UL << 13)
> +#define TX_BD_SHORT_FLAGS_COAL_NOW 0x8000UL
> + u16 len;
> + u32 opaque;
> + union dma_addr64_t dma;
> +};
> +
> +struct lm_tx_info_t {
> + void *bd_virt;
> + u16 prod_id; /* Tx producer index. */
> + u16 cons_id;
> + u16 ring_cnt;
> + u32 cnt; /* Tx statistics. */
> + u32 cnt_req;
> +};
> +
> +struct cmpl_base {
> + u16 type;
> +#define CMPL_BASE_TYPE_MASK 0x3fUL
> +#define CMPL_BASE_TYPE_TX_L2 0x0UL
> +#define CMPL_BASE_TYPE_RX_L2 0x11UL
> +#define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
> +#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
> + u16 info1;
> + u32 info2;
> + u32 info3_v;
> +#define CMPL_BASE_V 0x1UL
> + u32 info4;
> +};
> +
> +struct lm_cmp_info_t {
> + void *bd_virt;
> + u16 cons_idx;
> + u16 ring_cnt;
> + u8 completion_bit;
> + u8 res[3];
> +};
> +
> +struct rx_pkt_cmpl {
> + u16 flags_type;
> + u16 len;
> + u32 opaque;
> + u8 agg_bufs_v1;
> + u8 rss_hash_type;
> + u8 payload_offset;
> + u8 unused1;
> + u32 rss_hash;
> +};
> +
> +struct rx_pkt_cmpl_hi {
> + u32 flags2;
> + u32 metadata;
> + u16 errors_v2;
> +#define RX_PKT_CMPL_V2 0x1UL
> +#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
> + u16 cfa_code;
> + u32 reorder;
> +};
> +
> +struct rx_prod_pkt_bd {
> + u16 flags_type;
> +#define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT 0x4UL
> + u16 len;
> + u32 opaque;
> + union dma_addr64_t dma;
> +};
> +
> +struct lm_rx_info_t {
> + void *bd_virt;
> + void *iob[NUM_RX_BUFFERS];
> + void *iob_rx;
> + u16 iob_len;
> + u16 iob_recv;
> + u16 iob_cnt;
> + u16 buf_cnt; /* Total Rx buffer descriptors. */
> + u16 ring_cnt;
> + u16 cons_idx; /* Last processed consumer index. */
> + u32 rx_cnt;
> + u32 rx_buf_cnt;
> + u32 err;
> + u32 crc;
> + u32 dropped;
> +};
> +
> +#define VALID_DRIVER_REG 0x0001
> +#define VALID_STAT_CTX 0x0002
> +#define VALID_RING_CQ 0x0004
> +#define VALID_RING_TX 0x0008
> +#define VALID_RING_RX 0x0010
> +#define VALID_RING_GRP 0x0020
> +#define VALID_VNIC_ID 0x0040
> +#define VALID_RX_IOB 0x0080
> +#define VALID_L2_FILTER 0x0100
> +
> +enum RX_FLAGS {
> + PKT_DONE = 0,
> + PKT_RECEIVED = 1,
> + PKT_DROPPED = 2,
> +};
> +
> +struct bnxt {
> + struct udevice *pdev;
> + const char *name;
> + unsigned int cardnum;
> + void *hwrm_addr_req;
> + void *hwrm_addr_resp;
> + void *hwrm_addr_data;
> + dma_addr_t data_addr_mapping;
> + dma_addr_t req_addr_mapping;
> + dma_addr_t resp_addr_mapping;
> + struct lm_tx_info_t tx; /* Tx info. */
> + struct lm_rx_info_t rx; /* Rx info. */
> + struct lm_cmp_info_t cq; /* completion info. */
> + u16 last_resp_code;
> + u16 seq_id;
> + u32 flag_hwrm;
> + u32 flags;
> + u16 drv_load;
> + u16 vendor_id;
> + u16 device_id;
> + u16 subsystem_vendor;
> + u16 subsystem_device;
> + u16 cmd_reg;
> + u8 pf_num; /* absolute PF number */
> + u8 irq;
> + void __iomem *bar0;
> + void __iomem *bar1;
> + void __iomem *bar2;
> + u16 chip_num;
> + /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
> + u32 chip_id;
> + u32 hwrm_cmd_timeout;
> + u16 hwrm_spec_code;
> + u16 hwrm_max_req_len;
> + u16 hwrm_max_ext_req_len;
> + u8 fw_maj;
> + u8 fw_min;
> + u8 fw_bld;
> + u8 fw_rsvd;
> + u8 mac_addr[ETH_ALEN]; /* HW MAC address */
> + u8 mac_set[ETH_ALEN]; /* NVM Configured MAC */
> + u16 fid;
> + u8 port_idx;
> + u8 ordinal_value;
> + u16 mtu;
> + u16 ring_grp_id;
> + u16 cq_ring_id;
> + u16 tx_ring_id;
> + u16 rx_ring_id;
> + u16 current_link_speed;
> + u16 link_status;
> + u16 wait_link_timeout;
> + u64 l2_filter_id;
> + u16 vnic_id;
> + u16 stat_ctx_id;
> + u32 medium;
> + u16 support_speeds;
> + u32 link_set;
> + u8 media_detect;
> + u8 media_change;
> + u16 max_vfs;
> + u16 vf_res_strategy;
> + u16 min_vnics;
> + u16 max_vnics;
> + u16 max_msix;
> + u16 min_hw_ring_grps;
> + u16 max_hw_ring_grps;
> + u16 min_tx_rings;
> + u16 max_tx_rings;
> + u16 min_rx_rings;
> + u16 max_rx_rings;
> + u16 min_cp_rings;
> + u16 max_cp_rings;
> + u16 min_rsscos_ctxs;
> + u16 max_rsscos_ctxs;
> + u16 min_l2_ctxs;
> + u16 max_l2_ctxs;
> + u16 min_stat_ctxs;
> + u16 max_stat_ctxs;
> + u16 num_cmpl_rings;
> + u16 num_tx_rings;
> + u16 num_rx_rings;
> + u16 num_stat_ctxs;
> + u16 num_hw_ring_grps;
> + bool card_en;
> +};
> +
> +/* defines required to resolve checkpatch errors / warnings */
> +#define test_if if
> +#define write32 writel
> +#define pci_read_byte dm_pci_read_config8
> +#define pci_read_word16 dm_pci_read_config16
> +#define pci_write_word dm_pci_write_config16
> +#define pci_map_bar dm_pci_map_bar
> +#define SHORT_CMD_SUPPORTED VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED
> +#define SHORT_CMD_REQUIRED VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED
> +#define CQ_DOORBELL_KEY_IDX(a) \
> + (CMPL_DOORBELL_KEY_CMPL | \
> + CMPL_DOORBELL_IDX_VALID | \
> + (u32)(a))
> +#define TX_BD_FLAGS \
> + (TX_BD_SHORT_TYPE_TX_BD_SHORT | \
> + TX_BD_SHORT_FLAGS_NO_CMPL | \
> + TX_BD_SHORT_FLAGS_COAL_NOW | \
> + TX_BD_SHORT_FLAGS_PACKET_END | \
> + (1 << TX_BD_SHORT_FLAGS_BD_CNT_SFT))
> +#define MEM_HWRM_RESP memalign(BNXT_DMA_ALIGNMENT, RESP_BUF_SIZE_ALIGNED)
> +#define PORT_PHY_FLAGS (BNXT_FLAG_NPAR_MODE | BNXT_FLAG_MULTI_HOST)
> +#define RING_FREE(bp, rid, flag) bnxt_hwrm_ring_free(bp, rid, flag)
> +#define QCFG_PHY_ALL (SUPPORT_SPEEDS | DETECT_MEDIA | PHY_SPEED | PHY_STATUS)
> +enum BNXT_CMD_FLAG {
> + CMD_UNKNOWN = 0,
> + CMD_PROBE,
> + CMD_REMOVE,
> + CMD_GET_SUPPORTED_SPEED,
> + CMD_GET_LINK_SPEED,
> + CMD_GET_MAC,
> + CMD_SET_MAC,
> + CMD_SET_LINK_SPEED,
> +};
> +
> +int bnxt_get_link_speed(struct bnxt *bp);
> +int bnxt_get_mac(struct bnxt *bp);
> +int bnxt_supported_speed(struct bnxt *bp);
> +int bnxt_drv_remove(struct udevice *dev);
> +int bnxt_drv_probe(struct udevice *dev);
> +void bnxt_env_set_ethaddr(struct udevice *dev);
> +void bnxt_env_del_ethaddr(struct udevice *dev);
> +int bnxt_hwrm_nvm_flush(struct bnxt *bp);
> +int bnxt_set_mac(struct bnxt *bp);
> +int bnxt_set_link_speed(struct bnxt *bp);
> +void prn_link_speed(u32 speed, u8 flag);
> +void print_mac(u8 *mac, u8 flag);
> +
> +#endif /* _BNXT_H_ */
> diff --git a/include/broadcom/bnxt_hsi.h b/include/broadcom/bnxt_hsi.h
> new file mode 100644
> index 0000000000..81cc5da9e4
> --- /dev/null
> +++ b/include/broadcom/bnxt_hsi.h
> @@ -0,0 +1,889 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> + /*
> + * Copyright 2019-2021 Broadcom.
> + */
> +
> +#ifndef _BNXT_HSI_H_
> +#define _BNXT_HSI_H_
> +
> +/* input (size:128b/16B) */
> +struct input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> +};
> +
> +/* output (size:64b/8B) */
> +struct output {
> + __le16 error_code;
> + __le16 req_type;
> + __le16 seq_id;
> + __le16 resp_len;
> +};
> +
> +/* hwrm_short_input (size:128b/16B) */
> +struct hwrm_short_input {
> + __le16 req_type;
> + __le16 signature;
> +#define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
> + __le16 unused_0;
> + __le16 size;
> + __le64 req_addr;
> +};
> +
> +#define HWRM_VER_GET 0x0UL
> +#define HWRM_FUNC_RESET 0x11UL
> +#define HWRM_FUNC_QCAPS 0x15UL
> +#define HWRM_FUNC_QCFG 0x16UL
> +#define HWRM_FUNC_CFG 0x17UL
> +#define HWRM_FUNC_DRV_UNRGTR 0x1aUL
> +#define HWRM_FUNC_DRV_RGTR 0x1dUL
> +#define HWRM_PORT_PHY_CFG 0x20UL
> +#define HWRM_PORT_MAC_CFG 0x21UL
> +#define HWRM_PORT_PHY_QCFG 0x27UL
> +#define HWRM_VNIC_ALLOC 0x40UL
> +#define HWRM_VNIC_FREE 0x41UL
> +#define HWRM_VNIC_CFG 0x42UL
> +#define HWRM_RING_ALLOC 0x50UL
> +#define HWRM_RING_FREE 0x51UL
> +#define HWRM_RING_GRP_ALLOC 0x60UL
> +#define HWRM_RING_GRP_FREE 0x61UL
> +#define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
> +#define HWRM_CFA_L2_FILTER_FREE 0x91UL
> +#define HWRM_CFA_L2_SET_RX_MASK 0x93UL
> +#define HWRM_STAT_CTX_ALLOC 0xb0UL
> +#define HWRM_STAT_CTX_FREE 0xb1UL
> +#define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
> +#define HWRM_NVM_FLUSH 0xfff0UL
> +#define HWRM_NVM_GET_VARIABLE 0xfff1UL
> +#define HWRM_NVM_SET_VARIABLE 0xfff2UL
> +
> +#define HWRM_NA_SIGNATURE ((__le32)(-1))
> +#define HWRM_MAX_REQ_LEN 128
> +#define HWRM_VERSION_MAJOR 1
> +#define HWRM_VERSION_MINOR 10
> +#define HWRM_VERSION_UPDATE 0
> +
> +/* hwrm_ver_get_input (size:192b/24B) */
> +struct hwrm_ver_get_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + u8 hwrm_intf_maj;
> + u8 hwrm_intf_min;
> + u8 hwrm_intf_upd;
> + u8 unused_0[5];
> +};
> +
> +/* hwrm_ver_get_output (size:1408b/176B) */
> +struct hwrm_ver_get_output {
> + __le16 error_code;
> + __le16 req_type;
> + __le16 seq_id;
> + __le16 resp_len;
> + u8 hwrm_intf_maj_8b;
> + u8 hwrm_intf_min_8b;
> + u8 hwrm_intf_upd_8b;
> + u8 hwrm_intf_rsvd_8b;
> + u8 hwrm_fw_maj_8b;
> + u8 hwrm_fw_min_8b;
> + u8 hwrm_fw_bld_8b;
> + u8 hwrm_fw_rsvd_8b;
> + u8 mgmt_fw_maj_8b;
> + u8 mgmt_fw_min_8b;
> + u8 mgmt_fw_bld_8b;
> + u8 mgmt_fw_rsvd_8b;
> + u8 netctrl_fw_maj_8b;
> + u8 netctrl_fw_min_8b;
> + u8 netctrl_fw_bld_8b;
> + u8 netctrl_fw_rsvd_8b;
> + __le32 dev_caps_cfg;
> +#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
> +#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
> + u8 roce_fw_maj_8b;
> + u8 roce_fw_min_8b;
> + u8 roce_fw_bld_8b;
> + u8 roce_fw_rsvd_8b;
> + char hwrm_fw_name[16];
> + char mgmt_fw_name[16];
> + char netctrl_fw_name[16];
> + u8 reserved2[16];
> + char roce_fw_name[16];
> + __le16 chip_num;
> + u8 chip_rev;
> + u8 chip_metal;
> + u8 chip_bond_id;
> + u8 chip_platform_type;
> + __le16 max_req_win_len;
> + __le16 max_resp_len;
> + __le16 def_req_timeout;
> + u8 flags;
> + u8 unused_0[2];
> + u8 always_1;
> + __le16 hwrm_intf_major;
> + __le16 hwrm_intf_minor;
> + __le16 hwrm_intf_build;
> + __le16 hwrm_intf_patch;
> + __le16 hwrm_fw_major;
> + __le16 hwrm_fw_minor;
> + __le16 hwrm_fw_build;
> + __le16 hwrm_fw_patch;
> + __le16 mgmt_fw_major;
> + __le16 mgmt_fw_minor;
> + __le16 mgmt_fw_build;
> + __le16 mgmt_fw_patch;
> + __le16 netctrl_fw_major;
> + __le16 netctrl_fw_minor;
> + __le16 netctrl_fw_build;
> + __le16 netctrl_fw_patch;
> + __le16 roce_fw_major;
> + __le16 roce_fw_minor;
> + __le16 roce_fw_build;
> + __le16 roce_fw_patch;
> + __le16 max_ext_req_len;
> + u8 unused_1[5];
> + u8 valid;
> +};
> +
> +/* hwrm_async_event_cmpl (size:128b/16B) */
> +struct hwrm_async_event_cmpl {
> + __le16 type;
> + __le16 event_id;
> +#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
> + __le32 event_data2;
> + u8 opaque_v;
> + u8 timestamp_lo;
> + __le16 timestamp_hi;
> + __le32 event_data1;
> +};
> +
> +/* hwrm_func_reset_input (size:192b/24B) */
> +struct hwrm_func_reset_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le32 enables;
> + __le16 vf_id;
> + u8 func_reset_level;
> +#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL
> + u8 unused_0;
> +};
> +
> +/* hwrm_func_qcaps_input (size:192b/24B) */
> +struct hwrm_func_qcaps_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le16 fid;
> + u8 unused_0[6];
> +};
> +
> +/* hwrm_func_qcaps_output (size:640b/80B) */
> +struct hwrm_func_qcaps_output {
> + __le16 error_code;
> + __le16 req_type;
> + __le16 seq_id;
> + __le16 resp_len;
> + __le16 fid;
> + __le16 port_id;
> + __le32 flags;
> + u8 mac_address[6];
> + __le16 max_rsscos_ctx;
> + __le16 max_cmpl_rings;
> + __le16 max_tx_rings;
> + __le16 max_rx_rings;
> + __le16 max_l2_ctxs;
> + __le16 max_vnics;
> + __le16 first_vf_id;
> + __le16 max_vfs;
> + __le16 max_stat_ctx;
> + __le32 max_encap_records;
> + __le32 max_decap_records;
> + __le32 max_tx_em_flows;
> + __le32 max_tx_wm_flows;
> + __le32 max_rx_em_flows;
> + __le32 max_rx_wm_flows;
> + __le32 max_mcast_filters;
> + __le32 max_flow_id;
> + __le32 max_hw_ring_grps;
> + __le16 max_sp_tx_rings;
> + u8 unused_0;
> + u8 valid;
> +};
> +
> +/* hwrm_func_qcfg_input (size:192b/24B) */
> +struct hwrm_func_qcfg_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le16 fid;
> + u8 unused_0[6];
> +};
> +
> +/* hwrm_func_qcfg_output (size:704b/88B) */
> +struct hwrm_func_qcfg_output {
> + __le16 error_code;
> + __le16 req_type;
> + __le16 seq_id;
> + __le16 resp_len;
> + __le16 fid;
> + __le16 port_id;
> + __le16 vlan;
> + __le16 flags;
> +#define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
> + u8 mac_address[6];
> + __le16 pci_id;
> + __le16 alloc_rsscos_ctx;
> + __le16 alloc_cmpl_rings;
> + __le16 alloc_tx_rings;
> + __le16 alloc_rx_rings;
> + __le16 alloc_l2_ctx;
> + __le16 alloc_vnics;
> + __le16 mtu;
> + __le16 mru;
> + __le16 stat_ctx_id;
> + u8 port_partition_type;
> +#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
> + u8 port_pf_cnt;
> + __le16 dflt_vnic_id;
> + __le16 max_mtu_configured;
> + __le32 min_bw;
> + __le32 max_bw;
> + u8 evb_mode;
> + u8 options;
> + __le16 alloc_vfs;
> + __le32 alloc_mcast_filters;
> + __le32 alloc_hw_ring_grps;
> + __le16 alloc_sp_tx_rings;
> + __le16 alloc_stat_ctx;
> + __le16 alloc_msix;
> + __le16 registered_vfs;
> + u8 unused_1[3];
> + u8 always_1;
> + __le32 reset_addr_poll;
> + u8 unused_2[3];
> + u8 valid;
> +};
> +
> +/* hwrm_func_cfg_input (size:704b/88B) */
> +struct hwrm_func_cfg_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le16 fid;
> + __le16 num_msix;
> + __le32 flags;
> + __le32 enables;
> +#define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
> +#define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
> +#define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
> +#define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
> +#define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
> +#define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
> + __le16 mtu;
> + __le16 mru;
> + __le16 num_rsscos_ctxs;
> + __le16 num_cmpl_rings;
> + __le16 num_tx_rings;
> + __le16 num_rx_rings;
> + __le16 num_l2_ctxs;
> + __le16 num_vnics;
> + __le16 num_stat_ctxs;
> + __le16 num_hw_ring_grps;
> + u8 dflt_mac_addr[6];
> + __le16 dflt_vlan;
> + __be32 dflt_ip_addr[4];
> + __le32 min_bw;
> + __le32 max_bw;
> + __le16 async_event_cr;
> + u8 vlan_antispoof_mode;
> + u8 allowed_vlan_pris;
> + u8 evb_mode;
> + u8 options;
> + __le16 num_mcast_filters;
> +};
> +
> +/* hwrm_func_drv_rgtr_input (size:896b/112B) */
> +struct hwrm_func_drv_rgtr_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le32 flags;
> + __le32 enables;
> +#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
> +#define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
> +#define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
> + __le16 os_type;
> +#define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL
> + u8 ver_maj_8b;
> + u8 ver_min_8b;
> + u8 ver_upd_8b;
> + u8 unused_0[3];
> + __le32 timestamp;
> + u8 unused_1[4];
> + __le32 vf_req_fwd[8];
> + __le32 async_event_fwd[8];
> + __le16 ver_maj;
> + __le16 ver_min;
> + __le16 ver_upd;
> + __le16 ver_patch;
> +};
> +
> +/* hwrm_func_drv_unrgtr_input (size:192b/24B) */
> +struct hwrm_func_drv_unrgtr_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le32 flags;
> +#define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
> + u8 unused_0[4];
> +};
> +
> +/* hwrm_func_resource_qcaps_input (size:192b/24B) */
> +struct hwrm_func_resource_qcaps_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le16 fid;
> + u8 unused_0[6];
> +};
> +
> +/* hwrm_func_resource_qcaps_output (size:448b/56B) */
> +struct hwrm_func_resource_qcaps_output {
> + __le16 error_code;
> + __le16 req_type;
> + __le16 seq_id;
> + __le16 resp_len;
> + __le16 max_vfs;
> + __le16 max_msix;
> + __le16 vf_reservation_strategy;
> + __le16 min_rsscos_ctx;
> + __le16 max_rsscos_ctx;
> + __le16 min_cmpl_rings;
> + __le16 max_cmpl_rings;
> + __le16 min_tx_rings;
> + __le16 max_tx_rings;
> + __le16 min_rx_rings;
> + __le16 max_rx_rings;
> + __le16 min_l2_ctxs;
> + __le16 max_l2_ctxs;
> + __le16 min_vnics;
> + __le16 max_vnics;
> + __le16 min_stat_ctx;
> + __le16 max_stat_ctx;
> + __le16 min_hw_ring_grps;
> + __le16 max_hw_ring_grps;
> + __le16 max_tx_scheduler_inputs;
> + __le16 flags;
> + u8 unused_0[5];
> + u8 valid;
> +};
> +
> +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
> +struct hwrm_func_vlan_qcfg_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le16 fid;
> + u8 unused_0[6];
> +};
> +
> +/* hwrm_port_phy_cfg_input (size:448b/56B) */
> +struct hwrm_port_phy_cfg_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le32 flags;
> +#define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
> +#define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
> + __le32 enables;
> +#define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
> +#define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
> +#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
> +#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
> + __le16 port_id;
> + __le16 force_link_speed;
> +#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL
> +#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL
> +#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL
> +#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL
> +#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL
> +#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
> + u8 auto_mode;
> +#define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL
> + u8 auto_duplex;
> +#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
> + u8 auto_pause;
> +#define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
> +#define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
> + u8 unused_0;
> + __le16 auto_link_speed;
> + __le16 auto_link_speed_mask;
> +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
> +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
> +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
> +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
> +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
> +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
> +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
> + u8 wirespeed;
> + u8 lpbk;
> + u8 force_pause;
> + u8 unused_1;
> + __le32 preemphasis;
> + __le16 eee_link_speed_mask;
> + u8 unused_2[2];
> + __le32 tx_lpi_timer;
> + __le32 unused_3;
> +};
> +
> +/* hwrm_port_phy_qcfg_input (size:192b/24B) */
> +struct hwrm_port_phy_qcfg_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le16 port_id;
> + u8 unused_0[6];
> +};
> +
> +/* hwrm_port_phy_qcfg_output (size:768b/96B) */
> +struct hwrm_port_phy_qcfg_output {
> + __le16 error_code;
> + __le16 req_type;
> + __le16 seq_id;
> + __le16 resp_len;
> + u8 link;
> +#define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
> + u8 unused_0;
> + __le16 link_speed;
> +#define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
> +#define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
> +#define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL
> +#define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
> +#define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL
> +#define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL
> +#define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL
> +#define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
> +#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
> +#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
> +#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
> + u8 duplex_cfg;
> + u8 pause;
> + __le16 support_speeds;
> +#define PORT_QCFG_SUPPORT_SPEEDS_100MBHD 0x1UL
> +#define PORT_QCFG_SUPPORT_SPEEDS_100MB 0x2UL
> +#define PORT_QCFG_SUPPORT_SPEEDS_1GBHD 0x4UL
> +#define PORT_QCFG_SUPPORT_SPEEDS_1GB 0x8UL
> +#define PORT_QCFG_SUPPORT_SPEEDS_2GB 0x10UL
> +#define PORT_QCFG_SUPPORT_SPEEDS_2_5GB 0x20UL
> +#define PORT_QCFG_SUPPORT_SPEEDS_10GB 0x40UL
> +#define PORT_QCFG_SUPPORT_SPEEDS_20GB 0x80UL
> +#define PORT_QCFG_SUPPORT_SPEEDS_25GB 0x100UL
> +#define PORT_QCFG_SUPPORT_SPEEDS_50GB 0x400UL
> +#define PORT_QCFG_SUPPORT_SPEEDS_100GB 0x800UL
> +#define PORT_QCFG_SUPPORT_SPEEDS_200GB 0x4000UL
> + __le16 force_link_speed;
> + u8 auto_mode;
> + u8 auto_pause;
> + __le16 auto_link_speed;
> + __le16 auto_link_speed_mask;
> + u8 wirespeed;
> + u8 lpbk;
> + u8 force_pause;
> + u8 module_status;
> + __le32 preemphasis;
> + u8 phy_maj;
> + u8 phy_min;
> + u8 phy_bld;
> + u8 phy_type;
> + u8 media_type;
> + u8 xcvr_pkg_type;
> + u8 eee_config_phy_addr;
> + u8 parallel_detect;
> + __le16 link_partner_adv_speeds;
> + u8 link_partner_adv_auto_mode;
> + u8 link_partner_adv_pause;
> + __le16 adv_eee_link_speed_mask;
> + __le16 link_partner_adv_eee_link_speed_mask;
> + __le32 xcvr_identifier_type_tx_lpi_timer;
> + __le16 fec_cfg;
> + u8 duplex_state;
> + u8 option_flags;
> + char phy_vendor_name[16];
> + char phy_vendor_partnumber[16];
> + u8 unused_2[7];
> + u8 valid;
> +};
> +
> +/* hwrm_port_mac_cfg_input (size:320b/40B) */
> +struct hwrm_port_mac_cfg_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le32 flags;
> + __le32 enables;
> + __le16 port_id;
> + u8 ipg;
> + u8 lpbk;
> +#define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL
> + u8 vlan_pri2cos_map_pri;
> + u8 reserved1;
> + u8 tunnel_pri2cos_map_pri;
> + u8 dscp2pri_map_pri;
> + __le16 rx_ts_capture_ptp_msg_type;
> + __le16 tx_ts_capture_ptp_msg_type;
> + u8 cos_field_cfg;
> + u8 unused_0[3];
> +};
> +
> +/* hwrm_vnic_alloc_input (size:192b/24B) */
> +struct hwrm_vnic_alloc_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le32 flags;
> +#define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
> + u8 unused_0[4];
> +};
> +
> +/* hwrm_vnic_alloc_output (size:128b/16B) */
> +struct hwrm_vnic_alloc_output {
> + __le16 error_code;
> + __le16 req_type;
> + __le16 seq_id;
> + __le16 resp_len;
> + __le32 vnic_id;
> + u8 unused_0[3];
> + u8 valid;
> +};
> +
> +/* hwrm_vnic_free_input (size:192b/24B) */
> +struct hwrm_vnic_free_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le32 vnic_id;
> + u8 unused_0[4];
> +};
> +
> +/* hwrm_vnic_cfg_input (size:320b/40B) */
> +struct hwrm_vnic_cfg_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le32 flags;
> + __le32 enables;
> +#define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
> +#define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
> + __le16 vnic_id;
> + __le16 dflt_ring_grp;
> + __le16 rss_rule;
> + __le16 cos_rule;
> + __le16 lb_rule;
> + __le16 mru;
> + __le16 default_rx_ring_id;
> + __le16 default_cmpl_ring_id;
> +};
> +
> +/* hwrm_ring_alloc_input (size:704b/88B) */
> +struct hwrm_ring_alloc_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le32 enables;
> +#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
> + u8 ring_type;
> +#define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
> +#define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
> +#define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL
> + u8 unused_0;
> + __le16 flags;
> + __le64 page_tbl_addr;
> + __le32 fbo;
> + u8 page_size;
> + u8 page_tbl_depth;
> + u8 unused_1[2];
> + __le32 length;
> + __le16 logical_id;
> + __le16 cmpl_ring_id;
> + __le16 queue_id;
> + __le16 rx_buf_size;
> + __le16 rx_ring_id;
> + __le16 nq_ring_id;
> + __le16 ring_arb_cfg;
> + __le16 unused_3;
> + __le32 reserved3;
> + __le32 stat_ctx_id;
> + __le32 reserved4;
> + __le32 max_bw;
> + u8 int_mode;
> +#define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL
> + u8 unused_4[3];
> + __le64 cq_handle;
> +};
> +
> +/* hwrm_ring_alloc_output (size:128b/16B) */
> +struct hwrm_ring_alloc_output {
> + __le16 error_code;
> + __le16 req_type;
> + __le16 seq_id;
> + __le16 resp_len;
> + __le16 ring_id;
> + __le16 logical_ring_id;
> + u8 unused_0[3];
> + u8 valid;
> +};
> +
> +/* hwrm_ring_free_input (size:192b/24B) */
> +struct hwrm_ring_free_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + u8 ring_type;
> +#define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL
> +#define RING_FREE_REQ_RING_TYPE_TX 0x1UL
> +#define RING_FREE_REQ_RING_TYPE_RX 0x2UL
> + u8 unused_0;
> + __le16 ring_id;
> + u8 unused_1[4];
> +};
> +
> +/* hwrm_ring_grp_alloc_input (size:192b/24B) */
> +struct hwrm_ring_grp_alloc_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le16 cr;
> + __le16 rr;
> + __le16 ar;
> + __le16 sc;
> +};
> +
> +/* hwrm_ring_grp_alloc_output (size:128b/16B) */
> +struct hwrm_ring_grp_alloc_output {
> + __le16 error_code;
> + __le16 req_type;
> + __le16 seq_id;
> + __le16 resp_len;
> + __le32 ring_group_id;
> + u8 unused_0[3];
> + u8 valid;
> +};
> +
> +/* hwrm_ring_grp_free_input (size:192b/24B) */
> +struct hwrm_ring_grp_free_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le32 ring_group_id;
> + u8 unused_0[4];
> +};
> +
> +/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
> +struct hwrm_cfa_l2_filter_alloc_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le32 flags;
> +#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
> + __le32 enables;
> +#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
> +#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
> +#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
> + u8 l2_addr[6];
> + u8 unused_0[2];
> + u8 l2_addr_mask[6];
> + __le16 l2_ovlan;
> + __le16 l2_ovlan_mask;
> + __le16 l2_ivlan;
> + __le16 l2_ivlan_mask;
> + u8 unused_1[2];
> + u8 t_l2_addr[6];
> + u8 unused_2[2];
> + u8 t_l2_addr_mask[6];
> + __le16 t_l2_ovlan;
> + __le16 t_l2_ovlan_mask;
> + __le16 t_l2_ivlan;
> + __le16 t_l2_ivlan_mask;
> + u8 src_type;
> +#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
> + u8 unused_3;
> + __le32 src_id;
> + u8 tunnel_type;
> + u8 unused_4;
> + __le16 dst_id;
> + __le16 mirror_vnic_id;
> + u8 pri_hint;
> + u8 unused_5;
> + __le32 unused_6;
> + __le64 l2_filter_id_hint;
> +};
> +
> +/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
> +struct hwrm_cfa_l2_filter_alloc_output {
> + __le16 error_code;
> + __le16 req_type;
> + __le16 seq_id;
> + __le16 resp_len;
> + __le64 l2_filter_id;
> + __le32 flow_id;
> + u8 unused_0[3];
> + u8 valid;
> +};
> +
> +/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
> +struct hwrm_cfa_l2_filter_free_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le64 l2_filter_id;
> +};
> +
> +/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
> +struct hwrm_cfa_l2_set_rx_mask_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le32 vnic_id;
> + __le32 mask;
> +#define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
> +#define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
> +#define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
> +#define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
> + __le64 mc_tbl_addr;
> + __le32 num_mc_entries;
> + u8 unused_0[4];
> + __le64 vlan_tag_tbl_addr;
> + __le32 num_vlan_tags;
> + u8 unused_1[4];
> +};
> +
> +/* hwrm_stat_ctx_alloc_input (size:256b/32B) */
> +struct hwrm_stat_ctx_alloc_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le64 stats_dma_addr;
> + __le32 update_period_ms;
> + u8 stat_ctx_flags;
> + u8 unused_0[3];
> +};
> +
> +/* hwrm_stat_ctx_alloc_output (size:128b/16B) */
> +struct hwrm_stat_ctx_alloc_output {
> + __le16 error_code;
> + __le16 req_type;
> + __le16 seq_id;
> + __le16 resp_len;
> + __le32 stat_ctx_id;
> + u8 unused_0[3];
> + u8 valid;
> +};
> +
> +/* hwrm_stat_ctx_free_input (size:192b/24B) */
> +struct hwrm_stat_ctx_free_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le32 stat_ctx_id;
> + u8 unused_0[4];
> +};
> +
> +/* hwrm_nvm_flush_input (size:128b/16B) */
> +struct hwrm_nvm_flush_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> +};
> +
> +/* hwrm_nvm_get_variable_input (size:320b/40B) */
> +struct hwrm_nvm_get_variable_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le64 dest_data_addr;
> + __le16 data_len;
> + __le16 option_num;
> + __le16 dimensions;
> + __le16 index_0;
> + __le16 index_1;
> + __le16 index_2;
> + __le16 index_3;
> + u8 flags;
> + u8 unused_0;
> +};
> +
> +/* hwrm_nvm_set_variable_input (size:320b/40B) */
> +struct hwrm_nvm_set_variable_input {
> + __le16 req_type;
> + __le16 cmpl_ring;
> + __le16 seq_id;
> + __le16 target_id;
> + __le64 resp_addr;
> + __le64 src_data_addr;
> + __le16 data_len;
> + __le16 option_num;
> + __le16 dimensions;
> + __le16 index_0;
> + __le16 index_1;
> + __le16 index_2;
> + __le16 index_3;
> + u8 flags;
> + u8 unused_0;
> +};
> +
> +#endif /* _BNXT_HSI_H_ */
> diff --git a/include/broadcom/bnxt_ver.h b/include/broadcom/bnxt_ver.h
> new file mode 100644
> index 0000000000..fa84397338
> --- /dev/null
> +++ b/include/broadcom/bnxt_ver.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019-2021 Broadcom.
> + */
> +
> +#ifndef _BNXT_VER_H_
> +#define _BNXT_VER_H_
> +
> +#ifndef BNXT_EXTRA_VER_H
> +#define BNXT_EXTRA_VER_H
> +#define DRV_MODULE_EXTRA_VER "-216.1.182.0"
> +#endif
> +
> +#define DRV_MODULE_NAME "bnxt"
> +#define DRV_MODULE_VERSION "1.0.0" DRV_MODULE_EXTRA_VER
> +#define UBOOT_MODULE_VER "1.0.0"
> +#define UBOOT_VERSION_MAJOR 1
> +#define UBOOT_VERSION_MINOR 0
> +#define UBOOT_VERSION_UPDATE 0
> +#define DRV_MODULE_DESC "Broadcom NetXtreme-C/E driver"
> +
> +#endif /* _BNXT_VER_H_ */
> --
> 2.17.1
>
>
> --
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Reviewd-by: Ramon Fried <rfried.dev at gmail.com>
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