Question/issues about i.MX6 DDR configuration

[Fabio Estevam]

Hi Francesco,

On Thu, Dec 2, 2021 at 1:14 PM Francesco Dolcini
<francesco.dolcini at toradex.com> wrote:
>
> Hello Fabio, Tim and all,
> in the last few weeks I have been debugging some sporadic i.MX6 board
> boot failures (2020.07 U-Boot, if that matters) and we have some loose
> indication that they could be RAM related. The effect is that SPL is not
> able to load U-Boot from the eMMC to DDR and dqs|write_level calibration
> is failing.
>
> We do write the memory configuration in a pretty simple way, SPL is just
> iterating thought a list of register address/value, in a very similar
> way to what was done using the DCD table. Today most of the boards
> however use a more programmatic approach as introduced by Tim in 2014 [1].
>
> Contrary to that, however, Fabio moved away from this new approach to
> just raw registers writing for the sabre board [2][3].
>
> I'm a little bit puzzled at the moment, according to the iMX6 reference
> manual[4], 44.4.2 MMDC initialization, a specific sequence is required
> to be followed and this is implemented by the `mx6_dram_cfg()`[5]
> function, but according to what Fabio wrote the raw initialization of
> registers was just more reliable for mx6sabresd. Fabio, what was the
> reason?

The reason is that I wanted to keep the DDR initialization 100% the
same in U-Boot
mainline versus NXP U-Boot for mx6sabresd board.

The mx6_ddr_sysinfo approach is more elegant, for sure.

It is just that I wanted to keep 100% in sync with the initialization
done by the NXP hardware team.

Regards,

Fabio Estevam