Question/issues about i.MX6 DDR configuration

Fabio Estevam festevam at
Sat Dec 4 15:29:23 CET 2021

Hi Francesco,

On Fri, Dec 3, 2021 at 5:47 AM Francesco Dolcini
<francesco.dolcini at> wrote:

> I think that this applies even with just one chip select, it is just
> prescribing a procedure and explicitly saying that it must be done for
> all the chip select in use, either 1 or 2.

According to the NXP application note:

"To issue a Precharge-All to CS0, write 0x04000050 to MDSCR."

but such setting is not done in NXP U-Boot for mx6sabresd:

Back to your original instability issue: I suppose you are talking
about colibri_imx6.c.

Does it work well if you convert it to the mx6_dram_cfg() scheme?

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