[PATCH 2/5] arm: dts: beacon-rzg2: Resync device trees with Linux 5.16-rc3

[Adam Ford]

The device trees for the Beacon RZ/G2[MNH] boards have undergone
some changes over time, so resync them now.

Signed-off-by: Adam Ford <aford173 at gmail.com>
---
 arch/arm/dts/beacon-renesom-baseboard.dtsi | 16 ++++++--
 arch/arm/dts/beacon-renesom-som.dtsi       | 45 ++++++----------------
 arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts |  3 ++
 arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts |  3 ++
 arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts |  3 ++
 5 files changed, 32 insertions(+), 38 deletions(-)

diff --git a/arch/arm/dts/beacon-renesom-baseboard.dtsi b/arch/arm/dts/beacon-renesom-baseboard.dtsi
index 5f998d4706..2692cc64bf 100644
--- a/arch/arm/dts/beacon-renesom-baseboard.dtsi
+++ b/arch/arm/dts/beacon-renesom-baseboard.dtsi
@@ -197,6 +197,14 @@
 		compatible = "audio-graph-card";
 		label = "rcar-sound";
 		dais = <&rsnd_port0>, <&rsnd_port1>;
+		widgets = "Microphone", "Mic Jack",
+			  "Line", "Line In Jack",
+			  "Headphone", "Headphone Jack";
+		mic-det-gpio = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		routing = "Headphone Jack", "HPOUTL",
+			 "Headphone Jack", "HPOUTR",
+			 "IN3R", "MICBIAS",
+			 "Mic Jack", "IN3R";
 	};
 
 	vccq_sdhi0: regulator-vccq-sdhi0 {
@@ -271,12 +279,12 @@
 &ehci0 {
 	dr_mode = "otg";
 	status = "okay";
-	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
+	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
 };
 
 &ehci1 {
 	status = "okay";
-	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
 };
 
 &hdmi0 {
@@ -615,7 +623,7 @@
 };
 
 &rcar_sound {
-	pinctrl-0 = <&sound_pins &sound_clk_pins>;
+	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
 	pinctrl-names = "default";
 
 	/* Single DAI */
@@ -639,7 +647,7 @@
 				bitclock-master = <&rsnd_endpoint0>;
 				frame-master = <&rsnd_endpoint0>;
 
-				playback = <&ssi1 &dvc1 &src1>;
+				playback = <&ssi1>, <&dvc1>, <&src1>;
 				capture = <&ssi0>;
 			};
 		};
diff --git a/arch/arm/dts/beacon-renesom-som.dtsi b/arch/arm/dts/beacon-renesom-som.dtsi
index d30bab3c8b..0d136809eb 100644
--- a/arch/arm/dts/beacon-renesom-som.dtsi
+++ b/arch/arm/dts/beacon-renesom-som.dtsi
@@ -7,19 +7,10 @@
 #include <dt-bindings/clk/versaclock.h>
 
 / {
-	aliases {
-		spi0 = &rpc;
-	};
-
 	memory at 48000000 {
 		device_type = "memory";
 		/* first 128MB is reserved for secure area. */
-		reg = <0x0 0x48000000 0x0 0xc000000>;
-	};
-
-	memory at 57000000 {
-		device_type = "memory";
-		reg = <0x0 0x57000000 0x0 0x29000000>;
+		reg = <0x0 0x48000000 0x0 0x78000000>;
 	};
 
 	osc_32k: osc_32k {
@@ -59,12 +50,17 @@
 &avb {
 	pinctrl-0 = <&avb_pins>;
 	pinctrl-names = "default";
+	phy-mode = "rgmii-rxid";
 	phy-handle = <&phy0>;
 	rx-internal-delay-ps = <1800>;
 	tx-internal-delay-ps = <2000>;
+	clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
+	clock-names = "fck", "refclk";
 	status = "okay";
 
 	phy0: ethernet-phy at 0 {
+		compatible = "ethernet-phy-id004d.d074",
+			     "ethernet-phy-ieee802.3-c22";
 		reg = <0>;
 		interrupt-parent = <&gpio2>;
 		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
@@ -153,7 +149,7 @@
 	};
 
 	eeprom at 50 {
-		compatible = "microchip,at24c64", "atmel,24c64";
+		compatible = "microchip,24c64", "atmel,24c64";
 		pagesize = <32>;
 		read-only;	/* Manufacturing EEPROM programmed at factory */
 		reg = <0x50>;
@@ -279,25 +275,6 @@
 	};
 };
 
-&rpc {
-	compatible = "renesas,rcar-gen3-rpc";
-	num-cs = <1>;
-	spi-max-frequency = <40000000>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "okay";
-
-	flash0: spi-flash at 0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		compatible = "spi-flash", "jedec,spi-nor";
-		spi-max-frequency = <40000000>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <1>;
-	};
-};
-
 &scif_clk {
 	clock-frequency = <14745600>;
 };
@@ -340,17 +317,17 @@
 	vqmmc-supply = <&reg_1p8v>;
 	bus-width = <8>;
 	mmc-hs200-1_8v;
+	no-sd;
+	no-sdio;
 	non-removable;
 	fixed-emmc-driver-type = <1>;
 	status = "okay";
 };
 
 &usb2_clksel {
-	status = "okay";
 	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
-		 <&versaclock5 3>, <&usb3s0_clk>;
-	clock-names = "ehci_ohci", "hs-usb-if",
-		      "usb_extal", "usb_xtal";
+		  <&versaclock5 3>, <&usb3s0_clk>;
+	status = "okay";
 };
 
 &usb3s0_clk {
diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
index 501cb05da2..3cf2e07694 100644
--- a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
+++ b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
@@ -21,6 +21,9 @@
 		serial4 = &hscif2;
 		serial5 = &scif5;
 		ethernet0 = &avb;
+		mmc0 = &sdhi3;
+		mmc1 = &sdhi0;
+		mmc2 = &sdhi2;
 	};
 
 	chosen {
diff --git a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
index 71763f4402..3c0d59def8 100644
--- a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
+++ b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
@@ -22,6 +22,9 @@
 		serial5 = &scif5;
 		serial6 = &scif4;
 		ethernet0 = &avb;
+		mmc0 = &sdhi3;
+		mmc1 = &sdhi0;
+		mmc2 = &sdhi2;
 	};
 
 	chosen {
diff --git a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
index 273f062f29..7b6649a3de 100644
--- a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
+++ b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
@@ -22,6 +22,9 @@
 		serial5 = &scif5;
 		serial6 = &scif4;
 		ethernet0 = &avb;
+		mmc0 = &sdhi3;
+		mmc1 = &sdhi0;
+		mmc2 = &sdhi2;
 	};
 
 	chosen {
-- 
2.32.0