[PATCH v2 2/3] arm64: dts: rockchip: Sync px30 from linux-next
Kever Yang
kever.yang at rock-chips.com
Fri Dec 24 07:55:10 CET 2021
On 2021/11/16 上午1:38, Jagan Teki wrote:
> Sync the px30 devicetree files from linux-next tree.
>
> commit <14ce8069f48b> ("lib/stackdepot: allow optional init and
> stack_table allocation by kvmalloc() - fixup3")
>
> Note, this path even sync rk3326 files as it depends on px30.
>
> Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>
Thanks,
- Kever
> ---
> Changes for v2:
> - add sync on v5.15
> - add sync on rk3326
>
> arch/arm/dts/Makefile | 4 +-
> arch/arm/dts/px30-engicam-common.dtsi | 90 ++++++
> arch/arm/dts/px30-engicam-ctouch2.dtsi | 22 ++
> arch/arm/dts/px30-engicam-edimm2.2.dtsi | 59 ++++
> .../px30-engicam-px30-core-ctouch2-of10.dts | 77 +++++
> ...dts => px30-engicam-px30-core-ctouch2.dts} | 4 +-
> .../dts/px30-engicam-px30-core-edimm2.2.dts | 43 +++
> ...-core.dtsi => px30-engicam-px30-core.dtsi} | 11 +-
> arch/arm/dts/px30-evb.dts | 143 ++++++++--
> arch/arm/dts/px30-px30-core-edimm2.2.dts | 21 --
> arch/arm/dts/px30-u-boot.dtsi | 4 +
> arch/arm/dts/px30.dtsi | 270 +++++++++++++-----
> arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 2 +-
> arch/arm/dts/rk3326-odroid-go2.dts | 178 +++---------
> configs/px30-core-ctouch2-px30_defconfig | 4 +-
> configs/px30-core-edimm2.2-px30_defconfig | 4 +-
> 16 files changed, 681 insertions(+), 255 deletions(-)
> create mode 100644 arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
> rename arch/arm/dts/{px30-px30-core-ctouch2.dts => px30-engicam-px30-core-ctouch2.dts} (80%)
> create mode 100644 arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
> rename arch/arm/dts/{px30-px30-core.dtsi => px30-engicam-px30-core.dtsi} (96%)
> delete mode 100644 arch/arm/dts/px30-px30-core-edimm2.2.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index cc34da7bd8..57a33d0bc4 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -78,8 +78,8 @@ dtb-$(CONFIG_MACH_S700) += \
> dtb-$(CONFIG_ROCKCHIP_PX30) += \
> px30-evb.dtb \
> px30-firefly.dtb \
> - px30-px30-core-ctouch2.dtb \
> - px30-px30-core-edimm2.2.dtb \
> + px30-engicam-px30-core-ctouch2.dtb \
> + px30-engicam-px30-core-edimm2.2.dtb \
> rk3326-odroid-go2.dtb
>
> dtb-$(CONFIG_ROCKCHIP_RK3036) += \
> diff --git a/arch/arm/dts/px30-engicam-common.dtsi b/arch/arm/dts/px30-engicam-common.dtsi
> index bd5bde989e..3429e124d9 100644
> --- a/arch/arm/dts/px30-engicam-common.dtsi
> +++ b/arch/arm/dts/px30-engicam-common.dtsi
> @@ -6,6 +6,11 @@
> */
>
> / {
> + aliases {
> + mmc1 = &sdmmc;
> + mmc2 = &sdio;
> + };
> +
> vcc5v0_sys: vcc5v0-sys {
> compatible = "regulator-fixed";
> regulator-name = "vcc5v0_sys"; /* +5V */
> @@ -14,6 +19,63 @@
> regulator-min-microvolt = <5000000>;
> regulator-max-microvolt = <5000000>;
> };
> +
> + sdio_pwrseq: sdio-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + clocks = <&xin32k>;
> + clock-names = "ext_clock";
> + post-power-on-delay-ms = <80>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&wifi_enable_h>;
> + };
> +
> + vcc3v3_btreg: vcc3v3-btreg {
> + compatible = "regulator-gpio";
> + enable-active-high;
> + pinctrl-names = "default";
> + pinctrl-0 = <&bt_enable_h>;
> + regulator-name = "btreg-gpio-supply";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + states = <3300000 0x0>;
> + };
> +
> + vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3_rf_aux_mod";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <&vcc5v0_sys>;
> + };
> +
> + xin32k: xin32k {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "xin32k";
> + };
> +};
> +
> +&sdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-width = <4>;
> + clock-frequency = <50000000>;
> + cap-sdio-irq;
> + cap-sd-highspeed;
> + keep-power-in-suspend;
> + mmc-pwrseq = <&sdio_pwrseq>;
> + non-removable;
> + sd-uhs-sdr104;
> + status = "okay";
> +
> + brcmf: wifi at 1 {
> + compatible = "brcm,bcm4329-fmac";
> + reg = <1>;
> + };
> };
>
> &gmac {
> @@ -25,6 +87,10 @@
> status = "okay";
> };
>
> +&pwm0 {
> + status = "okay";
> +};
> +
> &sdmmc {
> cap-sd-highspeed;
> card-detect-delay = <800>;
> @@ -33,7 +99,31 @@
> status = "okay";
> };
>
> +&u2phy {
> + status = "okay";
> +
> + u2phy_host: host-port {
> + status = "okay";
> + };
> +
> + u2phy_otg: otg-port {
> + status = "okay";
> + };
> +};
> +
> &uart2 {
> pinctrl-0 = <&uart2m1_xfer>;
> status = "okay";
> };
> +
> +&usb20_otg {
> + status = "okay";
> +};
> +
> +&usb_host0_ehci {
> + status = "okay";
> +};
> +
> +&usb_host0_ohci {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi b/arch/arm/dts/px30-engicam-ctouch2.dtsi
> index 58425b1e55..bf10a3d29f 100644
> --- a/arch/arm/dts/px30-engicam-ctouch2.dtsi
> +++ b/arch/arm/dts/px30-engicam-ctouch2.dtsi
> @@ -6,3 +6,25 @@
> */
>
> #include "px30-engicam-common.dtsi"
> +
> +&pinctrl {
> + bt {
> + bt_enable_h: bt-enable-h {
> + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + sdio-pwrseq {
> + wifi_enable_h: wifi-enable-h {
> + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +};
> +
> +&sdio_pwrseq {
> + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
> +};
> +
> +&vcc3v3_btreg {
> + enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
> +};
> diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
> index cb00988953..449b8eb645 100644
> --- a/arch/arm/dts/px30-engicam-edimm2.2.dtsi
> +++ b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
> @@ -5,3 +5,62 @@
> */
>
> #include "px30-engicam-common.dtsi"
> +
> +/ {
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm0 0 25000 0>;
> + };
> +
> + panel {
> + compatible = "yes-optoelectronics,ytc700tlag-05-201c";
> + backlight = <&backlight>;
> + data-mapping = "vesa-24";
> + power-supply = <&vcc3v3_lcd>;
> +
> + port {
> + panel_in_lvds: endpoint {
> + remote-endpoint = <&lvds_out_panel>;
> + };
> + };
> + };
> +};
> +
> +&display_subsystem {
> + status = "okay";
> +};
> +
> +&dsi_dphy {
> + status = "okay";
> +};
> +
> +/* LVDS_B(secondary) */
> +&lvds {
> + status = "okay";
> +
> + ports {
> + port at 1 {
> + reg = <1>;
> +
> + lvds_out_panel: endpoint {
> + remote-endpoint = <&panel_in_lvds>;
> + };
> + };
> + };
> +};
> +
> +&vopb {
> + status = "okay";
> +};
> +
> +&vopb_mmu {
> + status = "okay";
> +};
> +
> +&vopl {
> + status = "okay";
> +};
> +
> +&vopl_mmu {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
> new file mode 100644
> index 0000000000..47aa30505a
> --- /dev/null
> +++ b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
> + * Copyright (c) 2020 Engicam srl
> + * Copyright (c) 2020 Amarula Solutions(India)
> + */
> +
> +/dts-v1/;
> +#include "px30.dtsi"
> +#include "px30-engicam-ctouch2.dtsi"
> +#include "px30-engicam-px30-core.dtsi"
> +
> +/ {
> + model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame";
> + compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core",
> + "rockchip,px30";
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm0 0 25000 0>;
> + };
> +
> + chosen {
> + stdout-path = "serial2:115200n8";
> + };
> +
> + panel {
> + compatible = "ampire,am-1280800n3tzqw-t00h";
> + backlight = <&backlight>;
> + power-supply = <&vcc3v3_lcd>;
> + data-mapping = "vesa-24";
> +
> + port {
> + panel_in_lvds: endpoint {
> + remote-endpoint = <&lvds_out_panel>;
> + };
> + };
> + };
> +};
> +
> +&display_subsystem {
> + status = "okay";
> +};
> +
> +&dsi_dphy {
> + status = "okay";
> +};
> +
> +&lvds {
> + status = "okay";
> +
> + ports {
> + port at 1 {
> + reg = <1>;
> +
> + lvds_out_panel: endpoint {
> + remote-endpoint = <&panel_in_lvds>;
> + };
> + };
> + };
> +};
> +
> +&vopb {
> + status = "okay";
> +};
> +
> +&vopb_mmu {
> + status = "okay";
> +};
> +
> +&vopl {
> + status = "okay";
> +};
> +
> +&vopl_mmu {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/px30-px30-core-ctouch2.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
> similarity index 80%
> rename from arch/arm/dts/px30-px30-core-ctouch2.dts
> rename to arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
> index 2da0128188..5a0ecb8fae 100644
> --- a/arch/arm/dts/px30-px30-core-ctouch2.dts
> +++ b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
> @@ -9,11 +9,11 @@
> /dts-v1/;
> #include "px30.dtsi"
> #include "px30-engicam-ctouch2.dtsi"
> -#include "px30-px30-core.dtsi"
> +#include "px30-engicam-px30-core.dtsi"
>
> / {
> model = "Engicam PX30.Core C.TOUCH 2.0";
> - compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core",
> + compatible = "engicam,px30-core-ctouch2", "engicam,px30-core",
> "rockchip,px30";
>
> chosen {
> diff --git a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
> new file mode 100644
> index 0000000000..d759478e1c
> --- /dev/null
> +++ b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
> + * Copyright (c) 2020 Engicam srl
> + * Copyright (c) 2020 Amarula Solutions(India)
> + */
> +
> +/dts-v1/;
> +#include "px30.dtsi"
> +#include "px30-engicam-edimm2.2.dtsi"
> +#include "px30-engicam-px30-core.dtsi"
> +
> +/ {
> + model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
> + compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core",
> + "rockchip,px30";
> +
> + chosen {
> + stdout-path = "serial2:115200n8";
> + };
> +};
> +
> +&pinctrl {
> + bt {
> + bt_enable_h: bt-enable-h {
> + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + sdio-pwrseq {
> + wifi_enable_h: wifi-enable-h {
> + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +};
> +
> +&sdio_pwrseq {
> + reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
> +};
> +
> +&vcc3v3_btreg {
> + enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
> +};
> diff --git a/arch/arm/dts/px30-px30-core.dtsi b/arch/arm/dts/px30-engicam-px30-core.dtsi
> similarity index 96%
> rename from arch/arm/dts/px30-px30-core.dtsi
> rename to arch/arm/dts/px30-engicam-px30-core.dtsi
> index 16e6cf28a4..7249871530 100644
> --- a/arch/arm/dts/px30-px30-core.dtsi
> +++ b/arch/arm/dts/px30-engicam-px30-core.dtsi
> @@ -10,7 +10,11 @@
> #include <dt-bindings/pinctrl/rockchip.h>
>
> / {
> - compatible = "engicam,px30-px30-core", "rockchip,px30";
> + compatible = "engicam,px30-core", "rockchip,px30";
> +
> + aliases {
> + mmc0 = &emmc;
> + };
> };
>
> &cpu0 {
> @@ -192,6 +196,11 @@
> };
> };
>
> + vcc3v3_lcd: SWITCH_REG1 {
> + regulator-boot-on;
> + regulator-name = "vcc3v3_lcd";
> + };
> +
> vcc5v0_host: SWITCH_REG2 {
> regulator-name = "vcc5v0_host";
> regulator-always-on;
> diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts
> index 4134e2ee13..848bc39cf8 100644
> --- a/arch/arm/dts/px30-evb.dts
> +++ b/arch/arm/dts/px30-evb.dts
> @@ -13,8 +13,14 @@
> model = "Rockchip PX30 EVB";
> compatible = "rockchip,px30-evb", "rockchip,px30";
>
> + aliases {
> + mmc0 = &sdmmc;
> + mmc1 = &sdio;
> + mmc2 = &emmc;
> + };
> +
> chosen {
> - stdout-path = "serial2:115200n8";
> + stdout-path = "serial5:115200n8";
> };
>
> adc-keys {
> @@ -108,6 +114,10 @@
> cpu-supply = <&vdd_arm>;
> };
>
> +&csi_dphy {
> + status = "okay";
> +};
> +
> &display_subsystem {
> status = "okay";
> };
> @@ -126,22 +136,15 @@
> };
>
> panel at 0 {
> - compatible = "sitronix,st7703";
> + compatible = "xinpeng,xpp055c272";
> reg = <0>;
> backlight = <&backlight>;
> iovcc-supply = <&vcc_1v8>;
> vci-supply = <&vcc3v3_lcd>;
>
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port at 0 {
> - reg = <0>;
> -
> - mipi_in_panel: endpoint {
> - remote-endpoint = <&mipi_out_panel>;
> - };
> + port {
> + mipi_in_panel: endpoint {
> + remote-endpoint = <&mipi_out_panel>;
> };
> };
> };
> @@ -152,7 +155,6 @@
> };
>
> &emmc {
> - bus-width = <8>;
> cap-mmc-highspeed;
> mmc-hs200-1_8v;
> non-removable;
> @@ -171,6 +173,11 @@
> status = "okay";
> };
>
> +&gpu {
> + mali-supply = <&vdd_log>;
> + status = "okay";
> +};
> +
> &i2c0 {
> status = "okay";
>
> @@ -388,6 +395,73 @@
> };
> };
>
> +&i2c1 {
> + status = "okay";
> +
> + sensor at d {
> + compatible = "asahi-kasei,ak8963";
> + reg = <0x0d>;
> + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
> + vdd-supply = <&vcc3v0_pmu>;
> + mount-matrix = "1", /* x0 */
> + "0", /* y0 */
> + "0", /* z0 */
> + "0", /* x1 */
> + "1", /* y1 */
> + "0", /* z1 */
> + "0", /* x2 */
> + "0", /* y2 */
> + "1"; /* z2 */
> + };
> +
> + touchscreen at 14 {
> + compatible = "goodix,gt1151";
> + reg = <0x14>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
> + irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
> + reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> + VDDIO-supply = <&vcc3v3_lcd>;
> + };
> +
> + sensor at 4c {
> + compatible = "fsl,mma7660";
> + reg = <0x4c>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> +
> +&i2c2 {
> + status = "okay";
> +
> + clock-frequency = <100000>;
> +
> + /* These are relatively safe rise/fall times; TODO: measure */
> + i2c-scl-falling-time-ns = <50>;
> + i2c-scl-rising-time-ns = <300>;
> +
> + ov5695: ov5695 at 36 {
> + compatible = "ovti,ov5695";
> + reg = <0x36>;
> + avdd-supply = <&vcc2v8_dvp>;
> + clocks = <&cru SCLK_CIF_OUT>;
> + clock-names = "xvclk";
> + dvdd-supply = <&vcc1v5_dvp>;
> + dovdd-supply = <&vcc1v8_dvp>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&cif_clkout_m0>;
> + reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
> +
> + port {
> + ucam_out: endpoint {
> + remote-endpoint = <&mipi_in_ucam>;
> + data-lanes = <1 2>;
> + };
> + };
> + };
> +};
> +
> &i2s1_2ch {
> status = "okay";
> };
> @@ -403,6 +477,24 @@
> vccio6-supply = <&vccio_flash>;
> };
>
> +&isp {
> + status = "okay";
> +
> + ports {
> + port at 0 {
> + mipi_in_ucam: endpoint at 0 {
> + reg = <0>;
> + data-lanes = <1 2>;
> + remote-endpoint = <&ucam_out>;
> + };
> + };
> + };
> +};
> +
> +&isp_mmu {
> + status = "okay";
> +};
> +
> &pinctrl {
> headphone {
> hp_det: hp-det {
> @@ -464,7 +556,6 @@
> };
>
> &sdmmc {
> - bus-width = <4>;
> cap-mmc-highspeed;
> cap-sd-highspeed;
> card-detect-delay = <800>;
> @@ -474,10 +565,10 @@
> sd-uhs-sdr104;
> vmmc-supply = <&vcc_sd>;
> vqmmc-supply = <&vccio_sd>;
> + status = "okay";
> };
>
> &sdio {
> - bus-width = <4>;
> cap-sd-highspeed;
> keep-power-in-suspend;
> non-removable;
> @@ -486,13 +577,27 @@
> status = "okay";
> };
>
> -&uart1 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&uart1_xfer &uart1_cts>;
> +&tsadc {
> + rockchip,hw-tshut-mode = <1>;
> + rockchip,hw-tshut-polarity = <1>;
> status = "okay";
> };
>
> -&uart2 {
> +&u2phy {
> + status = "okay";
> +
> + u2phy_host: host-port {
> + status = "okay";
> + };
> +
> + u2phy_otg: otg-port {
> + status = "okay";
> + };
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_xfer &uart1_cts>;
> status = "okay";
> };
>
> diff --git a/arch/arm/dts/px30-px30-core-edimm2.2.dts b/arch/arm/dts/px30-px30-core-edimm2.2.dts
> deleted file mode 100644
> index c36280ce7f..0000000000
> --- a/arch/arm/dts/px30-px30-core-edimm2.2.dts
> +++ /dev/null
> @@ -1,21 +0,0 @@
> -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> -/*
> - * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
> - * Copyright (c) 2020 Engicam srl
> - * Copyright (c) 2020 Amarula Solutions(India)
> - */
> -
> -/dts-v1/;
> -#include "px30.dtsi"
> -#include "px30-engicam-edimm2.2.dtsi"
> -#include "px30-px30-core.dtsi"
> -
> -/ {
> - model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
> - compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core",
> - "rockchip,px30";
> -
> - chosen {
> - stdout-path = "serial2:115200n8";
> - };
> -};
> diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
> index bbed7dcde5..f102b2aef4 100644
> --- a/arch/arm/dts/px30-u-boot.dtsi
> +++ b/arch/arm/dts/px30-u-boot.dtsi
> @@ -64,10 +64,14 @@
>
> &cru {
> u-boot,dm-pre-reloc;
> + /delete-property/ assigned-clocks;
> + /delete-property/ assigned-clock-rates;
> };
>
> &pmucru {
> u-boot,dm-pre-reloc;
> + /delete-property/ assigned-clocks;
> + /delete-property/ assigned-clock-rates;
> };
>
> &saradc {
> diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
> index ef77b7b997..00f50b05d5 100644
> --- a/arch/arm/dts/px30.dtsi
> +++ b/arch/arm/dts/px30.dtsi
> @@ -110,7 +110,7 @@
> };
> };
>
> - cpu0_opp_table: cpu0-opp-table {
> + cpu0_opp_table: opp-table-0 {
> compatible = "operating-points-v2";
> opp-shared;
>
> @@ -143,7 +143,7 @@
> };
>
> arm-pmu {
> - compatible = "arm,cortex-a53-pmu";
> + compatible = "arm,cortex-a35-pmu";
> interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> @@ -244,28 +244,31 @@
> #size-cells = <0>;
>
> /* These power domains are grouped by VD_LOGIC */
> - pd_usb at PX30_PD_USB {
> + power-domain at PX30_PD_USB {
> reg = <PX30_PD_USB>;
> clocks = <&cru HCLK_HOST>,
> <&cru HCLK_OTG>,
> <&cru SCLK_OTG_ADP>;
> pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
> + #power-domain-cells = <0>;
> };
> - pd_sdcard at PX30_PD_SDCARD {
> + power-domain at PX30_PD_SDCARD {
> reg = <PX30_PD_SDCARD>;
> clocks = <&cru HCLK_SDMMC>,
> <&cru SCLK_SDMMC>;
> pm_qos = <&qos_sdmmc>;
> + #power-domain-cells = <0>;
> };
> - pd_gmac at PX30_PD_GMAC {
> + power-domain at PX30_PD_GMAC {
> reg = <PX30_PD_GMAC>;
> clocks = <&cru ACLK_GMAC>,
> <&cru PCLK_GMAC>,
> <&cru SCLK_MAC_REF>,
> <&cru SCLK_GMAC_RX_TX>;
> pm_qos = <&qos_gmac>;
> + #power-domain-cells = <0>;
> };
> - pd_mmc_nand at PX30_PD_MMC_NAND {
> + power-domain at PX30_PD_MMC_NAND {
> reg = <PX30_PD_MMC_NAND>;
> clocks = <&cru HCLK_NANDC>,
> <&cru HCLK_EMMC>,
> @@ -277,15 +280,17 @@
> <&cru SCLK_SFC>;
> pm_qos = <&qos_emmc>, <&qos_nand>,
> <&qos_sdio>, <&qos_sfc>;
> + #power-domain-cells = <0>;
> };
> - pd_vpu at PX30_PD_VPU {
> + power-domain at PX30_PD_VPU {
> reg = <PX30_PD_VPU>;
> clocks = <&cru ACLK_VPU>,
> <&cru HCLK_VPU>,
> <&cru SCLK_CORE_VPU>;
> pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
> + #power-domain-cells = <0>;
> };
> - pd_vo at PX30_PD_VO {
> + power-domain at PX30_PD_VO {
> reg = <PX30_PD_VO>;
> clocks = <&cru ACLK_RGA>,
> <&cru ACLK_VOPB>,
> @@ -300,8 +305,9 @@
> <&cru SCLK_VOPB_PWM>;
> pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
> <&qos_vop_m0>, <&qos_vop_m1>;
> + #power-domain-cells = <0>;
> };
> - pd_vi at PX30_PD_VI {
> + power-domain at PX30_PD_VI {
> reg = <PX30_PD_VI>;
> clocks = <&cru ACLK_CIF>,
> <&cru ACLK_ISP>,
> @@ -311,11 +317,13 @@
> pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
> <&qos_isp_wr>, <&qos_isp_m1>,
> <&qos_vip>;
> + #power-domain-cells = <0>;
> };
> - pd_gpu at PX30_PD_GPU {
> + power-domain at PX30_PD_GPU {
> reg = <PX30_PD_GPU>;
> clocks = <&cru SCLK_GPU>;
> pm_qos = <&qos_gpu>;
> + #power-domain-cells = <0>;
> };
> };
> };
> @@ -600,7 +608,7 @@
> };
>
> wdt: watchdog at ff1e0000 {
> - compatible = "snps,dw-wdt";
> + compatible = "rockchip,px30-wdt", "snps,dw-wdt";
> reg = <0x0 0xff1e0000 0x0 0x100>;
> clocks = <&cru PCLK_WDT_NS>;
> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> @@ -703,21 +711,15 @@
> clock-names = "pclk", "timer";
> };
>
> - amba {
> - compatible = "simple-bus";
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> -
> - dmac: dmac at ff240000 {
> - compatible = "arm,pl330", "arm,primecell";
> - reg = <0x0 0xff240000 0x0 0x4000>;
> - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cru ACLK_DMAC>;
> - clock-names = "apb_pclk";
> - #dma-cells = <1>;
> - };
> + dmac: dmac at ff240000 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x0 0xff240000 0x0 0x4000>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + arm,pl330-periph-burst;
> + clocks = <&cru ACLK_DMAC>;
> + clock-names = "apb_pclk";
> + #dma-cells = <1>;
> };
>
> tsadc: tsadc at ff280000 {
> @@ -733,9 +735,9 @@
> rockchip,grf = <&grf>;
> rockchip,hw-tshut-temp = <120000>;
> pinctrl-names = "init", "default", "sleep";
> - pinctrl-0 = <&tsadc_otp_gpio>;
> + pinctrl-0 = <&tsadc_otp_pin>;
> pinctrl-1 = <&tsadc_otp_out>;
> - pinctrl-2 = <&tsadc_otp_gpio>;
> + pinctrl-2 = <&tsadc_otp_pin>;
> #thermal-sensor-cells = <1>;
> status = "disabled";
> };
> @@ -784,6 +786,16 @@
> rockchip,grf = <&grf>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> +
> + assigned-clocks = <&cru PLL_NPLL>,
> + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
> + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
> + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
> +
> + assigned-clock-rates = <1188000000>,
> + <200000000>, <200000000>,
> + <150000000>, <150000000>,
> + <100000000>, <200000000>;
> };
>
> pmucru: clock-controller at ff2bc000 {
> @@ -794,6 +806,13 @@
> rockchip,grf = <&grf>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> +
> + assigned-clocks =
> + <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
> + <&pmucru SCLK_WIFI_PMU>;
> + assigned-clock-rates =
> + <1200000000>, <100000000>,
> + <26000000>;
> };
>
> usb2phy_grf: syscon at ff2c0000 {
> @@ -803,7 +822,7 @@
> #address-cells = <1>;
> #size-cells = <1>;
>
> - u2phy: usb2-phy at 100 {
> + u2phy: usb2phy at 100 {
> compatible = "rockchip,px30-usb2phy";
> reg = <0x100 0x20>;
> clocks = <&pmucru SCLK_USBPHY_REF>;
> @@ -845,6 +864,19 @@
> status = "disabled";
> };
>
> + csi_dphy: phy at ff2f0000 {
> + compatible = "rockchip,px30-csi-dphy";
> + reg = <0x0 0xff2f0000 0x0 0x4000>;
> + clocks = <&cru PCLK_MIPICSIPHY>;
> + clock-names = "pclk";
> + #phy-cells = <0>;
> + power-domains = <&power PX30_PD_VI>;
> + resets = <&cru SRST_MIPICSIPHY_P>;
> + reset-names = "apb";
> + rockchip,grf = <&grf>;
> + status = "disabled";
> + };
> +
> usb20_otg: usb at ff300000 {
> compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
> "snps,dwc2";
> @@ -856,7 +888,6 @@
> g-np-tx-fifo-size = <16>;
> g-rx-fifo-size = <280>;
> g-tx-fifo-size = <256 128 128 64 32 16>;
> - g-use-dma;
> phys = <&u2phy_otg>;
> phy-names = "usb2-phy";
> power-domains = <&power PX30_PD_USB>;
> @@ -868,7 +899,6 @@
> reg = <0x0 0xff340000 0x0 0x10000>;
> interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru HCLK_HOST>;
> - clock-names = "usbhost";
> phys = <&u2phy_host>;
> phy-names = "usb";
> power-domains = <&power PX30_PD_USB>;
> @@ -880,7 +910,6 @@
> reg = <0x0 0xff350000 0x0 0x10000>;
> interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru HCLK_HOST>;
> - clock-names = "usbhost";
> phys = <&u2phy_host>;
> phy-names = "usb";
> power-domains = <&power PX30_PD_USB>;
> @@ -910,13 +939,14 @@
> status = "disabled";
> };
>
> - sdmmc: dwmmc at ff370000 {
> + sdmmc: mmc at ff370000 {
> compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
> reg = <0x0 0xff370000 0x0 0x4000>;
> interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
> <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
> - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + bus-width = <4>;
> fifo-depth = <0x100>;
> max-frequency = <150000000>;
> pinctrl-names = "default";
> @@ -925,13 +955,14 @@
> status = "disabled";
> };
>
> - sdio: dwmmc at ff380000 {
> + sdio: mmc at ff380000 {
> compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
> reg = <0x0 0xff380000 0x0 0x4000>;
> interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
> <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
> - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + bus-width = <4>;
> fifo-depth = <0x100>;
> max-frequency = <150000000>;
> pinctrl-names = "default";
> @@ -940,13 +971,14 @@
> status = "disabled";
> };
>
> - emmc: dwmmc at ff390000 {
> + emmc: mmc at ff390000 {
> compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
> reg = <0x0 0xff390000 0x0 0x4000>;
> interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
> <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
> - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + bus-width = <8>;
> fifo-depth = <0x100>;
> max-frequency = <150000000>;
> pinctrl-names = "default";
> @@ -955,18 +987,54 @@
> status = "disabled";
> };
>
> - sfc: sfc at ff3a0000 {
> + sfc: spi at ff3a0000 {
> compatible = "rockchip,sfc";
> reg = <0x0 0xff3a0000 0x0 0x4000>;
> interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
> clock-names = "clk_sfc", "hclk_sfc";
> - pinctrl-names = "default";
> pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
> + pinctrl-names = "default";
> + power-domains = <&power PX30_PD_MMC_NAND>;
> + status = "disabled";
> + };
> +
> + nfc: nand-controller at ff3b0000 {
> + compatible = "rockchip,px30-nfc";
> + reg = <0x0 0xff3b0000 0x0 0x4000>;
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
> + clock-names = "ahb", "nfc";
> + assigned-clocks = <&cru SCLK_NANDC>;
> + assigned-clock-rates = <150000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
> + &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
> power-domains = <&power PX30_PD_MMC_NAND>;
> status = "disabled";
> };
>
> + gpu_opp_table: opp-table-1 {
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-microvolt = <950000>;
> + };
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + opp-microvolt = <975000>;
> + };
> + opp-400000000 {
> + opp-hz = /bits/ 64 <400000000>;
> + opp-microvolt = <1050000>;
> + };
> + opp-480000000 {
> + opp-hz = /bits/ 64 <480000000>;
> + opp-microvolt = <1125000>;
> + };
> + };
> +
> gpu: gpu at ff400000 {
> compatible = "rockchip,px30-mali", "arm,mali-bifrost";
> reg = <0x0 0xff400000 0x0 0x4000>;
> @@ -977,9 +1045,32 @@
> clocks = <&cru SCLK_GPU>;
> #cooling-cells = <2>;
> power-domains = <&power PX30_PD_GPU>;
> + operating-points-v2 = <&gpu_opp_table>;
> status = "disabled";
> };
>
> + vpu: video-codec at ff442000 {
> + compatible = "rockchip,px30-vpu";
> + reg = <0x0 0xff442000 0x0 0x800>;
> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "vepu", "vdpu";
> + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
> + clock-names = "aclk", "hclk";
> + iommus = <&vpu_mmu>;
> + power-domains = <&power PX30_PD_VPU>;
> + };
> +
> + vpu_mmu: iommu at ff442800 {
> + compatible = "rockchip,iommu";
> + reg = <0x0 0xff442800 0x0 0x100>;
> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
> + clock-names = "aclk", "iface";
> + #iommu-cells = <0>;
> + power-domains = <&power PX30_PD_VPU>;
> + };
> +
> dsi: dsi at ff450000 {
> compatible = "rockchip,px30-mipi-dsi";
> reg = <0x0 0xff450000 0x0 0x10000>;
> @@ -1029,7 +1120,6 @@
> reset-names = "axi", "ahb", "dclk";
> iommus = <&vopb_mmu>;
> power-domains = <&power PX30_PD_VO>;
> - rockchip,grf = <&grf>;
> status = "disabled";
>
> vopb_out: port {
> @@ -1052,7 +1142,6 @@
> compatible = "rockchip,iommu";
> reg = <0x0 0xff460f00 0x0 0x100>;
> interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "vopb_mmu";
> clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
> clock-names = "aclk", "iface";
> power-domains = <&power PX30_PD_VO>;
> @@ -1071,7 +1160,6 @@
> reset-names = "axi", "ahb", "dclk";
> iommus = <&vopl_mmu>;
> power-domains = <&power PX30_PD_VO>;
> - rockchip,grf = <&grf>;
> status = "disabled";
>
> vopl_out: port {
> @@ -1093,8 +1181,7 @@
> vopl_mmu: iommu at ff470f00 {
> compatible = "rockchip,iommu";
> reg = <0x0 0xff470f00 0x0 0x100>;
> - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "vopl_mmu";
> + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
> clock-names = "aclk", "iface";
> power-domains = <&power PX30_PD_VO>;
> @@ -1102,103 +1189,144 @@
> status = "disabled";
> };
>
> + isp: isp at ff4a0000 {
> + compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
> + reg = <0x0 0xff4a0000 0x0 0x8000>;
> + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "isp", "mi", "mipi";
> + clocks = <&cru SCLK_ISP>,
> + <&cru ACLK_ISP>,
> + <&cru HCLK_ISP>,
> + <&cru PCLK_ISP>;
> + clock-names = "isp", "aclk", "hclk", "pclk";
> + iommus = <&isp_mmu>;
> + phys = <&csi_dphy>;
> + phy-names = "dphy";
> + power-domains = <&power PX30_PD_VI>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> + };
> +
> + isp_mmu: iommu at ff4a8000 {
> + compatible = "rockchip,iommu";
> + reg = <0x0 0xff4a8000 0x0 0x100>;
> + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
> + clock-names = "aclk", "iface";
> + power-domains = <&power PX30_PD_VI>;
> + rockchip,disable-mmu-reset;
> + #iommu-cells = <0>;
> + };
> +
> qos_gmac: qos at ff518000 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff518000 0x0 0x20>;
> };
>
> qos_gpu: qos at ff520000 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff520000 0x0 0x20>;
> };
>
> qos_sdmmc: qos at ff52c000 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff52c000 0x0 0x20>;
> };
>
> qos_emmc: qos at ff538000 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff538000 0x0 0x20>;
> };
>
> qos_nand: qos at ff538080 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff538080 0x0 0x20>;
> };
>
> qos_sdio: qos at ff538100 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff538100 0x0 0x20>;
> };
>
> qos_sfc: qos at ff538180 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff538180 0x0 0x20>;
> };
>
> qos_usb_host: qos at ff540000 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff540000 0x0 0x20>;
> };
>
> qos_usb_otg: qos at ff540080 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff540080 0x0 0x20>;
> };
>
> qos_isp_128: qos at ff548000 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff548000 0x0 0x20>;
> };
>
> qos_isp_rd: qos at ff548080 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff548080 0x0 0x20>;
> };
>
> qos_isp_wr: qos at ff548100 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff548100 0x0 0x20>;
> };
>
> qos_isp_m1: qos at ff548180 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff548180 0x0 0x20>;
> };
>
> qos_vip: qos at ff548200 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff548200 0x0 0x20>;
> };
>
> qos_rga_rd: qos at ff550000 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff550000 0x0 0x20>;
> };
>
> qos_rga_wr: qos at ff550080 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff550080 0x0 0x20>;
> };
>
> qos_vop_m0: qos at ff550100 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff550100 0x0 0x20>;
> };
>
> qos_vop_m1: qos at ff550180 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff550180 0x0 0x20>;
> };
>
> qos_vpu: qos at ff558000 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff558000 0x0 0x20>;
> };
>
> qos_vpu_r128: qos at ff558080 {
> - compatible = "syscon";
> + compatible = "rockchip,px30-qos", "syscon";
> reg = <0x0 0xff558080 0x0 0x20>;
> };
>
> @@ -1210,7 +1338,7 @@
> #size-cells = <2>;
> ranges;
>
> - gpio0: gpio0 at ff040000 {
> + gpio0: gpio at ff040000 {
> compatible = "rockchip,gpio-bank";
> reg = <0x0 0xff040000 0x0 0x100>;
> interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1222,7 +1350,7 @@
> #interrupt-cells = <2>;
> };
>
> - gpio1: gpio1 at ff250000 {
> + gpio1: gpio at ff250000 {
> compatible = "rockchip,gpio-bank";
> reg = <0x0 0xff250000 0x0 0x100>;
> interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1234,7 +1362,7 @@
> #interrupt-cells = <2>;
> };
>
> - gpio2: gpio2 at ff260000 {
> + gpio2: gpio at ff260000 {
> compatible = "rockchip,gpio-bank";
> reg = <0x0 0xff260000 0x0 0x100>;
> interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1246,7 +1374,7 @@
> #interrupt-cells = <2>;
> };
>
> - gpio3: gpio3 at ff270000 {
> + gpio3: gpio at ff270000 {
> compatible = "rockchip,gpio-bank";
> reg = <0x0 0xff270000 0x0 0x100>;
> interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1370,7 +1498,7 @@
> };
>
> tsadc {
> - tsadc_otp_gpio: tsadc-otp-gpio {
> + tsadc_otp_pin: tsadc-otp-pin {
> rockchip,pins =
> <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> @@ -1933,7 +2061,7 @@
> };
> };
>
> - serial_flash {
> + sfc {
> sfc_bus4: sfc-bus4 {
> rockchip,pins =
> <1 RK_PA0 3 &pcfg_pull_none>,
> diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> index 63d87e16e1..87f277f78e 100644
> --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> @@ -82,7 +82,7 @@
> u-boot,dm-pre-reloc;
> };
>
> -&{/sfc at ff3a0000/flash at 0} {
> +&{/spi at ff3a0000/flash at 0} {
> u-boot,dm-pre-reloc;
> };
>
> diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
> index 4e3dceecbe..ea0695b51e 100644
> --- a/arch/arm/dts/rk3326-odroid-go2.dts
> +++ b/arch/arm/dts/rk3326-odroid-go2.dts
> @@ -14,14 +14,12 @@
> model = "ODROID-GO Advance";
> compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
>
> - chosen {
> - stdout-path = "serial2:115200n8";
> + aliases {
> + mmc0 = &sdmmc;
> };
>
> - backlight: backlight {
> - compatible = "pwm-backlight";
> - power-supply = <&vcc_bl>;
> - pwms = <&pwm1 0 25000 0>;
> + chosen {
> + stdout-path = "serial2:115200n8";
> };
>
> adc-joystick {
> @@ -33,21 +31,27 @@
>
> axis at 0 {
> reg = <0>;
> - abs-range = <172 772>;
> - abs-fuzz = <10>;
> abs-flat = <10>;
> + abs-fuzz = <10>;
> + abs-range = <172 772>;
> linux,code = <ABS_X>;
> };
>
> axis at 1 {
> reg = <1>;
> - abs-range = <278 815>;
> - abs-fuzz = <10>;
> abs-flat = <10>;
> + abs-fuzz = <10>;
> + abs-range = <278 815>;
> linux,code = <ABS_Y>;
> };
> };
>
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + power-supply = <&vcc_bl>;
> + pwms = <&pwm1 0 25000 0>;
> + };
> +
> gpio-keys {
> compatible = "gpio-keys";
> pinctrl-names = "default";
> @@ -163,25 +167,26 @@
>
> rk817-sound {
> compatible = "simple-audio-card";
> + simple-audio-card,name = "Analog";
> simple-audio-card,format = "i2s";
> - simple-audio-card,name = "rockchip,rk817-codec";
> + simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
> simple-audio-card,mclk-fs = <256>;
> simple-audio-card,widgets =
> "Microphone", "Mic Jack",
> - "Headphone", "Headphone Jack";
> + "Headphone", "Headphones",
> + "Speaker", "Speaker";
> simple-audio-card,routing =
> - "MIC_IN", "Mic Jack",
> - "Headphone Jack", "HPOL",
> - "Headphone Jack", "HPOR";
> - simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
> - simple-audio-card,codec-hp-det = <1>;
> + "MICL", "Mic Jack",
> + "Headphones", "HPOL",
> + "Headphones", "HPOR",
> + "Speaker", "SPKO";
>
> - simple-audio-card,cpu {
> - sound-dai = <&i2s1_2ch>;
> + simple-audio-card,codec {
> + sound-dai = <&rk817>;
> };
>
> - simple-audio-card,codec {
> - sound-dai = <&rk817_codec>;
> + simple-audio-card,cpu {
> + sound-dai = <&i2s1_2ch>;
> };
> };
>
> @@ -202,7 +207,8 @@
> gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
> enable-active-high;
> regulator-always-on;
> - vin-supply = <&vccsys>;
> + regulator-boot-on;
> + vin-supply = <&usb_midu>;
> };
> };
>
> @@ -259,6 +265,7 @@
> backlight = <&backlight>;
> iovcc-supply = <&vcc_lcd>;
> reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
> + rotation = <270>;
> vdd-supply = <&vcc_lcd>;
>
> port {
> @@ -289,16 +296,14 @@
> reg = <0x20>;
> interrupt-parent = <&gpio0>;
> interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
> - pinctrl-names = "default", "pmic-sleep",
> - "pmic-power-off", "pmic-reset";
> - pinctrl-0 = <&pmic_int>;
> - pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
> - pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
> - pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
> - rockchip,system-power-controller;
> + clock-output-names = "rk808-clkout1", "xin32k";
> + clock-names = "mclk";
> + clocks = <&cru SCLK_I2S1_OUT>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
> wakeup-source;
> #clock-cells = <1>;
> - clock-output-names = "rk808-clkout1", "xin32k";
> + #sound-dai-cells = <0>;
>
> vcc1-supply = <&vccsys>;
> vcc2-supply = <&vccsys>;
> @@ -307,53 +312,7 @@
> vcc5-supply = <&vccsys>;
> vcc6-supply = <&vccsys>;
> vcc7-supply = <&vccsys>;
> -
> - pinctrl_rk8xx: pinctrl_rk8xx {
> - gpio-controller;
> - #gpio-cells = <2>;
> -
> - rk817_ts_gpio1: rk817_ts_gpio1 {
> - pins = "gpio_ts";
> - function = "pin_fun1";
> - /* output-low; */
> - /* input-enable; */
> - };
> -
> - rk817_gt_gpio2: rk817_gt_gpio2 {
> - pins = "gpio_gt";
> - function = "pin_fun1";
> - };
> -
> - rk817_pin_ts: rk817_pin_ts {
> - pins = "gpio_ts";
> - function = "pin_fun0";
> - };
> -
> - rk817_pin_gt: rk817_pin_gt {
> - pins = "gpio_gt";
> - function = "pin_fun0";
> - };
> -
> - rk817_slppin_null: rk817_slppin_null {
> - pins = "gpio_slp";
> - function = "pin_fun0";
> - };
> -
> - rk817_slppin_slp: rk817_slppin_slp {
> - pins = "gpio_slp";
> - function = "pin_fun1";
> - };
> -
> - rk817_slppin_pwrdn: rk817_slppin_pwrdn {
> - pins = "gpio_slp";
> - function = "pin_fun2";
> - };
> -
> - rk817_slppin_rst: rk817_slppin_rst {
> - pins = "gpio_slp";
> - function = "pin_fun3";
> - };
> - };
> + vcc8-supply = <&vccsys>;
>
> regulators {
> vdd_logic: DCDC_REG1 {
> @@ -503,66 +462,18 @@
> regulator-suspend-microvolt = <3000000>;
> };
> };
> - };
>
> - battery {
> - compatible = "rk817,battery";
> - ocv_table = <3500 3625 3685 3697 3718 3735 3748
> - 3760 3774 3788 3802 3816 3834 3853
> - 3877 3908 3946 3975 4018 4071 4106>;
> -
> - /* KPL605475 Battery Spec */
> - /*
> - Capacity : 3.7V 3000mA
> - Normal Voltage = 3.7V
> - Cut-Off Voltage : 3.1V
> - Internal Impedance : 180 mOhm
> - Charging Voltage : 4.2V
> - Charging Voltage Max : 4.25V
> - Sample resister : 10 mohm
> - */
> - design_capacity = <3000>;
> - design_qmax = <3000>;
> - bat_res = <180>;
> - sleep_enter_current = <300>;
> - sleep_exit_current = <300>;
> - sleep_filter_current = <100>;
> - power_off_thresd = <3500>;
> - zero_algorithm_vol = <3700>;
> - max_soc_offset = <60>;
> - monitor_sec = <5>;
> - virtual_power = <0>;
> - sample_res = <10>;
> - };
> -
> - charger {
> - compatible = "rk817,charger";
> - min_input_voltage = <4500>;
> - max_input_current = <1500>;
> - max_chrg_current = <2000>;
> - max_chrg_voltage = <4200>;
> - chrg_term_mode = <0>;
> - chrg_finish_cur = <300>;
> - virtual_power = <0>;
> - sample_res = <10>;
> -
> - /* P.C.B rev0.2 DC Detect & Charger Status LED GPIO */
> - dc_det_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
> - chg_led_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
> -
> - extcon = <&u2phy>;
> + usb_midu: BOOST {
> + regulator-name = "usb_midu";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5400000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> };
>
> rk817_codec: codec {
> - #sound-dai-cells = <0>;
> - compatible = "rockchip,rk817-codec";
> - clocks = <&cru SCLK_I2S1_OUT>;
> - clock-names = "mclk";
> - pinctrl-names = "default";
> - pinctrl-0 = <&i2s1_2ch_mclk>;
> - hp-volume = <20>;
> - spk-volume = <3>;
> - status = "okay";
> + rockchip,mic-in-differential;
> };
> };
> };
> @@ -604,7 +515,6 @@
> };
>
> &sdmmc {
> - bus-width = <4>;
> cap-sd-highspeed;
> card-detect-delay = <200>;
> cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
> diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig
> index a5dbbd7453..7d1920458e 100644
> --- a/configs/px30-core-ctouch2-px30_defconfig
> +++ b/configs/px30-core-ctouch2-px30_defconfig
> @@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_SPL_LIBCOMMON_SUPPORT=y
> CONFIG_SPL_LIBGENERIC_SUPPORT=y
> CONFIG_NR_DRAM_BANKS=1
> -CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2"
> +CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2"
> CONFIG_SPL_TEXT_BASE=0x00000000
> CONFIG_ROCKCHIP_PX30=y
> CONFIG_TARGET_PX30_CORE=y
> @@ -23,7 +23,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
> CONFIG_FIT=y
> CONFIG_FIT_VERBOSE=y
> CONFIG_SPL_LOAD_FIT=y
> -CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb"
> +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2.dtb"
> # CONFIG_CONSOLE_MUX is not set
> # CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig
> index 1e138d63ed..84c57337ce 100644
> --- a/configs/px30-core-edimm2.2-px30_defconfig
> +++ b/configs/px30-core-edimm2.2-px30_defconfig
> @@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_SPL_LIBCOMMON_SUPPORT=y
> CONFIG_SPL_LIBGENERIC_SUPPORT=y
> CONFIG_NR_DRAM_BANKS=1
> -CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2"
> +CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2"
> CONFIG_SPL_TEXT_BASE=0x00000000
> CONFIG_ROCKCHIP_PX30=y
> CONFIG_TARGET_PX30_CORE=y
> @@ -23,7 +23,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
> CONFIG_FIT=y
> CONFIG_FIT_VERBOSE=y
> CONFIG_SPL_LOAD_FIT=y
> -CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb"
> +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-edimm2.2.dtb"
> # CONFIG_CONSOLE_MUX is not set
> # CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
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