[PATCH] nvme: Fix cache alignment

[Marek Vasut]

On 2/2/21 2:04 PM, Andre Przywara wrote:

Hi,

[...]

>>> The various structures in the driver are already correcty padded and
>>
>> typo: correctly
>>
>>> cache aligned in memory, however the cache operations are called on
>>> the structure sizes, which themselves might not be cache aligned. Add
>>> the necessary rounding to fix this, which permits the nvme to work on
>>> arm64.
>>
>> +ARM guys
>>
>> Which ARM64 SoC did you test this with?
>>
>> The round down in this patch should be unnecessary. But it's better to
>> figure out which call to dcache_xxx() with an unaligned end address.
> 
> I agree. There is no requirement for the actual cache maintenance
> instruction's address to be aligned, and also we align everything
> already in the implementations of flush_dcache_range() and
> invalidate_dcache_range().

I would suggest you insert check_cache_range() into 
arch/arm/cpu/armv8/cache_v8.c invalidate_dcache_range() and 
flush_dcache_range() which would prove you wrong.

> Actually I think rounding here is *wrong*, as we paper over the
> requirement of the *buffer* to be cache line aligned. So this must be
> assured at buffer allocation time, and just rounding before calling
> cache maintenance merely avoids (read: silences!) the warnings.
> 
> I think drivers/net/bcmgenet.c does the right thing.
> 
> Happy to provide more detailed rationale and explanations if needed.

Please do spend some more time on this, possibly even test your claim on 
real hardware, and then provide more details.