[PATCH v3 4/4] board/km: add support for seli8 design based on nxp ls102x
Aleksandar Gerasimovski
aleksandar.gerasimovski at hitachi-powergrids.com
Thu Feb 4 16:28:59 CET 2021
The SELI8 design is a new tdm service unit card for Hitachi-Powergrids
XMC and FOX product lines.
It is based on NXP LS1021 SoC and it provides following interfaces:
- IFC interface for NOR, NAND and external FPGA's
- 1 x RGMII ETH for debug purposes
- 2 x SGMII ETH for management communication via back-plane
- 1 x uQE HDLC for management communication via back-plane
- 1 x I2C for peripheral devices
- 1 x SPI for peripheral devices
- 1 x UART for debug logging
It is foreseen that the design will be later re-used for another XMC and
FOX service cards with similar SoC requirements.
Signed-off-by: Rainer Boschung <rainer.boschung at hitachi-powergrids.com>
Signed-off-by: Matteo Ghidoni <matteo.ghidoni at hitachi-powergrids.com>
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski at hitachi-powergrids.com>
---
Changes for v2:
- fix patch subject to 60 characters
Changes for v3:
- remove obsolete CMDLINE_TAG
---
arch/arm/Kconfig | 19 ++
arch/arm/dts/Makefile | 2 +
arch/arm/dts/ls1021a-pg-wcom-seli8.dts | 111 +++++++++
board/keymile/Kconfig | 23 +-
board/keymile/common/ivm.c | 19 +-
board/keymile/pg-wcom-ls102xa/Kconfig | 19 ++
board/keymile/pg-wcom-ls102xa/MAINTAINERS | 10 +
board/keymile/pg-wcom-ls102xa/Makefile | 11 +
board/keymile/pg-wcom-ls102xa/ddr.c | 90 +++++++
board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 160 ++++++++++++
configs/pg_wcom_seli8_defconfig | 63 +++++
include/configs/km/pg-wcom-ls102xa.h | 307 ++++++++++++++++++++++++
include/configs/pg-wcom-seli8.h | 45 ++++
13 files changed, 868 insertions(+), 11 deletions(-)
create mode 100644 arch/arm/dts/ls1021a-pg-wcom-seli8.dts
create mode 100644 board/keymile/pg-wcom-ls102xa/Kconfig
create mode 100644 board/keymile/pg-wcom-ls102xa/MAINTAINERS
create mode 100644 board/keymile/pg-wcom-ls102xa/Makefile
create mode 100644 board/keymile/pg-wcom-ls102xa/ddr.c
create mode 100644 board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
create mode 100644 configs/pg_wcom_seli8_defconfig
create mode 100644 include/configs/km/pg-wcom-ls102xa.h
create mode 100644 include/configs/pg-wcom-seli8.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fbe9087..13fdf3c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1515,6 +1515,24 @@ config TARGET_LS1021ATWR
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
imply SCSI
+config TARGET_PG_WCOM_SELI8
+ bool "Support Hitachi-Powergrids SELI8 service unit card"
+ select ARCH_LS1021A
+ select ARCH_SUPPORT_PSCI
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select CPU_V7A
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select SYS_FSL_DDR
+ select FSL_DDR_INTERACTIVE
+ select VENDOR_KM
+ imply SCSI
+ help
+ Support for Hitachi-Powergrids SELI8 service unit card.
+ SELI8 is a QorIQ LS1021a based service unit card used
+ in XMC20 and FOX615 product families.
+
config TARGET_LS1021ATSN
bool "Support ls1021atsn"
select ARCH_LS1021A
@@ -2034,6 +2052,7 @@ source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/phytium/durian/Kconfig"
source "board/xen/xenguest_arm64/Kconfig"
+source "board/keymile/Kconfig"
source "arch/arm/Kconfig.debug"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fd47e40..ec93f93 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -393,6 +393,8 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-qds-lpuart.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
ls1021a-iot-duart.dtb ls1021a-tsn.dtb
+dtb-$(CONFIG_TARGET_PG_WCOM_SELI8) += ls1021a-pg-wcom-seli8.dtb
+
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-qds-42-x.dtb \
fsl-ls2080a-rdb.dtb \
diff --git a/arch/arm/dts/ls1021a-pg-wcom-seli8.dts b/arch/arm/dts/ls1021a-pg-wcom-seli8.dts
new file mode 100644
index 0000000..e335188
--- /dev/null
+++ b/arch/arm/dts/ls1021a-pg-wcom-seli8.dts
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright 2020 Hitachi Power Grids. All rights reserved.
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+ model = "Hitachi-Powergrids SELI8 Service Unit for XMC and FOX";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&enet0 {
+ status = "okay";
+ tbi-handle = <&tbi0>;
+ phy-connection-type = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&enet1 {
+ status = "okay";
+ tbi-handle = <&tbi1>;
+ phy-connection-type = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&enet2 {
+ phy-handle = <&debug_phy>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR Flash on board */
+ ranges = <0x0 0x0 0x60000000 0x04000000>;
+ status = "okay";
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x4000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition at 0 {
+ label = "rcw";
+ reg = <0x0 0x20000>;
+ read-only;
+ };
+ partition at 20000 {
+ label = "qe";
+ reg = <0x20000 0x20000>;
+ };
+ partition at 40000 {
+ label = "envred";
+ reg = <0x40000 0x20000>;
+ };
+ partition at 60000 {
+ label = "env";
+ reg = <0x60000 0x20000>;
+ };
+ partition at 100000 {
+ label = "u-boot";
+ reg = <0x100000 0x100000>;
+ };
+ partition at 200000 {
+ label = "ubi0";
+ reg = <0x200000 0x3E00000>;
+ };
+ };
+};
+
+&mdio0 {
+ debug_phy: ethernet-phy at 11 {
+ reg = <0x11>;
+ };
+
+ tbi0: tbi-phy at 0xb {
+ reg = <0xb>;
+ device_type = "tbi-phy";
+ };
+};
+
+&mdio1 {
+ tbi1: tbi-phy at 0xd {
+ reg = <0xd>;
+ device_type = "tbi-phy";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
index e590690..965a537 100644
--- a/board/keymile/Kconfig
+++ b/board/keymile/Kconfig
@@ -20,8 +20,8 @@ config KM_PNVRAM
config KM_PHRAM
hex "Physical RAM"
- default 0x17F000 if ARM
- default 0x100000 if PPC
+ default 0x17F000 if ARM && !ARCH_LS1021A
+ default 0x100000 if PPC || ARCH_LS1021A
depends on !ARCH_SOCFPGA
help
Start address of the physical RAM, which is the mounted /var folder.
@@ -30,13 +30,14 @@ config KM_RESERVED_PRAM
hex "Reserved RAM"
default 0x801000 if ARCH_KIRKWOOD
default 0x0 if MPC83xx
- default 0x1000 if MPC85xx
+ default 0x1000 if MPC85xx || ARCH_LS1021A
depends on !ARCH_SOCFPGA
help
Reserved physical RAM area at the end of memory for special purposes.
config KM_CRAMFS_ADDR
hex "CRAMFS Address"
+ default 0x83000000 if ARCH_LS1021A
default 0x3000000
depends on !ARCH_SOCFPGA
help
@@ -44,16 +45,25 @@ config KM_CRAMFS_ADDR
config KM_KERNEL_ADDR
hex "Kernel Load Address"
+ default 0x82000000 if ARCH_LS1021A
default 0x2000000
help
Address where to load Linux kernel in RAM.
config KM_FDT_ADDR
hex "FDT Load Address"
+ default 0x82FC0000 if ARCH_LS1021A
default 0x2FC0000
help
Address where to load flattened device tree in RAM.
+config SYS_PAX_BASE
+ hex "PAX IFC Base Address"
+ default 0x78000000
+ depends on ARCH_LS1021A
+ help
+ IFC Base Address for PAXx FPGA.
+
config KM_CONSOLE_TTY
string "KM Console"
default "ttyS0"
@@ -69,9 +79,9 @@ config KM_DEF_NETDEV
config KM_COMMON_ETH_INIT
bool "Common Ethernet Initialization"
default y if ARCH_KIRKWOOD || MPC83xx
- default n if MPC85xx || ARCH_SOCFPGA
+ default n if MPC85xx || ARCH_SOCFPGA || ARCH_LS1021A
help
- Use the Ethernet initialization implemented in common code, which
+ Use the Ethernet initialization implemented in common code that
detects if a Piggy board is present.
config PIGGY_MAC_ADDRESS_OFFSET
@@ -90,7 +100,7 @@ config KM_MVEXTSW_ADDR
config KM_IVM_BUS
int "IVM I2C Bus"
default 0 if ARCH_SOCFPGA
- default 1 if ARCH_KIRKWOOD || MPC85xx
+ default 1 if ARCH_KIRKWOOD || MPC85xx || ARCH_LS1021A
default 2 if MPC83xx
help
Identifier number of I2C bus, where the inventory EEPROM is connected to.
@@ -116,6 +126,7 @@ config SYS_IVM_EEPROM_PAGE_LEN
source "board/keymile/km83xx/Kconfig"
source "board/keymile/kmp204x/Kconfig"
source "board/keymile/km_arm/Kconfig"
+source "board/keymile/pg-wcom-ls102xa/Kconfig"
endmenu
diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c
index e989bf6..48817cb 100644
--- a/board/keymile/common/ivm.c
+++ b/board/keymile/common/ivm.c
@@ -306,11 +306,7 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset)
return 0;
page2 = &buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2];
- if (!IS_ENABLED(CONFIG_KMTEGR1)) {
- /* if an offset is defined, add it */
- process_mac(valbuf, page2, mac_address_offset, true);
- env_set((char *)"ethaddr", (char *)valbuf);
- } else {
+ if (IS_ENABLED(CONFIG_KMTEGR1)) {
/* KMTEGR1 has a special setup. eth0 has no connection to the
* outside and gets an locally administred MAC address, eth1 is
* the debug interface and gets the official MAC address from
@@ -320,6 +316,19 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset)
env_set((char *)"ethaddr", (char *)valbuf);
process_mac(valbuf, page2, mac_address_offset, true);
env_set((char *)"eth1addr", (char *)valbuf);
+ } else if (IS_ENABLED(CONFIG_ARCH_LS1021A)) {
+ /* LS102xA has 1xRGMII for debug connection and
+ * 2xSGMII for back-plane mgmt connection
+ */
+ process_mac(valbuf, page2, 1, true);
+ env_set((char *)"ethaddr", (char *)valbuf);
+ process_mac(valbuf, page2, 2, true);
+ env_set((char *)"eth1addr", (char *)valbuf);
+ process_mac(valbuf, page2, mac_address_offset, true);
+ env_set((char *)"eth2addr", (char *)valbuf);
+ } else {
+ process_mac(valbuf, page2, mac_address_offset, true);
+ env_set((char *)"ethaddr", (char *)valbuf);
}
return 0;
diff --git a/board/keymile/pg-wcom-ls102xa/Kconfig b/board/keymile/pg-wcom-ls102xa/Kconfig
new file mode 100644
index 0000000..15c009d
--- /dev/null
+++ b/board/keymile/pg-wcom-ls102xa/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_PG_WCOM_SELI8
+
+config SYS_BOARD
+ default "pg-wcom-ls102xa"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_SOC
+ default "ls102xa"
+
+config SYS_CONFIG_NAME
+ default "pg-wcom-seli8"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ imply FS_CRAMFS
+
+endif
diff --git a/board/keymile/pg-wcom-ls102xa/MAINTAINERS b/board/keymile/pg-wcom-ls102xa/MAINTAINERS
new file mode 100644
index 0000000..e1bc90a
--- /dev/null
+++ b/board/keymile/pg-wcom-ls102xa/MAINTAINERS
@@ -0,0 +1,10 @@
+Hitachi Power Grids LS102XA BOARD
+M: Aleksandar Gerasimovski <aleksandar.gerasimovski at hitachi-powergrids.com>
+M: Rainer Boschung <rainer.boschung at hitachi-powergrids.com>
+M: Matteo Ghidoni <matteo.ghidoni at hitachi-powergrids.com>
+S: Maintained
+F: board/keymile/pg-wcom-ls102xa/
+F: include/configs/km/pg-wcom-ls102xa.h
+F: include/configs/pg-wcom-seli8.h
+F: configs/pg_wcom_seli8_defconfig
+F: arch/arm/dts/ls1021a-pg-wcom-seli8.dts
diff --git a/board/keymile/pg-wcom-ls102xa/Makefile b/board/keymile/pg-wcom-ls102xa/Makefile
new file mode 100644
index 0000000..229b0c2
--- /dev/null
+++ b/board/keymile/pg-wcom-ls102xa/Makefile
@@ -0,0 +1,11 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2021 Hitachi Power Grids. All rights reserved.
+#
+
+obj-y += pg-wcom-ls102xa.o ddr.o
+obj-y += ../common/common.o ../common/ivm.o ../common/qrio.o
+obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ../../freescale/common/ns_access.o
+obj-$(CONFIG_LS102XA_STREAM_ID) += ../../freescale/common/ls102xa_stream_id.o
+obj-$(CONFIG_ID_EEPROM) += ../../freescale/common/sys_eeprom.o
diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c
new file mode 100644
index 0000000..6023573
--- /dev/null
+++ b/board/keymile/pg-wcom-ls102xa/ddr.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 Hitachi Power Grids. All rights reserved.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ls102xa_soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+
+ // 1/2 DRAM cycle (should be increased in case of ADDR/CMD heavily loaded than the clock)
+ popts->clk_adjust = 0x4;
+ popts->write_data_delay = 0x4;
+ // wr leveling start value for lane 0
+ popts->wrlvl_start = 0x5;
+ // wr leveling start values for lanes 1-3 (lane 4 not there)
+ popts->wrlvl_ctl_2 = 0x05050500;
+ // 32-bit DRAM, no need to set start values for lanes we do not have (5-8)
+ popts->wrlvl_ctl_3 = 0x0;
+ popts->cpo_override = 0x1f;
+
+ /* force DDR bus width to 32 bits */
+ popts->data_bus_width = 1;
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ popts->cswl_override = DDR_CSWL_CS0;
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x58;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+int fsl_initdram(void)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing DDR....using SPD\n");
+ dram_size = fsl_ddr_sdram();
+
+ erratum_a008850_post();
+
+ gd->ram_size = dram_size;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
new file mode 100644
index 0000000..6b0e963
--- /dev/null
+++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Hitachi Power Grids. All rights reserved.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_soc.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include <fsl_immap.h>
+#include <netdev.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <fsl_sec.h>
+#include <fsl_devdis.h>
+#include <fsl_ddr.h>
+#include <spl.h>
+#include <fdt_support.h>
+#include <fsl_qe.h>
+#include <fsl_validate.h>
+
+#include "../common/common.h"
+#include "../common/qrio.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
+int checkboard(void)
+{
+ show_qrio();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return fsl_initdram();
+}
+
+int board_early_init_f(void)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+
+ /* Disable unused MCK1 */
+ setbits_be32(&gur->ddrclkdr, 2);
+
+ /* IFC Global Configuration */
+ setbits_be32(&ifc.gregs->ifc_gcr, 12 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+ setbits_be32(&ifc.gregs->ifc_ccr, IFC_CCR_CLK_DIV(3) |
+ IFC_CCR_INV_CLK_EN);
+
+ /* clear BD & FR bits for BE BD's and frame data */
+ clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+
+ init_early_memctl_regs();
+
+ /* QRIO Configuration */
+ qrio_uprstreq(UPREQ_CORE_RST);
+
+ if (IS_ENABLED(CONFIG_TARGET_PG_WCOM_SELI8)) {
+ qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_LIU_RST, true);
+
+ qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_PAXK_RST, true);
+
+ qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prst(KM_DBG_ETH_RST, false, false);
+ }
+
+ i2c_deblock_gpio_cfg();
+
+ arch_soc_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010315))
+ erratum_a010315();
+
+ fsl_serdes_init();
+
+ ls102xa_smmu_stream_id_init();
+
+ u_qe_init();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ if (IS_ENABLED(CONFIG_FSL_DEVICE_DISABLE))
+ device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+
+ ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+ CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ if (IS_ENABLED(CONFIG_PCI))
+ ft_pci_setup(blob, bd);
+
+ return 0;
+}
+
+u8 flash_read8(void *addr)
+{
+ return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+ u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+ __raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+ u16 val = __raw_readw(addr);
+
+ return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
+
+int hush_init_var(void)
+{
+ ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ set_km_env();
+ return 0;
+}
diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig
new file mode 100644
index 0000000..2d58fa0
--- /dev/null
+++ b/configs/pg_wcom_seli8_defconfig
@@ -0,0 +1,63 @@
+CONFIG_ARM=y
+CONFIG_TARGET_PG_WCOM_SELI8=y
+CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_KM_DEF_NETDEV="eth2"
+CONFIG_KM_COMMON_ETH_INIT=y
+CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x9fffffff
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8"
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
+CONFIG_SILENT_CONSOLE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_CRAMFS=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),-(ubi0);68000000.flash:-(ubi1)"
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_ADDR=0x60060000
+CONFIG_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_FSL_DDR3=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_TSEC_ENET=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h
new file mode 100644
index 0000000..40df27d
--- /dev/null
+++ b/include/configs/km/pg-wcom-ls102xa.h
@@ -0,0 +1,307 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Hitachi Power Grids. All rights reserved.
+ */
+
+#ifndef __CONFIG_PG_WCOM_LS102XA_H
+#define __CONFIG_PG_WCOM_LS102XA_H
+
+#define CONFIG_SYS_FSL_CLK
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+/*
+ * Take into account default implementation where DDR_FDBK_MULTI is consider as
+ * configured for DDR_PLL = 2*MEM_PLL_RAT.
+ * In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT.
+ */
+#define CONFIG_DDR_CLK_FREQ (100000000 >> 1)
+
+#define PHYS_SDRAM 0x80000000
+#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x54
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash Definitions */
+#define CONFIG_FSL_IFC
+#define CONFIG_SYS_FLASH_BASE 0x60000000
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_TE | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024)
+
+#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \
+ CSOR_NOR_ADM_SHIFT(0x4) | \
+ CSOR_NOR_NOR_MODE_AYSNC_NOR | \
+ CSOR_NOR_TRHZ_20 | \
+ CSOR_NOR_BCTLD)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
+ FTIM0_NOR_TEADC(0x7) | \
+ FTIM0_NOR_TAVDS(0x0) | \
+ FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
+ FTIM1_NOR_TRAD_NOR(0x21) | \
+ FTIM1_NOR_TSEQRAD_NOR(0x21))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
+ FTIM2_NOR_TCH(0x1) | \
+ FTIM2_NOR_TWPH(0x6) | \
+ FTIM2_NOR_TWP(0xb))
+#define CONFIG_SYS_NOR_FTIM3 0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+/* NAND Flash Definitions */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0x68000000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+ CSPR_PORT_SIZE_8 | \
+ CSPR_TE | \
+ CSPR_MSEL_NAND | \
+ CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
+ | CSOR_NAND_ECC_DEC_EN \
+ | CSOR_NAND_ECC_MODE_4 \
+ | CSOR_NAND_RAL_3 \
+ | CSOR_NAND_PGS_2K \
+ | CSOR_NAND_SPRZ_64 \
+ | CSOR_NAND_PB(64) \
+ | CSOR_NAND_TRHZ_40 \
+ | CSOR_NAND_BCTLD)
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
+ FTIM0_NAND_TWP(0x8) | \
+ FTIM0_NAND_TWCHT(0x3) | \
+ FTIM0_NAND_TWH(0x5))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
+ FTIM1_NAND_TWBE(0x1e) | \
+ FTIM1_NAND_TRR(0x6) | \
+ FTIM1_NAND_TRP(0x8))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
+ FTIM2_NAND_TREH(0x5) | \
+ FTIM2_NAND_TWHRE(0x3c))
+#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
+
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+/* QRIO FPGA Definitions */
+#define CONFIG_SYS_QRIO_BASE 0x70000000
+#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE
+
+#define CONFIG_SYS_CSPR2_EXT (0x00)
+#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+ CSPR_PORT_SIZE_8 | \
+ CSPR_TE | \
+ CSPR_MSEL_GPCM | \
+ CSPR_V)
+#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
+ CSOR_GPCM_TRHZ_20 | \
+ CSOR_GPCM_BCTLD)
+#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x6))
+#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x7))
+#define CONFIG_SYS_CS2_FTIM3 0x04000000
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_NUM_I2C_BUSES 3
+#define I2C_MUX_PCA_ADDR 0x70
+#define I2C_MUX_CH_DEFAULT 0x0
+#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
+ {1, {I2C_NULL_HOP} }, \
+ }
+
+#ifndef __ASSEMBLY__
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+#endif
+
+/*
+ * eTSEC
+ */
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_ETHPRIME "ethernet at 2d90000"
+#endif
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+#define CONFIG_SMP_PEN_ADDR 0x01ee0200
+#define COUNTER_FREQUENCY 12500000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 256
+#define CONFIG_FSL_DEVICE_DISABLE
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LOAD_ADDR 0x82000000
+
+#define CONFIG_LS102XA_STREAM_ID
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */
+#define CONFIG_SYS_QE_FW_ADDR 0x60020000
+
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/*
+ * Environment
+ */
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_ENV_TOTAL_SIZE 0x40000
+#define ENV_DEL_ADDR 0x60040000 /* direct for newenv */
+
+#define CONFIG_ENV_OVERWRITE
+#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV
+#endif
+
+#ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
+#endif
+
+#define CONFIG_KM_DEF_ENV_CPU \
+ "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
+ "cramfsloadfdt=" \
+ "cramfsload ${fdt_addr_r} " \
+ "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize} && " \
+ "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize} && " \
+ "cp.b ${load_addr_r} " \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
+ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize}\0" \
+ "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " +${filesize} && " \
+ "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " +${filesize} && " \
+ "cp.b ${load_addr_r} " \
+ __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
+ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \
+ "set_fdthigh=true\0" \
+ "checkfdt=true\0" \
+ ""
+
+#define CONFIG_KM_NEW_ENV \
+ "newenv=protect off " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
+ "erase " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
+ "protect on " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_NEW_ENV \
+ CONFIG_KM_DEF_ENV \
+ "EEprom_ivm=pca9547:70:9\0" \
+ ""
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
+
+#endif
diff --git a/include/configs/pg-wcom-seli8.h b/include/configs/pg-wcom-seli8.h
new file mode 100644
index 0000000..9a7669c
--- /dev/null
+++ b/include/configs/pg-wcom-seli8.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Hitachi Power Grids. All rights reserved.
+ */
+
+#ifndef __CONFIG_PG_WCOM_SELI8_H
+#define __CONFIG_PG_WCOM_SELI8_H
+
+#define CONFIG_HOSTNAME "SELI8"
+
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
+#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
+
+/* PAXK FPGA Definitions */
+#define CONFIG_SYS_CSPR3_EXT (0x00)
+#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \
+ CSPR_PORT_SIZE_8 | \
+ CSPR_MSEL_GPCM | \
+ CSPR_V)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
+ CSOR_GPCM_TRHZ_40)
+#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+ FTIM0_GPCM_TEADC(0x7) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x12))
+#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x12))
+#define CONFIG_SYS_CS3_FTIM3 0x04000000
+
+/* PRST */
+#define KM_LIU_RST 0
+#define KM_PAXK_RST 1
+#define KM_DBG_ETH_RST 15
+
+/* QRIO GPIOs used for deblocking */
+#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
+#define KM_I2C_DEBLOCK_SCL 20
+#define KM_I2C_DEBLOCK_SDA 21
+
+#include "km/pg-wcom-ls102xa.h"
+
+#endif /* __CONFIG_PG_WCOM_SELI8_H */
--
1.8.3.1
-----Original Message-----
From: Tom Rini <trini at konsulko.com>
Sent: Donnerstag, 4. Februar 2021 14:22
To: Aleksandar Gerasimovski <aleksandar.gerasimovski at hitachi-powergrids.com>
Cc: Priyanka Jain <priyanka.jain at nxp.com>; Priyanka Jain (OSS) <priyanka.jain at oss.nxp.com>; u-boot at lists.denx.de; Valentin Longchamp <valentin.longchamp at hitachi-powergrids.com>; Holger Brunck <holger.brunck at hitachi-powergrids.com>; Rainer Boschung <rainer.boschung at hitachi-powergrids.com>; Matteo Ghidoni <matteo.ghidoni at hitachi-powergrids.com>
Subject: Re: Subject:[PATCH v2 4/4] board/km: add support for seli8 design based on nxp ls102x
On Thu, Feb 04, 2021 at 09:49:58AM +0000, Aleksandar Gerasimovski wrote:
>
> -----Original Message-----
> From: Tom Rini <trini at konsulko.com>
> Sent: Mittwoch, 3. Februar 2021 15:36
> To: Aleksandar Gerasimovski
> <aleksandar.gerasimovski at hitachi-powergrids.com>
> Cc: Priyanka Jain <priyanka.jain at nxp.com>; Priyanka Jain (OSS)
> <priyanka.jain at oss.nxp.com>; u-boot at lists.denx.de; Valentin Longchamp
> <valentin.longchamp at hitachi-powergrids.com>; Holger Brunck
> <holger.brunck at hitachi-powergrids.com>; Rainer Boschung
> <rainer.boschung at hitachi-powergrids.com>; Matteo Ghidoni
> <matteo.ghidoni at hitachi-powergrids.com>
> Subject: Re: Subject:[PATCH v2 4/4] board/km: add support for seli8
> design based on nxp ls102x
>
> On Wed, Feb 03, 2021 at 02:28:01PM +0000, Aleksandar Gerasimovski wrote:
> > -----Original Message-----
> > From: Tom Rini <trini at konsulko.com>
> > Sent: Mittwoch, 3. Februar 2021 15:08
> > To: Priyanka Jain <priyanka.jain at nxp.com>
> > Cc: Aleksandar Gerasimovski
> > <aleksandar.gerasimovski at hitachi-powergrids.com>; Priyanka Jain
> > (OSS) <priyanka.jain at oss.nxp.com>; u-boot at lists.denx.de; Valentin
> > Longchamp <valentin.longchamp at hitachi-powergrids.com>; Holger Brunck
> > <holger.brunck at hitachi-powergrids.com>; Rainer Boschung
> > <rainer.boschung at hitachi-powergrids.com>; Matteo Ghidoni
> > <matteo.ghidoni at hitachi-powergrids.com>
> > Subject: Re: Subject:[PATCH v2 4/4] board/km: add support for seli8
> > design based on nxp ls102x
> >
> > On Wed, Feb 03, 2021 at 08:15:49AM +0000, Priyanka Jain wrote:
> > >
> > >
> > > >-----Original Message-----
> > > >From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of
> > > >Aleksandar Gerasimovski
> > > >Sent: Tuesday, February 2, 2021 2:37 PM
> > > >To: Priyanka Jain (OSS) <priyanka.jain at oss.nxp.com>;
> > > >u-boot at lists.denx.de
> > > >Cc: Valentin Longchamp
> > > ><valentin.longchamp at hitachi-powergrids.com>;
> > > >Holger Brunck <holger.brunck at hitachi-powergrids.com>; Rainer
> > > >Boschung <rainer.boschung at hitachi-powergrids.com>; Matteo Ghidoni
> > > ><matteo.ghidoni at hitachi-powergrids.com>
> > > >Subject: RE: Subject:[PATCH v2 4/4] board/km: add support for
> > > >seli8 design based on nxp ls102x
> > > >
> > > >
> > > >-----Original Message-----
> > > >From: Priyanka Jain (OSS) <priyanka.jain at oss.nxp.com>
> > > >Sent: Dienstag, 2. Februar 2021 07:33
> > > >To: Aleksandar Gerasimovski <aleksandar.gerasimovski at hitachi-
> > > >powergrids.com>; Priyanka Jain (OSS) <priyanka.jain at oss.nxp.com>;
> > > >u- boot at lists.denx.de
> > > >Cc: Valentin Longchamp
> > > ><valentin.longchamp at hitachi-powergrids.com>;
> > > >Holger Brunck <holger.brunck at hitachi-powergrids.com>; Rainer
> > > >Boschung <rainer.boschung at hitachi-powergrids.com>; Matteo Ghidoni
> > > ><matteo.ghidoni at hitachi-powergrids.com>
> > > >Subject: RE: Subject: [PATCH v2 4/4] board/km: add support for
> > > >seli8 design based on nxp ls102x
> > > >
> > > >CAUTION: This email originated from outside of the organization.
> > > >Do not click links or open attachments unless you recognize the
> > > >sender and know the content is safe.
> > > >
> > > >
> > > >>-----Original Message-----
> > > >>From: Aleksandar Gerasimovski <aleksandar.gerasimovski at hitachi-
> > > >>powergrids.com>
> > > >>Sent: Tuesday, January 19, 2021 4:11 PM
> > > >>To: Priyanka Jain (OSS) <priyanka.jain at oss.nxp.com>;
> > > >>u-boot at lists.denx.de
> > > >>Cc: Valentin Longchamp
> > > >><valentin.longchamp at hitachi-powergrids.com>;
> > > >>Holger Brunck <holger.brunck at hitachi-powergrids.com>; Rainer
> > > >>Boschung <rainer.boschung at hitachi-powergrids.com>; Matteo
> > > >>Ghidoni <matteo.ghidoni at hitachi-powergrids.com>
> > > >>Subject: Subject: [PATCH v2 4/4] board/km: add support for seli8
> > > >>design based on nxp ls102x
> > > >>
> > > >>The SELI8 design is a new tdm service unit card for
> > > >>Hitachi-Powergrids XMC and FOX product lines.
> > > >>
> > > >>It is based on NXP LS1021 SoC and it provides following interfaces:
> > > >> - IFC interface for NOR, NAND and external FPGA's
> > > >> - 1 x RGMII ETH for debug purposes
> > > >> - 2 x SGMII ETH for management communication via back-plane
> > > >> - 1 x uQE HDLC for management communication via back-plane
> > > >> - 1 x I2C for peripheral devices
> > > >> - 1 x SPI for peripheral devices
> > > >> - 1 x UART for debug logging
> > > >>
> > > >>It is foreseen that the design will be later re-used for another
> > > >>XMC and FOX service cards with similar SoC requirements.
> > > >>
> > > >>Signed-off-by: Rainer Boschung
> > > >><rainer.boschung at hitachi-powergrids.com>
> > > >>Signed-off-by: Matteo Ghidoni
> > > >><matteo.ghidoni at hitachi-powergrids.com>
> > > >>Signed-off-by: Aleksandar Gerasimovski
> > > >><aleksandar.gerasimovski at hitachi- powergrids.com>
> > > >>---
> > > ><snip>
> > > >Kindly fix below checkpatch errors /warnings
> > > >WARNING: 'AYSNC' may be misspelled - perhaps 'ASYNC'?
> > > >#799: FILE: include/configs/km/pg-wcom-ls102xa.h:64:
> > > >+
> > > >+ CSOR_NOR_NOR_MODE_AYSNC_NOR
> > > >+ | \
> > > >
> > > >ERROR: All commands are managed by Kconfig
> > > >#953: FILE: include/configs/km/pg-wcom-ls102xa.h:218:
> > > >+#define CONFIG_CMDLINE_TAG
> > > >
> > > >total: 1 errors, 2 warnings, 0 checks, 964 lines checked
> > > >
> > > >Regards
> > > >Priyanka
> > > >
> > > >Hi Priyanka,
> > > >
> > > >CSOR_NOR_NOR_MODE_AYSNC_NOR is named like in mainline (nxp) see
> > > >include/fsl_ifc.h If you asking me to change that than it belongs
> > > >to a separate patch, not this topic.
> > > >
> > > OK this warning can be ignored
> > >
> > > >CONFIG_CMDLINE_TAG is a whitelisted on mainline, there is no Kconfig for that.
> > > >
> > >
> > > Tom,
> > >
> > > How to handle this checkpatch error?
> > > CONFIG_CMDLINE_TAG is a whitelisted in mainline, but checkpatch is throwing error.
> > > Can I go ahead and accept this patch ?
> >
> > There's two parts to it. One part, checkpatch regex is wrong and shouldn't trigger on that, since it's not an actual command. Second part, uh, does passing ATAGs make sense on that platform? Is there some unfortunate and needing to be fixed logic in U-Boot that requires CMDLINE_TAG (and the few others) to be enabled for device tree to be passed or something?
> >
> > --
> > Tom
> >
> > Hi Tom,
> >
> > To answer to the second part of CMDLINE_TAG doubt, in our design (proposed patch) this is inherited from the NXP reference design that is Layerscape ls1021atwr and if I grep the u-boot I see this set for all layerscape reference boards, I'm not sure if this must to be set but we are trying to stay close to mainline for our designs.
> >
> > Priyanka, CMDLINE_TAG is already set for all layerscape reference designs so I see no strong reason to be different in our platform.
>
> This got me to grep around and yes, there's some unused code here. None of the CONFIG_xxx_TAG stuff is used on aarch64 and these SoCs never ever supported a kernel that used ATAGs and not device tree. So update your platform to drop all of this dead code would be best.
>
> --
> Tom
>
> Hi Priyanka,
>
> What do you think, can be remove CMDLINE_TAG from our design without consequences? Let's say our design is similar as ls1021atwr (arm32 bit)?
> Tom mentioned that that's dead code for aarch64, but I grep around as well and I see they are still in use for arm32?
> I can remove this but don't want to enter in a trap now or in future and layerscape kernel is expecting this.
It's been dead code for arm32 for over a decade at this point as well, please keep in mind.
--
Tom
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