[PATCH u-boot-marvell 01/18] ddr: marvell: a38x: fix write leveling suplementary algo

[Marek Behún]

commit ce62bef8fac559e27245259882e45f19cdc293ad upstream.

- fix JIRA A7K8K-5056
- remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage
- the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory
  then the algorithm will fail, since it think that there are no phase to correct

Signed-off-by: motib <motib at marvell.com>
Reviewed-by: Kostya Porotchkin <kostap at marvell.com>
Signed-off-by: Marek Behún <marek.behun at nic.cz>
---
 drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
index 979f3530b7..5fd9a052fa 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
@@ -864,8 +864,11 @@ int ddr3_tip_load_all_pattern_to_mem(u32 dev_num)
 			      DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3)));
 	}
 
-	for (pattern = 0; pattern < PATTERN_LAST; pattern++)
+	for (pattern = 0; pattern < PATTERN_LAST; pattern++) {
+		if (pattern == PATTERN_TEST)
+			continue;
 		ddr3_tip_load_pattern_to_mem(dev_num, pattern);
+	}
 
 	return MV_OK;
 }
-- 
2.26.2