[PATCH 50/57] ppc: Remove MPC837XERDB board
Tom Rini
trini at konsulko.com
Sun Feb 21 02:06:27 CET 2021
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Sinan Akman <sinan at writeme.com>
Signed-off-by: Tom Rini <trini at konsulko.com>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 6 -
board/freescale/mpc837xerdb/Kconfig | 12 -
board/freescale/mpc837xerdb/MAINTAINERS | 7 -
board/freescale/mpc837xerdb/Makefile | 7 -
board/freescale/mpc837xerdb/README | 97 -----
board/freescale/mpc837xerdb/mpc837xerdb.c | 226 ------------
board/freescale/mpc837xerdb/pci.c | 109 ------
configs/MPC837XERDB_SLAVE_defconfig | 142 --------
configs/MPC837XERDB_defconfig | 186 ----------
include/configs/MPC837XERDB.h | 412 ----------------------
10 files changed, 1204 deletions(-)
delete mode 100644 board/freescale/mpc837xerdb/Kconfig
delete mode 100644 board/freescale/mpc837xerdb/MAINTAINERS
delete mode 100644 board/freescale/mpc837xerdb/Makefile
delete mode 100644 board/freescale/mpc837xerdb/README
delete mode 100644 board/freescale/mpc837xerdb/mpc837xerdb.c
delete mode 100644 board/freescale/mpc837xerdb/pci.c
delete mode 100644 configs/MPC837XERDB_SLAVE_defconfig
delete mode 100644 configs/MPC837XERDB_defconfig
delete mode 100644 include/configs/MPC837XERDB.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index d2c620e22954..b13a555413ec 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -82,11 +82,6 @@ config TARGET_MPC837XEMDS
imply CMD_SATA
imply FSL_SATA
-config TARGET_MPC837XERDB
- bool "Support MPC837XERDB"
- select ARCH_MPC837X
- select BOARD_EARLY_INIT_F
-
config TARGET_IDS8313
bool "Support ids8313"
select ARCH_MPC8313
@@ -322,7 +317,6 @@ source "board/freescale/mpc832xemds/Kconfig"
source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc8349itx/Kconfig"
source "board/freescale/mpc837xemds/Kconfig"
-source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
source "board/keymile/Kconfig"
source "board/mpc8308_p1m/Kconfig"
diff --git a/board/freescale/mpc837xerdb/Kconfig b/board/freescale/mpc837xerdb/Kconfig
deleted file mode 100644
index 03415f9fc941..000000000000
--- a/board/freescale/mpc837xerdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC837XERDB
-
-config SYS_BOARD
- default "mpc837xerdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC837XERDB"
-
-endif
diff --git a/board/freescale/mpc837xerdb/MAINTAINERS b/board/freescale/mpc837xerdb/MAINTAINERS
deleted file mode 100644
index 9f44a37a0d94..000000000000
--- a/board/freescale/mpc837xerdb/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC837XERDB BOARD
-M: Sinan Akman <sinan at writeme.com>
-S: Maintained
-F: board/freescale/mpc837xerdb/
-F: include/configs/MPC837XERDB.h
-F: configs/MPC837XERDB_defconfig
-F: configs/MPC837XERDB_SLAVE_defconfig
diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile
deleted file mode 100644
index c683b017b559..000000000000
--- a/board/freescale/mpc837xerdb/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y += mpc837xerdb.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc837xerdb/README b/board/freescale/mpc837xerdb/README
deleted file mode 100644
index 12df2f2e756d..000000000000
--- a/board/freescale/mpc837xerdb/README
+++ /dev/null
@@ -1,97 +0,0 @@
-Freescale MPC837xE-RDB Board
------------------------------------------
-
-1. Board Description
-
- The MPC837xE-RDB are reference boards featuring the Freescale MPC8377E,
- MPC8378E, and the MPC8379E processors in a Mini-ITX form factor.
-
- The MPC837xE-RDB's have the following common features:
-
- A) 256-MBytes on-board DDR2 unbuffered SDRAM
- B) 8-Mbytes NOR Flash
- C) 32-MBytes NAND Flash
- D) 1 Secure Digital High Speed Card (SDHC) Interface
- E) 1 Gigabit Ethernet
- F) 5-port Ethernet switch (Vitesse 7385)
- G) 1 32-bit, 3.3 V, PCI slot
- H) 1 32-bit, 3.3 V, Mini-PCI slot
- I) 4-port USB 2.0 Hub
- J) 1-port OTG USB
- K) 2 serial ports (top main console)
- L) on board Oscillator: 66M
-
- The MPC837xE-RDB's have the following differences:
-
- MPC8377E-RDB MPC8378E-RDB MPC8379E-RDB
- SATA controllers 2 0 4
- PCI-Express (mini) 2 2 0
- SGMII Ports 0 2 0
-
-
-2. Memory Map
-
-2.1. The memory map should look pretty much like this:
-
- Address Range Device Size Port Size
- (Bytes) (Bits)
- =========================== ================= ======= =========
- 0x0000_0000 0x0fff_ffff DDR 256M 64
- 0x1000_0000 0x7fff_ffff Empty 1.75G -
- 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 32
- 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 32
- 0xe030_0000 0xe03f_ffff PCI I/O space 1M 32
- 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M -
- 0xe060_0000 0xe060_7fff NAND Flash 32K 8
- 0xfe00_0000 0xfe7f_ffff NOR Flash on CS0 8M 16
-
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC837XERDB.h
-
- CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
- CONFIG_MPC837x MPC837x specific
- CONFIG_MPC837XERDB MPC837xE-RDB board specific
-
-
-4. Compilation
-
- Assuming you're using BASH shell:
-
- export CROSS_COMPILE=your-cross-compile-prefix
- cd u-boot
- make distclean
- make MPC837XERDB_config
- make
-
-
-5. Downloading and Flashing Images
-
-5.0 Download over serial line using Kermit:
-
- loadb $loadaddr
- [Drop to kermit:
- ^\c
- send <u-boot-bin-image>
- c
- ]
-
-
- Or via tftp:
-
- tftp $loadaddr u-boot.bin
-
-5.1 Reflash U-Boot Image using U-Boot
-
- tftp $loadaddr u-boot.bin
- protect off fe000000 fe0fffff
- erase fe000000 fe0fffff
- cp.b $loadaddr fe000000 $filesize
-
-
-6. Additional Notes:
- 1) The console is connected to the top RS-232 connector and the
- baudrate for MPC837XE-RDB is 115200bps.
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
deleted file mode 100644
index 81d31f19c4c1..000000000000
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ /dev/null
@@ -1,226 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- * Kevin Lam <kevin.lam at freescale.com>
- * Joe D'Abbraccio <joe.d'abbraccio at freescale.com>
- */
-
-#include <common.h>
-#include <env.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <init.h>
-#include <asm/bitops.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-#include <fdt_support.h>
-#include <spd_sdram.h>
-#include <vsc7385.h>
-#include <fsl_esdhc.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int
-testdram(void)
-{
- uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
- uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
- uint *p;
-
- printf("Testing DRAM from 0x%08x to 0x%08x\n",
- CONFIG_SYS_MEMTEST_START,
- CONFIG_SYS_MEMTEST_END);
-
- printf("DRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test passed.\n");
- return 0;
-}
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-void ddr_enable_ecc(unsigned int dram_size);
-#endif
-int fixed_sdram(void);
-
-int dram_init(void)
-{
- immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -ENXIO;
-
-#if defined(CONFIG_SPD_EEPROM)
- msize = spd_sdram();
-#else
- msize = fixed_sdram();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /* Initialize DDR ECC byte */
- ddr_enable_ecc(msize * 1024 * 1024);
-#endif
- /* return total bus DDR size(bytes) */
- gd->ram_size = msize * 1024 * 1024;
-
- return 0;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
- u32 msize_log2 = __ilog2(msize);
-
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-
- im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
- udelay(50000);
-
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
- udelay(1000);
-
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- udelay(1000);
-
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- sync();
- udelay(1000);
-
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- udelay(2000);
- return CONFIG_SYS_DDR_SIZE;
-}
-#endif /*!CONFIG_SYS_SPD_EEPROM */
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC837xERDB\n");
- return 0;
-}
-
-int board_early_init_f(void)
-{
-#ifdef CONFIG_FSL_SERDES
- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- u32 spridr = in_be32(&immr->sysconf.spridr);
-
- /* we check only part num, and don't look for CPU revisions */
- switch (PARTID_NO_E(spridr)) {
- case SPR_8377:
- fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- break;
- case SPR_8378:
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- break;
- case SPR_8379:
- fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- break;
- default:
- printf("serdes not configured: unknown CPU part number: "
- "%04x\n", spridr >> 16);
- break;
- }
-#endif /* CONFIG_FSL_SERDES */
- return 0;
-}
-
-#ifdef CONFIG_FSL_ESDHC
-int board_mmc_init(struct bd_info *bd)
-{
- struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
- char buffer[HWCONFIG_BUFFER_SIZE] = {0};
- int esdhc_hwconfig_enabled = 0;
-
- if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
- esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
-
- if (esdhc_hwconfig_enabled == 0)
- return 0;
-
- clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
- clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
-
- return fsl_esdhc_mmc_init(bd);
-}
-#endif
-
-/*
- * Miscellaneous late-boot configurations
- *
- * If a VSC7385 microcode image is present, then upload it.
-*/
-int misc_init_r(void)
-{
- int rc = 0;
-
-#ifdef CONFIG_VSC7385_IMAGE
- if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
- CONFIG_VSC7385_IMAGE_SIZE)) {
- puts("Failure uploading VSC7385 microcode.\n");
- rc = 1;
- }
-#endif
-
- return rc;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
- fsl_fdt_fixup_dr_usb(blob, bd);
- fdt_fixup_esdhc(blob, bd);
-
- return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c
deleted file mode 100644
index dccf8c5551b0..000000000000
--- a/board/freescale/mpc837xerdb/pci.c
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-static struct pci_region pci_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI_MEM_BASE,
- phys_start: CONFIG_SYS_PCI_MEM_PHYS,
- size: CONFIG_SYS_PCI_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
- size: CONFIG_SYS_PCI_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
- {
- bus_start: CONFIG_SYS_PCI_IO_BASE,
- phys_start: CONFIG_SYS_PCI_IO_PHYS,
- size: CONFIG_SYS_PCI_IO_SIZE,
- flags: PCI_REGION_IO
- }
-};
-
-static struct pci_region pcie_regions_0[] = {
- {
- .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
- .size = CONFIG_SYS_PCIE1_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
- .size = CONFIG_SYS_PCIE1_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-static struct pci_region pcie_regions_1[] = {
- {
- .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
- .size = CONFIG_SYS_PCIE2_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
- .size = CONFIG_SYS_PCIE2_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile sysconf83xx_t *sysconf = &immr->sysconf;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile law83xx_t *pcie_law = sysconf->pcielaw;
- struct pci_region *reg[] = { pci_regions };
- struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
- u32 spridr = in_be32(&immr->sysconf.spridr);
-
- /* Enable all 5 PCI_CLK_OUTPUTS */
- clk->occr |= 0xf8000000;
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-
- /* There is no PEX in MPC8379 parts. */
- if (PARTID_NO_E(spridr) == SPR_8379)
- return;
-
- /* Configure the clock for PCIE controller */
- clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
- SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
-
- /* Deassert the resets in the control register */
- out_be32(&sysconf->pecr1, 0xE0008000);
- out_be32(&sysconf->pecr2, 0xE0008000);
- udelay(2000);
-
- /* Configure PCI Express Local Access Windows */
- out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- mpc83xx_pcie_init(2, pcie_reg);
-}
diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig
deleted file mode 100644
index ea84564d9af8..000000000000
--- a/configs/MPC837XERDB_SLAVE_defconfig
+++ /dev/null
@@ -1,142 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_CLK_FREQ=66666667
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC837XERDB=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_5_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_RGMII=y
-CONFIG_TSEC2_MODE_RGMII=y
-CONFIG_LDP_PIN_MUX_STATE_0=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM_LOWER"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="SDRAM_UPPER"
-CONFIG_BAT1_BASE=0x10000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="IMMR"
-CONFIG_BAT2_BASE=0xE0000000
-CONFIG_BAT2_LENGTH_8_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="L2_SWITCH"
-CONFIG_BAT3_BASE=0xF0000000
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_INHIBITED=y
-CONFIG_BAT3_ICACHE_GUARDED=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_8_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE0600000
-CONFIG_LBLAW1_NAME="NAND"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW2=y
-CONFIG_LBLAW2_BASE=0xF0000000
-CONFIG_LBLAW2_NAME="VSC7385"
-CONFIG_LBLAW2_LENGTH_128_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_SCY_9=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_EHTR_1_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSECEP_3=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_8=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE"
-CONFIG_BOOTDELAY=6
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-CONFIG_FSL_SATA=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
deleted file mode 100644
index 0d8ec8e9cafd..000000000000
--- a/configs/MPC837XERDB_defconfig
+++ /dev/null
@@ -1,186 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_CLK_FREQ=66666667
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC837XERDB=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_5_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_RGMII=y
-CONFIG_TSEC2_MODE_RGMII=y
-CONFIG_LDP_PIN_MUX_STATE_0=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM_LOWER"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="SDRAM_UPPER"
-CONFIG_BAT1_BASE=0x10000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="IMMR"
-CONFIG_BAT2_BASE=0xE0000000
-CONFIG_BAT2_LENGTH_8_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="L2_SWITCH"
-CONFIG_BAT3_BASE=0xF0000000
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_INHIBITED=y
-CONFIG_BAT3_ICACHE_GUARDED=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT4=y
-CONFIG_BAT4_NAME="FLASH"
-CONFIG_BAT4_BASE=0xFE000000
-CONFIG_BAT4_LENGTH_32_MBYTES=y
-CONFIG_BAT4_ACCESS_RW=y
-CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT4_DCACHE_INHIBITED=y
-CONFIG_BAT4_DCACHE_GUARDED=y
-CONFIG_BAT4_USER_MODE_VALID=y
-CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="STACH_IN_DCACHE"
-CONFIG_BAT5_BASE=0xE6000000
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="PCI_MEM"
-CONFIG_BAT6_BASE=0x80000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT7=y
-CONFIG_BAT7_NAME="PCI_MMIO"
-CONFIG_BAT7_BASE=0x90000000
-CONFIG_BAT7_LENGTH_256_MBYTES=y
-CONFIG_BAT7_ACCESS_RW=y
-CONFIG_BAT7_ICACHE_INHIBITED=y
-CONFIG_BAT7_ICACHE_GUARDED=y
-CONFIG_BAT7_DCACHE_INHIBITED=y
-CONFIG_BAT7_DCACHE_GUARDED=y
-CONFIG_BAT7_USER_MODE_VALID=y
-CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_8_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE0600000
-CONFIG_LBLAW1_NAME="NAND"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW2=y
-CONFIG_LBLAW2_BASE=0xF0000000
-CONFIG_LBLAW2_NAME="VSC7385"
-CONFIG_LBLAW2_LENGTH_128_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_SCY_9=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_EHTR_1_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSECEP_3=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_8=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCIE"
-CONFIG_BOOTDELAY=6
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-CONFIG_FSL_SATA=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
deleted file mode 100644
index ae368a1f1e30..000000000000
--- a/include/configs/MPC837XERDB.h
+++ /dev/null
@@ -1,412 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- * Kevin Lam <kevin.lam at freescale.com>
- * Joe D'Abbraccio <joe.d'abbraccio at freescale.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-
-#define CONFIG_HWCONFIG
-
-/*
- * On-board devices
- */
-#define CONFIG_VSC7385_ENET
-
-/* System performance - define the value i.e. CONFIG_SYS_XXX
-*/
-
-/* System Clock Configuration Register */
-#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH 0x08200000
-#define CONFIG_SYS_SICRL 0x00000000
-
-/*
- * Output Buffer Impedance
- */
-#define CONFIG_SYS_OBIR 0x30100000
-
-/*
- * Device configurations
- */
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
-#define CONFIG_TSEC2
-
-/* The flash address and size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE 0xFE7FE000
-#define CONFIG_VSC7385_IMAGE_SIZE 8192
-
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
-
-#undef CONFIG_DDR_ECC /* support DDR ECC function */
-#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
-
-#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ODT_WR_ONLY_CURRENT \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00260802 */ /* DDR400 */
-#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (7 << TIMING_CFG1_CASLAT_SHIFT) \
- | (13 << TIMING_CFG1_REFREC_SHIFT) \
- | (3 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x3937d322 */
-#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (5 << TIMING_CFG2_CPO_SHIFT) \
- | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x02984cc8 */
-
-#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x06090100 */
-
-#if defined(CONFIG_DDR_2T_TIMING)
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE \
- | SDRAM_CFG_2T_EN)
- /* 0x43088000 */
-#else
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2)
- /* 0x43000000 */
-#endif
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0442 << SDRAM_MODE_SD_SHIFT))
- /* 0x04400442 */ /* DDR400 */
-#define CONFIG_SYS_DDR_MODE2 0x00000000
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-/*
- * NAND Flash on the Local Bus
- */
-#define CONFIG_SYS_NAND_BASE 0xE0600000
-
-
-/* Vitesse 7385 */
-
-#define CONFIG_SYS_VSC7385_BASE 0xF0000000
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* SERDES */
-#define CONFIG_FSL_SERDES
-#define CONFIG_FSL_SERDES1 0xe3000
-#define CONFIG_FSL_SERDES2 0xe3100
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
-#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
-
-#define CONFIG_SYS_PCIE1_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
-
-#define CONFIG_SYS_PCIE2_BASE 0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
-#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-#endif /* CONFIG_PCI */
-
-/*
- * TSEC
- */
-#ifdef CONFIG_TSEC_ENET
-
-#define CONFIG_GMII /* MII PHY management */
-
-#define CONFIG_TSEC1
-
-#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define TSEC1_PHY_ADDR 2
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC1_PHYIDX 0
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define TSEC2_PHY_ADDR 0x1c
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_PHYIDX 0
-#endif
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#endif
-
-/*
- * SATA
- */
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1_OFFSET 0x18000
-#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2_OFFSET 0x19000
-#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#ifdef CONFIG_FSL_SATA
-#define CONFIG_LBA48
-#endif
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC_PIN_MUX
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-#define CONFIG_NETDEV "eth1"
-
-#define CONFIG_HOSTNAME "mpc837x_rdb"
-#define CONFIG_ROOTPATH "/nfsroot"
-#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
-#define CONFIG_BOOTFILE "uImage"
- /* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH "u-boot.bin"
-#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
-
- /* default location for tftp and bootm */
-#define CONFIG_LOADADDR 800000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" CONFIG_NETDEV "\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "tftpflash=tftp $loadaddr $uboot;" \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=780000\0" \
- "fdtfile=" CONFIG_FDTFILE "\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
- "console=ttyS0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setbootargs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif /* __CONFIG_H */
--
2.17.1
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