[PATCH 55/57] ppc: Remove T1023RDB board
Y.b. Lu
yangbo.lu at nxp.com
Mon Feb 22 09:58:40 CET 2021
Hi Tom,
> -----Original Message-----
> From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Tom Rini
> Sent: Sunday, February 21, 2021 9:07 AM
> To: u-boot at lists.denx.de
> Cc: Priyanka Jain <priyanka.jain at nxp.com>
> Subject: [PATCH 55/57] ppc: Remove T1023RDB board
>
> This board has not been converted to CONFIG_DM_MMC by the deadline.
> Remove it. As this is the last ARCH_T1023 platform, remove that support
> as well.
>
> Cc: Priyanka Jain <priyanka.jain at nxp.com>
> Signed-off-by: Tom Rini <trini at konsulko.com>
> ---
> arch/powerpc/cpu/mpc85xx/Kconfig | 38 +-
> arch/powerpc/cpu/mpc85xx/Makefile | 2 -
> arch/powerpc/cpu/mpc85xx/speed.c | 4 +-
> arch/powerpc/include/asm/config_mpc85xx.h | 2 +-
> arch/powerpc/include/asm/fsl_secure_boot.h | 1 -
> arch/powerpc/include/asm/immap_85xx.h | 4 +-
> board/freescale/t102xrdb/Kconfig | 14 -
> board/freescale/t102xrdb/MAINTAINERS | 15 -
> board/freescale/t102xrdb/Makefile | 17 -
> board/freescale/t102xrdb/README | 340 ----------
> board/freescale/t102xrdb/cpld.c | 102 ---
> board/freescale/t102xrdb/cpld.h | 48 --
> board/freescale/t102xrdb/ddr.c | 258 -------
> board/freescale/t102xrdb/eth_t102xrdb.c | 149 ----
> board/freescale/t102xrdb/law.c | 31 -
> board/freescale/t102xrdb/pci.c | 25 -
> board/freescale/t102xrdb/spl.c | 142 ----
> board/freescale/t102xrdb/t1023_nand_rcw.cfg | 8 -
> board/freescale/t102xrdb/t1023_sd_rcw.cfg | 8 -
> board/freescale/t102xrdb/t1023_spi_rcw.cfg | 8 -
> board/freescale/t102xrdb/t1024_nand_rcw.cfg | 8 -
> board/freescale/t102xrdb/t1024_pbi.cfg | 26 -
> board/freescale/t102xrdb/t1024_sd_rcw.cfg | 8 -
> board/freescale/t102xrdb/t1024_spi_rcw.cfg | 8 -
> board/freescale/t102xrdb/t102xrdb.c | 397 -----------
> board/freescale/t102xrdb/t102xrdb.h | 15 -
> board/freescale/t102xrdb/tlb.c | 116 ----
> configs/T1023RDB_NAND_defconfig | 80 ---
> configs/T1023RDB_SDCARD_defconfig | 77 ---
> configs/T1023RDB_SECURE_BOOT_defconfig | 67 --
> configs/T1023RDB_SPIFLASH_defconfig | 79 ---
> configs/T1023RDB_defconfig | 64 --
> configs/T1024RDB_NAND_defconfig | 93 ---
> configs/T1024RDB_SDCARD_defconfig | 90 ---
> configs/T1024RDB_SECURE_BOOT_defconfig | 71 --
> configs/T1024RDB_SPIFLASH_defconfig | 92 ---
> configs/T1024RDB_defconfig | 78 ---
DM_MMC had already been in use for T1024RDB. The board is still in maintaining.
Can we keep it?
Thanks.
> drivers/net/Kconfig | 1 -
> drivers/net/fm/Makefile | 1 -
> include/configs/T102xRDB.h | 709 --------------------
> 40 files changed, 6 insertions(+), 3290 deletions(-)
> delete mode 100644 board/freescale/t102xrdb/Kconfig
> delete mode 100644 board/freescale/t102xrdb/MAINTAINERS
> delete mode 100644 board/freescale/t102xrdb/Makefile
> delete mode 100644 board/freescale/t102xrdb/README
> delete mode 100644 board/freescale/t102xrdb/cpld.c
> delete mode 100644 board/freescale/t102xrdb/cpld.h
> delete mode 100644 board/freescale/t102xrdb/ddr.c
> delete mode 100644 board/freescale/t102xrdb/eth_t102xrdb.c
> delete mode 100644 board/freescale/t102xrdb/law.c
> delete mode 100644 board/freescale/t102xrdb/pci.c
> delete mode 100644 board/freescale/t102xrdb/spl.c
> delete mode 100644 board/freescale/t102xrdb/t1023_nand_rcw.cfg
> delete mode 100644 board/freescale/t102xrdb/t1023_sd_rcw.cfg
> delete mode 100644 board/freescale/t102xrdb/t1023_spi_rcw.cfg
> delete mode 100644 board/freescale/t102xrdb/t1024_nand_rcw.cfg
> delete mode 100644 board/freescale/t102xrdb/t1024_pbi.cfg
> delete mode 100644 board/freescale/t102xrdb/t1024_sd_rcw.cfg
> delete mode 100644 board/freescale/t102xrdb/t1024_spi_rcw.cfg
> delete mode 100644 board/freescale/t102xrdb/t102xrdb.c
> delete mode 100644 board/freescale/t102xrdb/t102xrdb.h
> delete mode 100644 board/freescale/t102xrdb/tlb.c
> delete mode 100644 configs/T1023RDB_NAND_defconfig
> delete mode 100644 configs/T1023RDB_SDCARD_defconfig
> delete mode 100644 configs/T1023RDB_SECURE_BOOT_defconfig
> delete mode 100644 configs/T1023RDB_SPIFLASH_defconfig
> delete mode 100644 configs/T1023RDB_defconfig
> delete mode 100644 configs/T1024RDB_NAND_defconfig
> delete mode 100644 configs/T1024RDB_SDCARD_defconfig
> delete mode 100644 configs/T1024RDB_SECURE_BOOT_defconfig
> delete mode 100644 configs/T1024RDB_SPIFLASH_defconfig
> delete mode 100644 configs/T1024RDB_defconfig
> delete mode 100644 include/configs/T102xRDB.h
>
> diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig
> b/arch/powerpc/cpu/mpc85xx/Kconfig
> index 55cce515ccf0..42c4d1f0399e 100644
> --- a/arch/powerpc/cpu/mpc85xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc85xx/Kconfig
> @@ -124,16 +124,6 @@ config TARGET_QEMU_PPCE500
> select ARCH_QEMU_E500
> select PHYS_64BIT
>
> -config TARGET_T1023RDB
> - bool "Support T1023RDB"
> - select ARCH_T1023
> - select BOARD_LATE_INIT if CHAIN_OF_TRUST
> - select SUPPORT_SPL
> - select PHYS_64BIT
> - select FSL_DDR_INTERACTIVE
> - imply CMD_EEPROM
> - imply PANIC_HANG
> -
> config TARGET_T1024RDB
> bool "Support T1024RDB"
> select ARCH_T1024
> @@ -722,27 +712,6 @@ config ARCH_P5040
> config ARCH_QEMU_E500
> bool
>
> -config ARCH_T1023
> - bool
> - select E500MC
> - select FSL_LAW
> - select SYS_FSL_DDR_VER_50
> - select SYS_FSL_ERRATUM_A008378
> - select SYS_FSL_ERRATUM_A008109
> - select SYS_FSL_ERRATUM_A009663
> - select SYS_FSL_ERRATUM_A009942
> - select SYS_FSL_ERRATUM_ESDHC111
> - select SYS_FSL_HAS_DDR3
> - select SYS_FSL_HAS_DDR4
> - select SYS_FSL_HAS_SEC
> - select SYS_FSL_QORIQ_CHASSIS2
> - select SYS_FSL_SEC_BE
> - select SYS_FSL_SEC_COMPAT_5
> - select FSL_IFC
> - imply CMD_EEPROM
> - imply CMD_NAND
> - imply CMD_REGINFO
> -
> config ARCH_T1024
> bool
> select E500MC
> @@ -952,7 +921,6 @@ config MAX_CPUS
> ARCH_P1024 || \
> ARCH_P1025 || \
> ARCH_P2020 || \
> - ARCH_T1023 || \
> ARCH_T1024
> default 1
> help
> @@ -990,7 +958,6 @@ config SYS_CCSRBAR_DEFAULT
> ARCH_P3041 || \
> ARCH_P4080 || \
> ARCH_P5040 || \
> - ARCH_T1023 || \
> ARCH_T1024 || \
> ARCH_T1040 || \
> ARCH_T1042 || \
> @@ -1182,8 +1149,7 @@ config SYS_FSL_NUM_LAWS
> ARCH_T2080 || \
> ARCH_T4160 || \
> ARCH_T4240
> - default 16 if ARCH_T1023 || \
> - ARCH_T1024 || \
> + default 16 if ARCH_T1024 || \
> ARCH_T1040 || \
> ARCH_T1042
> default 12 if ARCH_BSC9131 || \
> @@ -1264,7 +1230,6 @@ config SYS_FSL_IFC_CLK_DIV
> default 2 if ARCH_B4420 || \
> ARCH_B4860 || \
> ARCH_T1024 || \
> - ARCH_T1023 || \
> ARCH_T1040 || \
> ARCH_T1042 || \
> ARCH_T4160 || \
> @@ -1300,7 +1265,6 @@ source "board/freescale/p1010rdb/Kconfig"
> source "board/freescale/p1_p2_rdb_pc/Kconfig"
> source "board/freescale/p2041rdb/Kconfig"
> source "board/freescale/qemu-ppce500/Kconfig"
> -source "board/freescale/t102xrdb/Kconfig"
> source "board/freescale/t208xqds/Kconfig"
> source "board/freescale/t208xrdb/Kconfig"
> source "board/freescale/t4rdb/Kconfig"
> diff --git a/arch/powerpc/cpu/mpc85xx/Makefile
> b/arch/powerpc/cpu/mpc85xx/Makefile
> index b9d87ddb655e..4d9a07b5d9c3 100644
> --- a/arch/powerpc/cpu/mpc85xx/Makefile
> +++ b/arch/powerpc/cpu/mpc85xx/Makefile
> @@ -47,7 +47,6 @@ obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
> obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
> obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
> obj-$(CONFIG_ARCH_T1042) += t1040_ids.o
> -obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
> obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
> obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
>
> @@ -83,7 +82,6 @@ obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
> obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
> obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o
> obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o
> -obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
> obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
> obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
>
> diff --git a/arch/powerpc/cpu/mpc85xx/speed.c
> b/arch/powerpc/cpu/mpc85xx/speed.c
> index 864c53ce2ecb..5a545a6d6412 100644
> --- a/arch/powerpc/cpu/mpc85xx/speed.c
> +++ b/arch/powerpc/cpu/mpc85xx/speed.c
> @@ -201,7 +201,7 @@ void get_sys_info(sys_info_t *sys_info)
> defined(CONFIG_ARCH_T2080)
> #define FM1_CLK_SEL 0xe0000000
> #define FM1_CLK_SHIFT 29
> -#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
> +#elif defined(CONFIG_ARCH_T1024)
> #define FM1_CLK_SEL 0x00000007
> #define FM1_CLK_SHIFT 0
> #else
> @@ -211,7 +211,7 @@ void get_sys_info(sys_info_t *sys_info)
> #define FM1_CLK_SHIFT 26
> #endif
> #if !defined(CONFIG_FM_PLAT_CLK_DIV)
> || !defined(CONFIG_PME_PLAT_CLK_DIV)
> -#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
> +#if defined(CONFIG_ARCH_T1024)
> rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
> #else
> rcw_tmp = in_be32(&gur->rcwsr[7]);
> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
> b/arch/powerpc/include/asm/config_mpc85xx.h
> index 20535487310f..a52b31ec3950 100644
> --- a/arch/powerpc/include/asm/config_mpc85xx.h
> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
> @@ -313,7 +313,7 @@
> #define QE_NUM_OF_SNUM 28
> #define CONFIG_SYS_FSL_SFP_VER_3_0
>
> -#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
> +#elif defined(CONFIG_ARCH_T1024)
> #define CONFIG_E5500
> #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
> #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
> diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h
> b/arch/powerpc/include/asm/fsl_secure_boot.h
> index 53bfb8f64af7..991d75312a34 100644
> --- a/arch/powerpc/include/asm/fsl_secure_boot.h
> +++ b/arch/powerpc/include/asm/fsl_secure_boot.h
> @@ -28,7 +28,6 @@
> defined(CONFIG_TARGET_T1042RDB) || \
> defined(CONFIG_TARGET_T1042D4RDB) || \
> defined(CONFIG_TARGET_T1042RDB_PI) || \
> - defined(CONFIG_ARCH_T1023) || \
> defined(CONFIG_ARCH_T1024)
> #ifndef CONFIG_SYS_RAMBOOT
> #define CONFIG_SYS_CPC_REINIT_F
> diff --git a/arch/powerpc/include/asm/immap_85xx.h
> b/arch/powerpc/include/asm/immap_85xx.h
> index 7a1a86881eb1..1b3097772fb8 100644
> --- a/arch/powerpc/include/asm/immap_85xx.h
> +++ b/arch/powerpc/include/asm/immap_85xx.h
> @@ -1793,7 +1793,7 @@ typedef struct ccsr_gur {
> #define PXCKEN_MASK 0x80000000
> #define PXCK_MASK 0x00FF0000
> #define PXCK_BITS_START 16
> -#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
> +#elif defined(CONFIG_ARCH_T1024)
> #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
> #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
> #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
> @@ -2501,7 +2501,7 @@ typedef struct ccsr_gur {
>
> #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
> #define MAX_SERDES 4
> -#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
> +#if defined(CONFIG_ARCH_T1024)
> #define SRDS_MAX_LANES 4
> #else
> #define SRDS_MAX_LANES 8
> diff --git a/board/freescale/t102xrdb/Kconfig
> b/board/freescale/t102xrdb/Kconfig
> deleted file mode 100644
> index 6deeb248a300..000000000000
> --- a/board/freescale/t102xrdb/Kconfig
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -if TARGET_T1023RDB || TARGET_T1024RDB
> -
> -config SYS_BOARD
> - default "t102xrdb"
> -
> -config SYS_VENDOR
> - default "freescale"
> -
> -config SYS_CONFIG_NAME
> - default "T102xRDB"
> -
> -source "board/freescale/common/Kconfig"
> -
> -endif
> diff --git a/board/freescale/t102xrdb/MAINTAINERS
> b/board/freescale/t102xrdb/MAINTAINERS
> deleted file mode 100644
> index 6c24f7785ce4..000000000000
> --- a/board/freescale/t102xrdb/MAINTAINERS
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -T102XRDB BOARD
> -#M: Shengzhou Liu <Shengzhou.Liu at freescale.com>
> -S: Orphan (since 2018-05)
> -F: board/freescale/t102xrdb/
> -F: include/configs/T102xRDB.h
> -F: configs/T1024RDB_defconfig
> -F: configs/T1024RDB_NAND_defconfig
> -F: configs/T1024RDB_SDCARD_defconfig
> -F: configs/T1024RDB_SPIFLASH_defconfig
> -F: configs/T1024RDB_SECURE_BOOT_defconfig
> -F: configs/T1023RDB_defconfig
> -F: configs/T1023RDB_NAND_defconfig
> -F: configs/T1023RDB_SDCARD_defconfig
> -F: configs/T1023RDB_SPIFLASH_defconfig
> -F: configs/T1023RDB_SECURE_BOOT_defconfig
> diff --git a/board/freescale/t102xrdb/Makefile
> b/board/freescale/t102xrdb/Makefile
> deleted file mode 100644
> index ddeb44f36e22..000000000000
> --- a/board/freescale/t102xrdb/Makefile
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -#
> -# Copyright 2014 Freescale Semiconductor, Inc.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -ifdef CONFIG_SPL_BUILD
> -obj-y += spl.o
> -else
> -obj-y += t102xrdb.o
> -obj-$(CONFIG_TARGET_T1024RDB) += cpld.o
> -obj-y += eth_t102xrdb.o
> -obj-$(CONFIG_PCI) += pci.o
> -endif
> -obj-y += ddr.o
> -obj-y += law.o
> -obj-y += tlb.o
> diff --git a/board/freescale/t102xrdb/README
> b/board/freescale/t102xrdb/README
> deleted file mode 100644
> index dde3f8ca37f6..000000000000
> --- a/board/freescale/t102xrdb/README
> +++ /dev/null
> @@ -1,340 +0,0 @@
> -T1024 SoC Overview
> -------------------
> -The T1024/T1023 dual core and T1014/T1013 single core QorIQ
> communication processor
> -combines two or one 64-bit Power Architecture e5500 core respectively with
> high
> -performance datapath acceleration logic, and network peripheral bus
> interfaces
> -required for networking and telecommunications. This processor can be used
> in
> -applications such as enterprise WLAN access points, routers, switches, firewall
> -and other packet processing intensive small enterprise and branch office
> appliances,
> -and general-purpose embedded computing. Its high level of integration offers
> -significant performance benefits and greatly helps to simplify board design.
> -
> -
> -The T1024 SoC includes the following function and features:
> -- two e5500 cores, each with a private 256 KB L2 cache
> - - Up to 1.4 GHz with 64-bit ISA support (Power Architecture
> v2.06-compliant)
> - - Three levels of instructions: User, supervisor, and hypervisor
> - - Independent boot and reset
> - - Secure boot capability
> -- 256 KB shared L3 CoreNet platform cache (CPC)
> -- Interconnect CoreNet platform
> - - CoreNet coherency manager supporting coherent and noncoherent
> transactions
> - with prioritization and bandwidth allocation amongst CoreNet endpoints
> - - 150 Gbps coherent read bandwidth
> -- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
> interleaving support
> -- Data Path Acceleration Architecture (DPAA) incorporating acceleration for
> the following functions:
> - - Packet parsing, classification, and distribution
> - - Queue management for scheduling, packet sequencing, and congestion
> management
> - - Cryptography Acceleration (SEC 5.x)
> - - IEEE 1588 support
> - - Hardware buffer management for buffer allocation and deallocation
> - - MACSEC on DPAA-based Ethernet ports
> -- Ethernet interfaces
> - - Four 1 Gbps Ethernet controllers
> -- Parallel Ethernet interfaces
> - - Two RGMII interfaces
> -- High speed peripheral interfaces
> - - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
> - - One SATA controller supporting 1.5 and 3.0 Gb/s operation
> - - One QSGMII interface
> - - Four SGMII interface supporting 1000 Mbps
> - - Three SGMII interfaces supporting up to 2500 Mbps
> - - 10GbE XFI or 10Base-KR interface
> -- Additional peripheral interfaces
> - - Two USB 2.0 controllers with integrated PHY
> - - SD/eSDHC/eMMC
> - - eSPI controller
> - - Four I2C controllers
> - - Four UARTs
> - - Four GPIO controllers
> - - Integrated flash controller (IFC)
> - - LCD interface (DIU) with 12 bit dual data rate
> -- Multicore programmable interrupt controller (PIC)
> -- Two 8-channel DMA engines
> -- Single source clocking implementation
> -- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
> -- QUICC Engine block
> - - 32-bit RISC controller for flexible support of the communications
> peripherals
> - - Serial DMA channel for receive and transmit on all serial channels
> - - Two universal communication controllers, supporting TDM, HDLC, and
> UART
> -
> -T1023 Personality
> -------------------
> -T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
> -unavailable deep sleep. Rest of the blocks are almost same as T1024.
> -Differences between T1024 and T1023
> -Feature T1024 T1023
> -QUICC Engine: yes no
> -DIU: yes no
> -Deep Sleep: yes no
> -I2C controller: 4 3
> -DDR: 64-bit 32-bit
> -IFC: 32-bit 28-bit
> -Package: 23x23 19x19
> -
> -
> -T1024RDB board Overview
> ------------------------
> - - Ethernet
> - - Two on-board 10M/100M/1G bps RGMII ethernet ports
> - - One on-board 10G bps Base-T port.
> - - DDR Memory
> - - Supports 64-bit 4GB DDR3L DIMM
> - - PCIe
> - - One on-board PCIe slot.
> - - Two on-board PCIe Mini-PCIe connectors.
> - - IFC/Local Bus
> - - NOR: 128MB 16-bit NOR Flash
> - - NAND: 1GB 8-bit NAND flash
> - - CPLD: for system controlling with programable header on-board
> - - USB
> - - Supports two USB 2.0 ports with integrated PHYs
> - - Two type A ports with 5V at 1.5A per port.
> - - SDHC
> - - one SD connector supporting 1.8V/3.3V via J53.
> - - SPI
> - - On-board 64MB SPI flash
> - - Other
> - - Two Serial ports
> - - Four I2C ports
> -
> -
> -T1023RDB board Overview
> ------------------------
> -- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
> -- CoreNet fabric supporting coherent and noncoherent transactions with
> - prioritization and bandwidth allocation
> -- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o
> ECC
> -- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
> -- Ethernet interfaces:
> - - one 1G RGMII port on-board(RTL8211FS PHY)
> - - one 1G SGMII port on-board(RTL8211FS PHY)
> - - one 2.5G SGMII port on-board(AQR105 PHY)
> -- PCIe: Two Mini-PCIe connectors on-board.
> -- SerDes: 4 lanes up to 10.3125GHz
> -- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
> -- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
> -- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
> -- USB: one Type-A USB 2.0 port with internal PHY
> -- eSDHC: support SD/MMC and eMMC card
> -- 256Kbit M24256 I2C EEPROM
> -- RTC: Real-time clock DS1339U on I2C bus
> -- UART: one serial port on-board with RJ45 connector
> -- Debugging: JTAG/COP for T1023 debugging
> -
> -
> -Memory map on T1024RDB
> -----------------------
> -Start Address End Address Description Size
> -0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
> -0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
> -0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
> -0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
> -0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
> -0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
> -0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal
> 32MB
> -0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
> -0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
> -0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
> -0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space
> 256MB
> -0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space
> 256MB
> -0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space
> 256MB
> -0x0_0000_0000 0x0_ffff_ffff DDR 4GB
> -
> -
> -128MB NOR Flash Memory Layout
> ------------------------------
> -Start Address End Address Definition Max size
> -0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
> -0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
> -0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
> -0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
> -0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB
> -0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB
> -0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB
> -0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB
> -0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB
> -0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
> -0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB
> -0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB
> -0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
> -0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
> -0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
> -0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
> -0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
> -0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB
> -0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB
> -0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB
> -0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB
> -0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB
> -0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
> -0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB
> -0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB
> -0xE8000000 0xE801FFFF RCW (current bank) 128KB
> -
> -
> -T1024/T1023 Clock frequency
> ----------------------------
> -BIN Core DDR Platform FMan
> -Bin1: 1400MHz 1600MT/s 400MHz 700MHz
> -Bin2: 1200MHz 1600MT/s 400MHz 600MHz
> -Bin3: 1000MHz 1600MT/s 400MHz 500MHz
> -
> -
> -Software configurations and board settings
> -------------------------------------------
> -1. NOR boot:
> - a. build NOR boot image
> - $ make T1024RDB_defconfig
> - $ make
> - b. program u-boot.bin image to NOR flash
> - => tftp 1000000 u-boot.bin
> - => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
> - on T1024RDB:
> - set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
> - on T1023RDB:
> - set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
> -
> - Switching between default bank0 and alternate bank4 on NOR flash
> - To change boot source to vbank4:
> - on T1024RDB:
> - via software: run command 'cpld reset altbank' in U-Boot.
> - via DIP-switch: set SW3[5:7] = '100'
> - on T1023RDB:
> - via software: run command 'switch bank4' in U-Boot.
> - via DIP-switch: set SW3[5:7] = '100'
> -
> - To change boot source to vbank0:
> - on T1024RDB:
> - via software: run command 'cpld reset' in U-Boot.
> - via DIP-Switch: set SW3[5:7] = '000'
> - on T1023RDB:
> - via software: run command 'switch bank0' in U-Boot.
> - via DIP-switch: set SW3[5:7] = '000'
> -
> -2. NAND Boot:
> - a. build PBL image for NAND boot
> - $ make T1024RDB_NAND_defconfig
> - $ make
> - b. program u-boot-with-spl-pbl.bin to NAND flash
> - => tftp 1000000 u-boot-with-spl-pbl.bin
> - => nand erase 0 $filesize
> - => nand write 1000000 0 $filesize
> - set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
> -
> -3. SPI Boot:
> - a. build PBL image for SPI boot
> - $ make T1024RDB_SPIFLASH_defconfig
> - $ make
> - b. program u-boot-with-spl-pbl.bin to SPI flash
> - => tftp 1000000 u-boot-with-spl-pbl.bin
> - => sf probe 0
> - => sf erase 0 100000
> - => sf write 1000000 0 $filesize
> - => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
> - => sf erase 100000 100000
> - => sf write 1000000 110000 20000
> - set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
> -
> -4. SD Boot:
> - a. build PBL image for SD boot
> - $ make T1024RDB_SDCARD_defconfig
> - $ make
> - b. program u-boot-with-spl-pbl.bin to SD/MMC card
> - => tftp 1000000 u-boot-with-spl-pbl.bin
> - => mmc write 1000000 8 0x7f0
> - => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
> - => mmc write 1000000 0x820 80
> - set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
> -
> - SW3[3] = '1' for SD card(or 'switch sd' by software)
> - SW3[3] = '0' for eMMC (or 'switch emmc' by software)
> -
> -
> -device tree support and how to enable it for different configs
> ---------------------------------------------------------------
> -device tree support is available for t1024rdb for below mentioned boot,
> -1. nor boot
> -2. nand boot
> -3. sd boot
> -4. spiflash boot
> -
> -to enable device tree support for other boot, below configs need to be
> -enabled in relative defconfig file,
> -1. config_default_device_tree="t1024rdb" (change default device tree name if
> required)
> -2. config_of_control
> -3. config_mpc85xx_have_reset_vector if reset vector is located at
> - config_reset_vector_address - 0xffc
> -
> -if device tree support is enabled in defconfig,
> -1. use 'u-boot-with-dtb.bin' for nor boot.
> -2. use 'u-boot-with-spl-pbl.bin' for other boot.
> -
> -2-stage NAND/SPI/SD boot loader
> --------------------------------
> -PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
> -SPL further initializes DDR using SPD and environment variables
> -and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
> -Finally SPL transers control to U-Boot for futher booting.
> -
> -SPL has following features:
> - - Executes within 256K
> - - No relocation required
> -
> -Run time view of SPL framework
> --------------------------------------------------
> -|Area | Address |
> --------------------------------------------------
> -|SecureBoot header | 0xFFFC0000 (32KB) |
> --------------------------------------------------
> -|GD, BD | 0xFFFC8000 (4KB) |
> --------------------------------------------------
> -|ENV | 0xFFFC9000 (8KB) |
> --------------------------------------------------
> -|HEAP | 0xFFFCB000 (30KB) |
> --------------------------------------------------
> -|STACK | 0xFFFD8000 (22KB) |
> --------------------------------------------------
> -|U-Boot SPL | 0xFFFD8000 (160KB) |
> --------------------------------------------------
> -
> -NAND Flash memory Map on T1024RDB
> --------------------------------------------------------------
> -Start End Definition Size
> -0x000000 0x0FFFFF U-Boot 1MB(2 block)
> -0x100000 0x17FFFF U-Boot env 512KB(1 block)
> -0x180000 0x1FFFFF FMAN Ucode 512KB(1 block)
> -0x200000 0x27FFFF QE Firmware 512KB(1 block)
> -
> -
> -NAND Flash memory Map on T1023RDB
> -----------------------------------------------------
> -Start End Definition Size
> -0x000000 0x0FFFFF U-Boot 1MB
> -0x100000 0x15FFFF U-Boot env 8KB
> -0x160000 0x17FFFF FMAN Ucode 128KB
> -
> -
> -SD Card memory Map on T102xRDB
> -----------------------------------------------------
> -Block #blocks Definition Size
> -0x008 2048 U-Boot img 1MB
> -0x800 0016 U-Boot env 8KB
> -0x820 0256 FMAN Ucode 128KB
> -0x920 0256 QE Firmware 128KB(only T1024RDB)
> -
> -
> -64MB SPI Flash memory Map on T102xRDB
> -----------------------------------------------------
> -Start End Definition Size
> -0x000000 0x0FFFFF U-Boot img 1MB
> -0x100000 0x101FFF U-Boot env 8KB
> -0x110000 0x12FFFF FMAN Ucode 128KB
> -0x130000 0x14FFFF QE Firmware 128KB(only T1024RDB)
> -0x300000 0x3FFFFF device tree 128KB
> -0x400000 0x9FFFFF Linux kernel 6MB
> -0xa00000 0x3FFFFFF rootfs 54MB
> -
> -
> -For more details, please refer to T1024RDB/T1023RDB User Guide
> -and Freescale QorIQ SDK Infocenter document.
> diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c
> deleted file mode 100644
> index 47c3b1627e34..000000000000
> --- a/board/freescale/t102xrdb/cpld.c
> +++ /dev/null
> @@ -1,102 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/**
> - * Copyright 2014 Freescale Semiconductor
> - *
> - * Freescale T1024RDB board-specific CPLD controlling supports.
> - *
> - * The following macros need to be defined:
> - */
> -
> -#include <common.h>
> -#include <command.h>
> -#include <asm/io.h>
> -#include "cpld.h"
> -
> -u8 cpld_read(unsigned int reg)
> -{
> - void *p = (void *)CONFIG_SYS_CPLD_BASE;
> -
> - return in_8(p + reg);
> -}
> -
> -void cpld_write(unsigned int reg, u8 value)
> -{
> - void *p = (void *)CONFIG_SYS_CPLD_BASE;
> -
> - out_8(p + reg, value);
> -}
> -
> -/**
> - * Set the boot bank to the alternate bank
> - */
> -void cpld_set_altbank(void)
> -{
> - u8 reg = CPLD_READ(flash_csr);
> -
> - reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
> -
> - CPLD_WRITE(flash_csr, reg);
> - CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
> -}
> -
> -/**
> - * Set the boot bank to the default bank
> - */
> -void cpld_set_defbank(void)
> -{
> - u8 reg = CPLD_READ(flash_csr);
> -
> - reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
> -
> - CPLD_WRITE(flash_csr, reg);
> - CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
> -}
> -
> -static void cpld_dump_regs(void)
> -{
> - printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
> - printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
> - printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
> - printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
> - printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
> - printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
> - printf("int_status = 0x%02x\n", CPLD_READ(int_status));
> - printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr));
> - printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
> - printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
> - printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
> - printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
> - printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
> - printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
> - printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
> - putc('\n');
> -}
> -
> -int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
> -{
> - int rc = 0;
> -
> - if (argc <= 1)
> - return cmd_usage(cmdtp);
> -
> - if (strcmp(argv[1], "reset") == 0) {
> - if (strcmp(argv[2], "altbank") == 0)
> - cpld_set_altbank();
> - else
> - cpld_set_defbank();
> - } else if (strcmp(argv[1], "dump") == 0) {
> - cpld_dump_regs();
> - } else {
> - rc = cmd_usage(cmdtp);
> - }
> -
> - return rc;
> -}
> -
> -U_BOOT_CMD(
> - cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
> - "Reset the board or alternate bank",
> - "reset - hard reset to default bank\n"
> - "cpld reset altbank - reset to alternate bank\n"
> - "cpld dump - display the CPLD registers\n"
> - );
> diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h
> deleted file mode 100644
> index c05f536806fb..000000000000
> --- a/board/freescale/t102xrdb/cpld.h
> +++ /dev/null
> @@ -1,48 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/**
> - * Copyright 2014 Freescale Semiconductor
> - *
> - */
> -
> -struct cpld_data {
> - u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
> - u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
> - u8 hw_ver; /* 0x02 - Hardware Revision Register */
> - u8 sw_ver; /* 0x03 - Software Revision register */
> - u8 res0[12]; /* 0x04 - 0x0F - not used */
> - u8 reset_ctl1; /* 0x10 - Reset control Register1 */
> - u8 reset_ctl2; /* 0x11 - Reset control Register2 */
> - u8 int_status; /* 0x12 - Interrupt status Register */
> - u8 flash_csr; /* 0x13 - Flash control and status register */
> - u8 fan_ctl_status; /* 0x14 - Fan control and status register */
> - u8 led_ctl_status; /* 0x15 - LED control and status register */
> - u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
> - u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
> - u8 boot_override; /* 0x18 - Boot override register */
> - u8 boot_config1; /* 0x19 - Boot config override register*/
> - u8 boot_config2; /* 0x1A - Boot config override register*/
> -} cpld_data_t;
> -
> -
> -/* Pointer to the CPLD register set */
> -
> -u8 cpld_read(unsigned int reg);
> -void cpld_write(unsigned int reg, u8 value);
> -
> -#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
> -#define CPLD_WRITE(reg, value)\
> - cpld_write(offsetof(struct cpld_data, reg), value)
> -
> -/* CPLD on IFC */
> -#define CPLD_LBMAP_MASK 0x3F
> -#define CPLD_BANK_SEL_MASK 0x07
> -#define CPLD_BANK_OVERRIDE 0x40
> -#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
> -#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
> -#define CPLD_LBMAP_RESET 0xFF
> -#define CPLD_LBMAP_SHIFT 0x03
> -#define CPLD_BOOT_SEL 0x80
> -
> -#define CPLD_PCIE_SGMII_MUX 0x80
> -#define CPLD_OVERRIDE_BOOT_EN 0x01
> -#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override
> enable */
> diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
> deleted file mode 100644
> index 818c20cf1b5e..000000000000
> --- a/board/freescale/t102xrdb/ddr.c
> +++ /dev/null
> @@ -1,258 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2014 Freescale Semiconductor, Inc.
> - */
> -
> -#include <common.h>
> -#include <i2c.h>
> -#include <hwconfig.h>
> -#include <init.h>
> -#include <log.h>
> -#include <asm/global_data.h>
> -#include <asm/mmu.h>
> -#include <fsl_ddr_sdram.h>
> -#include <fsl_ddr_dimm_params.h>
> -#include <asm/fsl_law.h>
> -#include <asm/mpc85xx_gpio.h>
> -#include <linux/delay.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -struct board_specific_parameters {
> - u32 n_ranks;
> - u32 datarate_mhz_high;
> - u32 rank_gb;
> - u32 clk_adjust;
> - u32 wrlvl_start;
> - u32 wrlvl_ctl_2;
> - u32 wrlvl_ctl_3;
> -};
> -
> -/*
> - * datarate_mhz_high values need to be in ascending order
> - */
> -static const struct board_specific_parameters udimm0[] = {
> - /*
> - * memory controller 0
> - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
> - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
> - */
> - {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
> - {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
> - {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
> - {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
> - {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
> - {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
> - {}
> -};
> -
> -static const struct board_specific_parameters *udimms[] = {
> - udimm0,
> -};
> -
> -void fsl_ddr_board_options(memctl_options_t *popts,
> - dimm_params_t *pdimm,
> - unsigned int ctrl_num)
> -{
> - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
> - ulong ddr_freq;
> - struct cpu_type *cpu = gd->arch.cpu;
> -
> - if (ctrl_num > 1) {
> - printf("Not supported controller number %d\n", ctrl_num);
> - return;
> - }
> - if (!pdimm->n_ranks)
> - return;
> -
> - pbsp = udimms[0];
> -
> - /* Get clk_adjust according to the board ddr freqency and n_banks
> - * specified in board_specific_parameters table.
> - */
> - ddr_freq = get_ddr_freq(0) / 1000000;
> - while (pbsp->datarate_mhz_high) {
> - if (pbsp->n_ranks == pdimm->n_ranks &&
> - (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
> - if (ddr_freq <= pbsp->datarate_mhz_high) {
> - popts->clk_adjust = pbsp->clk_adjust;
> - popts->wrlvl_start = pbsp->wrlvl_start;
> - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> - goto found;
> - }
> - pbsp_highest = pbsp;
> - }
> - pbsp++;
> - }
> -
> - if (pbsp_highest) {
> - printf("Error: board specific timing not found\n");
> - printf("for data rate %lu MT/s\n", ddr_freq);
> - printf("Trying to use the highest speed (%u) parameters\n",
> - pbsp_highest->datarate_mhz_high);
> - popts->clk_adjust = pbsp_highest->clk_adjust;
> - popts->wrlvl_start = pbsp_highest->wrlvl_start;
> - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> - } else {
> - panic("DIMM is not supported by this board");
> - }
> -found:
> - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
> - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
> - debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
> - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
> - debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
> -
> - /*
> - * Factors to consider for half-strength driver enable:
> - * - number of DIMMs installed
> - */
> - popts->half_strength_driver_enable = 0;
> - /*
> - * Write leveling override
> - */
> - popts->wrlvl_override = 1;
> - popts->wrlvl_sample = 0xf;
> -
> - /*
> - * rtt and rtt_wr override
> - */
> - popts->rtt_override = 0;
> -
> - /* Enable ZQ calibration */
> - popts->zq_en = 1;
> -
> - /* DHC_EN =1, ODT = 75 Ohm */
> - popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
> DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
> - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
> -
> - /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
> - * force DDR bus width to 32bit for T1023
> - */
> - if (cpu->soc_ver == SVR_T1023)
> - popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
> -
> -#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
> - /* for DDR bus 32bit test on T1024 */
> - popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
> -#endif
> -
> -#ifdef CONFIG_TARGET_T1023RDB
> - popts->wrlvl_ctl_2 = 0x07070606;
> - popts->half_strength_driver_enable = 1;
> - popts->cpo_sample = 0x43;
> -#elif defined(CONFIG_TARGET_T1024RDB)
> - /* optimize cpo for erratum A-009942 */
> - popts->cpo_sample = 0x52;
> -#endif
> -}
> -
> -#ifdef CONFIG_SYS_DDR_RAW_TIMING
> -/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
> -dimm_params_t ddr_raw_timing = {
> - .n_ranks = 1,
> - .rank_density = 0x80000000,
> - .capacity = 0x80000000,
> - .primary_sdram_width = 32,
> - .ec_sdram_width = 8,
> - .registered_dimm = 0,
> - .mirrored_dimm = 0,
> - .n_row_addr = 15,
> - .n_col_addr = 10,
> - .bank_addr_bits = 2,
> - .bank_group_bits = 2,
> - .edc_config = 0,
> - .burst_lengths_bitmask = 0x0c,
> - .tckmin_x_ps = 938,
> - .tckmax_ps = 1500,
> - .caslat_x = 0x000DFA00,
> - .taa_ps = 13500,
> - .trcd_ps = 13500,
> - .trp_ps = 13500,
> - .tras_ps = 33000,
> - .trc_ps = 46500,
> - .trfc1_ps = 260000,
> - .trfc2_ps = 160000,
> - .trfc4_ps = 110000,
> - .tfaw_ps = 25000,
> - .trrds_ps = 3700,
> - .trrdl_ps = 5300,
> - .tccdl_ps = 5355,
> - .refresh_rate_ps = 7800000,
> - .dq_mapping[0] = 0x0,
> - .dq_mapping[1] = 0x0,
> - .dq_mapping[2] = 0x0,
> - .dq_mapping[3] = 0x0,
> - .dq_mapping[4] = 0x0,
> - .dq_mapping[5] = 0x0,
> - .dq_mapping[6] = 0x0,
> - .dq_mapping[7] = 0x0,
> - .dq_mapping[8] = 0x0,
> - .dq_mapping[9] = 0x0,
> - .dq_mapping[10] = 0x0,
> - .dq_mapping[11] = 0x0,
> - .dq_mapping[12] = 0x0,
> - .dq_mapping[13] = 0x0,
> - .dq_mapping[14] = 0x0,
> - .dq_mapping[15] = 0x0,
> - .dq_mapping[16] = 0x0,
> - .dq_mapping[17] = 0x0,
> - .dq_mapping_ors = 1,
> -};
> -
> -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
> - unsigned int controller_number,
> - unsigned int dimm_number)
> -{
> - const char dimm_model[] = "Fixed DDR4 on board";
> -
> - if (((controller_number == 0) && (dimm_number == 0)) ||
> - ((controller_number == 1) && (dimm_number == 0))) {
> - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
> - memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
> - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
> - }
> -
> - return 0;
> -}
> -#endif
> -
> -#if defined(CONFIG_DEEP_SLEEP)
> -void board_mem_sleep_setup(void)
> -{
> - void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
> -
> - /* does not provide HW signals for power management */
> - clrbits_8(cpld_base + 0x17, 0x40);
> - /* Disable MCKE isolation */
> - gpio_set_value(2, 0);
> - udelay(1);
> -}
> -#endif
> -
> -int dram_init(void)
> -{
> - phys_size_t dram_size;
> -
> -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
> -#ifndef CONFIG_SYS_DDR_RAW_TIMING
> - puts("Initializing....using SPD\n");
> -#endif
> - dram_size = fsl_ddr_sdram();
> -#else
> - /* DDR has been initialised by first stage boot loader */
> - dram_size = fsl_ddr_sdram_size();
> -#endif
> - dram_size = setup_ddr_tlbs(dram_size / 0x100000);
> - dram_size *= 0x100000;
> -
> -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
> - fsl_dp_resume();
> -#endif
> -
> - gd->ram_size = dram_size;
> -
> - return 0;
> -}
> diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c
> b/board/freescale/t102xrdb/eth_t102xrdb.c
> deleted file mode 100644
> index 56e6109288f7..000000000000
> --- a/board/freescale/t102xrdb/eth_t102xrdb.c
> +++ /dev/null
> @@ -1,149 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2014 Freescale Semiconductor, Inc.
> - *
> - * Shengzhou Liu <Shengzhou.Liu at freescale.com>
> - */
> -
> -#include <common.h>
> -#include <command.h>
> -#include <fdt_support.h>
> -#include <net.h>
> -#include <netdev.h>
> -#include <asm/mmu.h>
> -#include <asm/processor.h>
> -#include <asm/immap_85xx.h>
> -#include <asm/fsl_law.h>
> -#include <asm/fsl_serdes.h>
> -#include <asm/fsl_portals.h>
> -#include <asm/fsl_liodn.h>
> -#include <malloc.h>
> -#include <fm_eth.h>
> -#include <fsl_mdio.h>
> -#include <miiphy.h>
> -#include <phy.h>
> -#include <fsl_dtsec.h>
> -#include <asm/fsl_serdes.h>
> -#include "../common/fman.h"
> -
> -int board_eth_init(struct bd_info *bis)
> -{
> -#if defined(CONFIG_FMAN_ENET)
> - int i, interface;
> - struct memac_mdio_info dtsec_mdio_info;
> - struct memac_mdio_info tgec_mdio_info;
> - struct mii_dev *dev;
> - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> - u32 srds_s1;
> -
> - srds_s1 = in_be32(&gur->rcwsr[4]) &
> - FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
> - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
> -
> - dtsec_mdio_info.regs =
> - (struct memac_mdio_controller
> *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
> -
> - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
> -
> - /* Register the 1G MDIO bus */
> - fm_memac_mdio_init(bis, &dtsec_mdio_info);
> -
> - tgec_mdio_info.regs =
> - (struct memac_mdio_controller
> *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
> - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
> -
> - /* Register the 10G MDIO bus */
> - fm_memac_mdio_init(bis, &tgec_mdio_info);
> -
> - /* Set the on-board RGMII PHY address */
> - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
> -
> - switch (srds_s1) {
> -#ifdef CONFIG_TARGET_T1024RDB
> - case 0x95:
> - /* set the on-board RGMII2 PHY */
> - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
> -
> - /* set 10G XFI with Aquantia AQR105 PHY */
> - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
> - break;
> -#endif
> - case 0x6a:
> - case 0x6b:
> - case 0x77:
> - case 0x135:
> - /* set the on-board 2.5G SGMII AQR105 PHY */
> - fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
> -#ifdef CONFIG_TARGET_T1023RDB
> - /* set the on-board 1G SGMII RTL8211F PHY */
> - fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
> -#endif
> - break;
> - default:
> - printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
> - srds_s1);
> - break;
> - }
> -
> - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC;
> i++) {
> - interface = fm_info_get_enet_if(i);
> - switch (interface) {
> - case PHY_INTERFACE_MODE_RGMII:
> - case PHY_INTERFACE_MODE_RGMII_TXID:
> - case PHY_INTERFACE_MODE_RGMII_RXID:
> - case PHY_INTERFACE_MODE_RGMII_ID:
> - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
> - fm_info_set_mdio(i, dev);
> - break;
> - case PHY_INTERFACE_MODE_SGMII:
> -#if defined(CONFIG_TARGET_T1023RDB)
> - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
> -#elif defined(CONFIG_TARGET_T1024RDB)
> - dev =
> miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
> -#endif
> - fm_info_set_mdio(i, dev);
> - break;
> - case PHY_INTERFACE_MODE_SGMII_2500:
> - dev =
> miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
> - fm_info_set_mdio(i, dev);
> - break;
> - default:
> - break;
> - }
> - }
> -
> - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC;
> i++) {
> - switch (fm_info_get_enet_if(i)) {
> - case PHY_INTERFACE_MODE_XGMII:
> - dev =
> miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
> - fm_info_set_mdio(i, dev);
> - break;
> - default:
> - break;
> - }
> - }
> -
> - cpu_eth_init(bis);
> -#endif /* CONFIG_FMAN_ENET */
> -
> - return pci_eth_init(bis);
> -}
> -
> -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
> - enum fm_port port, int offset)
> -{
> -#if defined(CONFIG_TARGET_T1024RDB)
> - if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500)
> ||
> - (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
> - (port == FM1_DTSEC3)) {
> - fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
> - fdt_setprop_string(fdt, offset, "phy-connection-type",
> - "sgmii-2500");
> - fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
> - }
> -#endif
> -}
> -
> -void fdt_fixup_board_enet(void *fdt)
> -{
> -}
> diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c
> deleted file mode 100644
> index 04a4239797c5..000000000000
> --- a/board/freescale/t102xrdb/law.c
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2014 Freescale Semiconductor, Inc.
> - */
> -
> -#include <common.h>
> -#include <asm/fsl_law.h>
> -#include <asm/mmu.h>
> -
> -struct law_entry law_table[] = {
> -#ifdef CONFIG_MTD_NOR_FLASH
> - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M,
> LAW_TRGT_IF_IFC),
> -#endif
> -#ifdef CONFIG_SYS_BMAN_MEM_PHYS
> - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M,
> LAW_TRGT_IF_BMAN),
> -#endif
> -#ifdef CONFIG_SYS_QMAN_MEM_PHYS
> - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M,
> LAW_TRGT_IF_QMAN),
> -#endif
> -#ifdef CONFIG_SYS_CPLD_BASE_PHYS
> - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K,
> LAW_TRGT_IF_IFC),
> -#endif
> -#ifdef CONFIG_SYS_DCSRBAR_PHYS
> - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M,
> LAW_TRGT_IF_DCSR),
> -#endif
> -#ifdef CONFIG_SYS_NAND_BASE_PHYS
> - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K,
> LAW_TRGT_IF_IFC),
> -#endif
> -};
> -
> -int num_law_entries = ARRAY_SIZE(law_table);
> diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c
> deleted file mode 100644
> index 45ab9223ae1f..000000000000
> --- a/board/freescale/t102xrdb/pci.c
> +++ /dev/null
> @@ -1,25 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2007-2014 Freescale Semiconductor, Inc.
> - */
> -
> -#include <common.h>
> -#include <command.h>
> -#include <init.h>
> -#include <pci.h>
> -#include <asm/fsl_pci.h>
> -#include <linux/libfdt.h>
> -#include <fdt_support.h>
> -#include <asm/fsl_serdes.h>
> -
> -#if !defined(CONFIG_DM_PCI)
> -void pci_init_board(void)
> -{
> - fsl_pcie_init_board(0);
> -}
> -
> -void pci_of_setup(void *blob, struct bd_info *bd)
> -{
> - FT_FSL_PCI_SETUP;
> -}
> -#endif
> diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
> deleted file mode 100644
> index 71566851d01d..000000000000
> --- a/board/freescale/t102xrdb/spl.c
> +++ /dev/null
> @@ -1,142 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/* Copyright 2014 Freescale Semiconductor, Inc.
> - */
> -
> -#include <common.h>
> -#include <clock_legacy.h>
> -#include <console.h>
> -#include <env_internal.h>
> -#include <init.h>
> -#include <malloc.h>
> -#include <ns16550.h>
> -#include <nand.h>
> -#include <i2c.h>
> -#include <mmc.h>
> -#include <fsl_esdhc.h>
> -#include <spi_flash.h>
> -#include <asm/global_data.h>
> -#include "../common/sleep.h"
> -#include "../common/spl.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -phys_size_t get_effective_memsize(void)
> -{
> - return CONFIG_SYS_L3_SIZE;
> -}
> -
> -unsigned long get_board_sys_clk(void)
> -{
> - return CONFIG_SYS_CLK_FREQ;
> -}
> -
> -unsigned long get_board_ddr_clk(void)
> -{
> - return CONFIG_DDR_CLK_FREQ;
> -}
> -
> -#if defined(CONFIG_SPL_MMC_BOOT)
> -#define GPIO1_SD_SEL 0x00020000
> -int board_mmc_getcd(struct mmc *mmc)
> -{
> - ccsr_gpio_t __iomem *pgpio = (void
> *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
> - u32 val = in_be32(&pgpio->gpdat);
> -
> - /* GPIO1_14, 0: eMMC, 1: SD */
> - val &= GPIO1_SD_SEL;
> -
> - return val ? -1 : 1;
> -}
> -
> -int board_mmc_getwp(struct mmc *mmc)
> -{
> - ccsr_gpio_t __iomem *pgpio = (void
> *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
> - u32 val = in_be32(&pgpio->gpdat);
> -
> - val &= GPIO1_SD_SEL;
> -
> - return val ? -1 : 0;
> -}
> -#endif
> -
> -void board_init_f(ulong bootflag)
> -{
> - u32 plat_ratio, sys_clk, ccb_clk;
> - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
> -
> - /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
> - memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
> -
> - /* Update GD pointer */
> - gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
> -
> - console_init_f();
> -
> -#ifdef CONFIG_DEEP_SLEEP
> - /* disable the console if boot from deep sleep */
> - if (is_warm_boot())
> - fsl_dp_disable_console();
> -#endif
> -
> - /* initialize selected port with appropriate baud rate */
> - sys_clk = get_board_sys_clk();
> - plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
> - ccb_clk = sys_clk * plat_ratio / 2;
> -
> - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
> - ccb_clk / 16 / CONFIG_BAUDRATE);
> -
> -#if defined(CONFIG_SPL_MMC_BOOT)
> - puts("\nSD boot...\n");
> -#elif defined(CONFIG_SPL_SPI_BOOT)
> - puts("\nSPI boot...\n");
> -#elif defined(CONFIG_SPL_NAND_BOOT)
> - puts("\nNAND boot...\n");
> -#endif
> -
> - relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t
> *)CONFIG_SPL_GD_ADDR, 0x0);
> -}
> -
> -void board_init_r(gd_t *gd, ulong dest_addr)
> -{
> - struct bd_info *bd;
> -
> - bd = (struct bd_info *)(gd + sizeof(gd_t));
> - memset(bd, 0, sizeof(struct bd_info));
> - gd->bd = bd;
> -
> - arch_cpu_init();
> - get_clocks();
> - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
> - CONFIG_SPL_RELOC_MALLOC_SIZE);
> - gd->flags |= GD_FLG_FULL_MALLOC_INIT;
> -
> -#ifdef CONFIG_SPL_NAND_BOOT
> - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
> - (uchar *)SPL_ENV_ADDR);
> -#endif
> -#ifdef CONFIG_SPL_MMC_BOOT
> - mmc_initialize(bd);
> - mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
> - (uchar *)SPL_ENV_ADDR);
> -#endif
> -#ifdef CONFIG_SPL_SPI_BOOT
> - fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
> - (uchar *)SPL_ENV_ADDR);
> -#endif
> -
> - gd->env_addr = (ulong)(SPL_ENV_ADDR);
> - gd->env_valid = ENV_VALID;
> -
> - i2c_init_all();
> -
> - dram_init();
> -
> -#ifdef CONFIG_SPL_MMC_BOOT
> - mmc_boot();
> -#elif defined(CONFIG_SPL_SPI_BOOT)
> - fsl_spi_boot();
> -#elif defined(CONFIG_SPL_NAND_BOOT)
> - nand_boot();
> -#endif
> -}
> diff --git a/board/freescale/t102xrdb/t1023_nand_rcw.cfg
> b/board/freescale/t102xrdb/t1023_nand_rcw.cfg
> deleted file mode 100644
> index f8f72826b16f..000000000000
> --- a/board/freescale/t102xrdb/t1023_nand_rcw.cfg
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#PBL preamble and RCW header for T1023RDB
> -aa55aa55 010e0100
> -#SerDes Protocol: 0x77
> -#Default Core=1200MHz, DDR=1600MT/s with single source clock
> -0810000c 00000000 00000000 00000000
> -3b800003 00000012 e8104000 21000000
> -00000000 00000000 00000000 00022800
> -00000130 04020200 00000000 00000006
> diff --git a/board/freescale/t102xrdb/t1023_sd_rcw.cfg
> b/board/freescale/t102xrdb/t1023_sd_rcw.cfg
> deleted file mode 100644
> index dbf8fba55353..000000000000
> --- a/board/freescale/t102xrdb/t1023_sd_rcw.cfg
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#PBL preamble and RCW header for T1023RDB
> -aa55aa55 010e0100
> -#SerDes Protocol: 0x77
> -#Default Core=1200MHz, DDR=1600MT/s with single source clock
> -0810000c 00000000 00000000 00000000
> -3b800003 00000012 68104000 21000000
> -00000000 00000000 00000000 00022800
> -00000130 04020200 00000000 00000006
> diff --git a/board/freescale/t102xrdb/t1023_spi_rcw.cfg
> b/board/freescale/t102xrdb/t1023_spi_rcw.cfg
> deleted file mode 100644
> index 5edcdb50ea90..000000000000
> --- a/board/freescale/t102xrdb/t1023_spi_rcw.cfg
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#PBL preamble and RCW header for T1023RDB
> -aa55aa55 010e0100
> -#SerDes Protocol: 0x77
> -#Default Core=1200MHz, DDR=1600MT/s with single source clock
> -0810000c 00000000 00000000 00000000
> -3b800003 00000012 58104000 21000000
> -00000000 00000000 00000000 00022800
> -00000130 04020200 00000000 00000006
> diff --git a/board/freescale/t102xrdb/t1024_nand_rcw.cfg
> b/board/freescale/t102xrdb/t1024_nand_rcw.cfg
> deleted file mode 100644
> index cd6f906396eb..000000000000
> --- a/board/freescale/t102xrdb/t1024_nand_rcw.cfg
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#PBL preamble and RCW header for T1024RDB
> -aa55aa55 010e0100
> -#SerDes Protocol: 0x95
> -#Core/DDR: 1400Mhz/1600MT/s with single source clock
> -0810000c 00000000 00000000 00000000
> -4a800003 80000012 ec027000 21000000
> -00000000 00000000 00000000 00030810
> -00000000 0b005a08 00000000 00000006
> diff --git a/board/freescale/t102xrdb/t1024_pbi.cfg
> b/board/freescale/t102xrdb/t1024_pbi.cfg
> deleted file mode 100644
> index 98efca25a290..000000000000
> --- a/board/freescale/t102xrdb/t1024_pbi.cfg
> +++ /dev/null
> @@ -1,26 +0,0 @@
> -#PBI commands
> -#Initialize CPC1
> -09010000 00200400
> -09138000 00000000
> -091380c0 00000100
> -#Configure CPC1 as 256KB SRAM
> -09010100 00000000
> -09010104 fffc0007
> -09010f00 081e000d
> -09010000 80000000
> -#Configure LAW for CPC1
> -09000cd0 00000000
> -09000cd4 fffc0000
> -09000cd8 81000011
> -#Configure alternate space
> -09000010 00000000
> -09000014 ff000000
> -09000018 81000000
> -#Configure SPI controller
> -09110000 80000403
> -09110020 2d170008
> -09110024 00100008
> -09110028 00100008
> -0911002c 00100008
> -#Flush PBL data
> -091380c0 000FFFFF
> diff --git a/board/freescale/t102xrdb/t1024_sd_rcw.cfg
> b/board/freescale/t102xrdb/t1024_sd_rcw.cfg
> deleted file mode 100644
> index 05b3f377636d..000000000000
> --- a/board/freescale/t102xrdb/t1024_sd_rcw.cfg
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#PBL preamble and RCW header for T1024RDB
> -aa55aa55 010e0100
> -#SerDes Protocol: 0x95
> -#Core/DDR: 1400Mhz/1600MT/s with single source clock
> -0810000c 00000000 00000000 00000000
> -4a800003 80000012 6c027000 21000000
> -00000000 00000000 00000000 00030810
> -00000000 0b005a08 00000000 00000006
> diff --git a/board/freescale/t102xrdb/t1024_spi_rcw.cfg
> b/board/freescale/t102xrdb/t1024_spi_rcw.cfg
> deleted file mode 100644
> index 8b695b4ab7bc..000000000000
> --- a/board/freescale/t102xrdb/t1024_spi_rcw.cfg
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#PBL preamble and RCW header for T1024RDB
> -aa55aa55 010e0100
> -#SerDes Protocol: 0x95
> -#Core/DDR: 1400Mhz/1600MT/s with single source clock
> -0810000c 00000000 00000000 00000000
> -4a800003 80000012 5c027000 21000000
> -00000000 00000000 00000000 00030810
> -00000000 0b005a08 00000000 00000006
> diff --git a/board/freescale/t102xrdb/t102xrdb.c
> b/board/freescale/t102xrdb/t102xrdb.c
> deleted file mode 100644
> index 2770e104ee61..000000000000
> --- a/board/freescale/t102xrdb/t102xrdb.c
> +++ /dev/null
> @@ -1,397 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2014 Freescale Semiconductor, Inc.
> - * Copyright 2020 NXP
> - */
> -
> -#include <common.h>
> -#include <command.h>
> -#include <env.h>
> -#include <fdt_support.h>
> -#include <i2c.h>
> -#include <image.h>
> -#include <init.h>
> -#include <netdev.h>
> -#include <asm/global_data.h>
> -#include <linux/compiler.h>
> -#include <asm/mmu.h>
> -#include <asm/processor.h>
> -#include <asm/immap_85xx.h>
> -#include <asm/fsl_law.h>
> -#include <asm/fsl_serdes.h>
> -#include <asm/fsl_liodn.h>
> -#include <fm_eth.h>
> -#include "t102xrdb.h"
> -#ifdef CONFIG_TARGET_T1024RDB
> -#include "cpld.h"
> -#elif defined(CONFIG_TARGET_T1023RDB)
> -#include <i2c.h>
> -#include <mmc.h>
> -#endif
> -#include "../common/sleep.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -#ifdef CONFIG_TARGET_T1023RDB
> -enum {
> - GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
> - GPIO1_EMMC_SEL,
> - GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */
> - GPIO3_BRD_VER_MASK = 0x0c000000,
> - GPIO3_OFFSET = 0x2000,
> - I2C_GET_BANK,
> - I2C_SET_BANK0,
> - I2C_SET_BANK4,
> -};
> -#endif
> -
> -int checkboard(void)
> -{
> - struct cpu_type *cpu = gd->arch.cpu;
> - static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
> - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> - u32 srds_s1;
> -
> - srds_s1 = in_be32(&gur->rcwsr[4]) &
> FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
> - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
> -
> - printf("Board: %sRDB, ", cpu->name);
> -#if defined(CONFIG_TARGET_T1024RDB)
> - printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
> - CPLD_READ(hw_ver), CPLD_READ(sw_ver));
> -#elif defined(CONFIG_TARGET_T1023RDB)
> - printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
> -#endif
> - printf("boot from ");
> -
> -#ifdef CONFIG_SDCARD
> - puts("SD/MMC\n");
> -#elif CONFIG_SPIFLASH
> - puts("SPI\n");
> -#elif defined(CONFIG_TARGET_T1024RDB)
> - u8 reg;
> -
> - reg = CPLD_READ(flash_csr);
> -
> - if (reg & CPLD_BOOT_SEL) {
> - puts("NAND\n");
> - } else {
> - reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
> - printf("NOR vBank%d\n", reg);
> - }
> -#elif defined(CONFIG_TARGET_T1023RDB)
> -#ifdef CONFIG_MTD_RAW_NAND
> - puts("NAND\n");
> -#else
> - printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
> -#endif
> -#endif
> -
> - puts("SERDES Reference Clocks:\n");
> - if (srds_s1 == 0x95)
> - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
> - else
> - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_TARGET_T1024RDB
> -static void board_mux_lane(void)
> -{
> - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> - u32 srds_prtcl_s1;
> - u8 reg = CPLD_READ(misc_ctl_status);
> -
> - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
> - FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
> - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
> -
> - if (srds_prtcl_s1 == 0x95) {
> - /* Route Lane B to PCIE */
> - CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
> - } else {
> - /* Route Lane B to SGMII */
> - CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
> - }
> - CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
> -}
> -#endif
> -
> -int board_early_init_f(void)
> -{
> -#if defined(CONFIG_DEEP_SLEEP)
> - if (is_warm_boot())
> - fsl_dp_disable_console();
> -#endif
> -
> - return 0;
> -}
> -
> -int board_early_init_r(void)
> -{
> -#ifdef CONFIG_SYS_FLASH_BASE
> - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
> - int flash_esel = find_tlb_idx((void *)flashbase, 1);
> - /*
> - * Remap Boot flash region to caching-inhibited
> - * so that flash can be erased properly.
> - */
> -
> - /* Flush d-cache and invalidate i-cache of any FLASH data */
> - flush_dcache();
> - invalidate_icache();
> - if (flash_esel == -1) {
> - /* very unlikely unless something is messed up */
> - puts("Error: Could not find TLB for FLASH BASE\n");
> - flash_esel = 2; /* give our best effort to continue */
> - } else {
> - /* invalidate existing TLB entry for flash + promjet */
> - disable_tlb(flash_esel);
> - }
> -
> - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, flash_esel, BOOKE_PAGESZ_256M, 1);
> -#endif
> -
> -#ifdef CONFIG_TARGET_T1024RDB
> - board_mux_lane();
> -#endif
> -
> - return 0;
> -}
> -
> -unsigned long get_board_sys_clk(void)
> -{
> - return CONFIG_SYS_CLK_FREQ;
> -}
> -
> -unsigned long get_board_ddr_clk(void)
> -{
> - return CONFIG_DDR_CLK_FREQ;
> -}
> -
> -#ifdef CONFIG_TARGET_T1024RDB
> -void board_reset(void)
> -{
> - CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
> -}
> -#endif
> -
> -int misc_init_r(void)
> -{
> - return 0;
> -}
> -
> -int ft_board_setup(void *blob, struct bd_info *bd)
> -{
> - phys_addr_t base;
> - phys_size_t size;
> -
> - ft_cpu_setup(blob, bd);
> -
> - base = env_get_bootm_low();
> - size = env_get_bootm_size();
> -
> - fdt_fixup_memory(blob, (u64)base, (u64)size);
> -
> -#ifdef CONFIG_PCI
> - pci_of_setup(blob, bd);
> -#endif
> -
> - fdt_fixup_liodn(blob);
> - fsl_fdt_fixup_dr_usb(blob, bd);
> -
> -#ifdef CONFIG_SYS_DPAA_FMAN
> -#ifndef CONFIG_DM_ETH
> - fdt_fixup_fman_ethernet(blob);
> -#endif
> - fdt_fixup_board_enet(blob);
> -#endif
> -
> -#ifdef CONFIG_TARGET_T1023RDB
> - if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
> - fdt_enable_nor(blob);
> -#endif
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_TARGET_T1023RDB
> -/* Enable NOR flash for RevC */
> -static void fdt_enable_nor(void *blob)
> -{
> - int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
> -
> - if (nodeoff >= 0)
> - fdt_status_okay(blob, nodeoff);
> - else
> - printf("WARNING unable to set status for NOR\n");
> -}
> -
> -int board_mmc_getcd(struct mmc *mmc)
> -{
> - ccsr_gpio_t __iomem *pgpio = (void
> *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
> - u32 val = in_be32(&pgpio->gpdat);
> -
> - /* GPIO1_14, 0: eMMC, 1: SD/MMC */
> - val &= GPIO1_SD_SEL;
> -
> - return val ? -1 : 1;
> -}
> -
> -int board_mmc_getwp(struct mmc *mmc)
> -{
> - ccsr_gpio_t __iomem *pgpio = (void
> *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
> - u32 val = in_be32(&pgpio->gpdat);
> -
> - val &= GPIO1_SD_SEL;
> -
> - return val ? -1 : 0;
> -}
> -
> -static u32 t1023rdb_ctrl(u32 ctrl_type)
> -{
> - ccsr_gpio_t __iomem *pgpio = (void
> *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
> - ccsr_gur_t __iomem *gur = (void
> *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> - u32 val;
> - u8 tmp;
> - int bus_num = I2C_PCA6408_BUS_NUM;
> -
> -#ifdef CONFIG_DM_I2C
> - struct udevice *dev;
> - int ret;
> -
> - ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR,
> - 1, &dev);
> - if (ret) {
> - printf("%s: Cannot find udev for a bus %d\n", __func__,
> - bus_num);
> - return ret;
> - }
> - switch (ctrl_type) {
> - case GPIO1_SD_SEL:
> - val = in_be32(&pgpio->gpdat);
> - val |= GPIO1_SD_SEL;
> - out_be32(&pgpio->gpdat, val);
> - setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
> - break;
> - case GPIO1_EMMC_SEL:
> - val = in_be32(&pgpio->gpdat);
> - val &= ~GPIO1_SD_SEL;
> - out_be32(&pgpio->gpdat, val);
> - setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
> - break;
> - case GPIO3_GET_VERSION:
> - pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
> - + GPIO3_OFFSET);
> - val = in_be32(&pgpio->gpdat);
> - val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
> - if (val == 0x3) /* GPIO3_4/5 not used on RevB */
> - val = 0;
> - return val;
> - case I2C_GET_BANK:
> - dm_i2c_read(dev, 0, &tmp, 1);
> - tmp &= 0x7;
> - tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
> - return tmp;
> - case I2C_SET_BANK0:
> - tmp = 0x0;
> - dm_i2c_write(dev, 1, &tmp, 1);
> - tmp = 0xf8;
> - dm_i2c_write(dev, 3, &tmp, 1);
> - /* asserting HRESET_REQ */
> - out_be32(&gur->rstcr, 0x2);
> - break;
> - case I2C_SET_BANK4:
> - tmp = 0x1;
> - dm_i2c_write(dev, 1, &tmp, 1);
> - tmp = 0xf8;
> - dm_i2c_write(dev, 3, &tmp, 1);
> - out_be32(&gur->rstcr, 0x2);
> - break;
> - default:
> - break;
> - }
> -#else
> - u32 orig_bus;
> -
> - orig_bus = i2c_get_bus_num();
> -
> - switch (ctrl_type) {
> - case GPIO1_SD_SEL:
> - val = in_be32(&pgpio->gpdat);
> - val |= GPIO1_SD_SEL;
> - out_be32(&pgpio->gpdat, val);
> - setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
> - break;
> - case GPIO1_EMMC_SEL:
> - val = in_be32(&pgpio->gpdat);
> - val &= ~GPIO1_SD_SEL;
> - out_be32(&pgpio->gpdat, val);
> - setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
> - break;
> - case GPIO3_GET_VERSION:
> - pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
> - + GPIO3_OFFSET);
> - val = in_be32(&pgpio->gpdat);
> - val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
> - if (val == 0x3) /* GPIO3_4/5 not used on RevB */
> - val = 0;
> - return val;
> - case I2C_GET_BANK:
> - i2c_set_bus_num(bus_num);
> - i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
> - tmp &= 0x7;
> - tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
> - i2c_set_bus_num(orig_bus);
> - return tmp;
> - case I2C_SET_BANK0:
> - i2c_set_bus_num(bus_num);
> - tmp = 0x0;
> - i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
> - tmp = 0xf8;
> - i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
> - /* asserting HRESET_REQ */
> - out_be32(&gur->rstcr, 0x2);
> - break;
> - case I2C_SET_BANK4:
> - i2c_set_bus_num(bus_num);
> - tmp = 0x1;
> - i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
> - tmp = 0xf8;
> - i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
> - out_be32(&gur->rstcr, 0x2);
> - break;
> - default:
> - break;
> - }
> -#endif
> - return 0;
> -}
> -
> -static int switch_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
> - char *const argv[])
> -{
> - if (argc < 2)
> - return CMD_RET_USAGE;
> - if (!strcmp(argv[1], "bank0"))
> - t1023rdb_ctrl(I2C_SET_BANK0);
> - else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
> - t1023rdb_ctrl(I2C_SET_BANK4);
> - else if (!strcmp(argv[1], "sd"))
> - t1023rdb_ctrl(GPIO1_SD_SEL);
> - else if (!strcmp(argv[1], "emmc"))
> - t1023rdb_ctrl(GPIO1_EMMC_SEL);
> - else
> - return CMD_RET_USAGE;
> - return 0;
> -}
> -
> -U_BOOT_CMD(
> - switch, 2, 0, switch_cmd,
> - "for bank0/bank4/sd/emmc switch control in runtime",
> - "command (e.g. switch bank4)"
> -);
> -#endif
> diff --git a/board/freescale/t102xrdb/t102xrdb.h
> b/board/freescale/t102xrdb/t102xrdb.h
> deleted file mode 100644
> index 33df0f24df8a..000000000000
> --- a/board/freescale/t102xrdb/t102xrdb.h
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright 2014 Freescale Semiconductor, Inc.
> - */
> -
> -#ifndef __T1024_RDB_H__
> -#define __T1024_RDB_H__
> -
> -void fdt_fixup_board_enet(void *blob);
> -void pci_of_setup(void *blob, struct bd_info *bd);
> -#ifdef CONFIG_TARGET_T1023RDB
> -static u32 t1023rdb_ctrl(u32 ctrl_type);
> -static void fdt_enable_nor(void *blob);
> -#endif
> -#endif
> diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c
> deleted file mode 100644
> index 97080eb95e59..000000000000
> --- a/board/freescale/t102xrdb/tlb.c
> +++ /dev/null
> @@ -1,116 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2014 Freescale Semiconductor, Inc.
> - */
> -
> -#include <common.h>
> -#include <asm/mmu.h>
> -
> -struct fsl_e_tlb_entry tlb_table[] = {
> - /* TLB 0 - for temp stack in cache */
> - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
> - CONFIG_SYS_INIT_RAM_ADDR_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, 0,
> - 0, 0, BOOKE_PAGESZ_4K, 0),
> - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
> - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
> - MAS3_SX|MAS3_SW|MAS3_SR, 0,
> - 0, 0, BOOKE_PAGESZ_4K, 0),
> - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
> - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
> - MAS3_SX|MAS3_SW|MAS3_SR, 0,
> - 0, 0, BOOKE_PAGESZ_4K, 0),
> - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
> - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
> - MAS3_SX|MAS3_SW|MAS3_SR, 0,
> - 0, 0, BOOKE_PAGESZ_4K, 0),
> -
> - /* TLB 1 */
> - /* *I*** - Covers boot page */
> -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
> - /*
> - * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
> - * SRAM is at 0xfffc0000, it covered the 0xfffff000.
> - */
> - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR,
> CONFIG_SYS_INIT_L3_ADDR,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 0, BOOKE_PAGESZ_256K, 1),
> -#else
> - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 0, BOOKE_PAGESZ_4K, 1),
> -#endif
> -
> - /* *I*G* - CCSRBAR */
> - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 1, BOOKE_PAGESZ_16M, 1),
> -
> - /* *I*G* - Flash, localbus */
> - /* This will be changed to *I*G* after relocation to RAM. */
> - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE,
> CONFIG_SYS_FLASH_BASE_PHYS,
> - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
> - 0, 2, BOOKE_PAGESZ_256M, 1),
> -
> -#ifndef CONFIG_SPL_BUILD
> - /* *I*G* - PCI */
> - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT,
> CONFIG_SYS_PCIE1_MEM_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 3, BOOKE_PAGESZ_1G, 1),
> -
> - /* *I*G* - PCI I/O */
> - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT,
> CONFIG_SYS_PCIE1_IO_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 4, BOOKE_PAGESZ_256K, 1),
> -
> - /* Bman/Qman */
> -#ifdef CONFIG_SYS_BMAN_MEM_PHYS
> - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE,
> CONFIG_SYS_BMAN_MEM_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, 0,
> - 0, 5, BOOKE_PAGESZ_16M, 1),
> - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
> - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 6, BOOKE_PAGESZ_16M, 1),
> -#endif
> -#ifdef CONFIG_SYS_QMAN_MEM_PHYS
> - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE,
> CONFIG_SYS_QMAN_MEM_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, 0,
> - 0, 7, BOOKE_PAGESZ_16M, 1),
> - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
> - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 8, BOOKE_PAGESZ_16M, 1),
> -#endif
> -#endif
> -#ifdef CONFIG_SYS_DCSRBAR_PHYS
> - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 9, BOOKE_PAGESZ_4M, 1),
> -#endif
> -#ifdef CONFIG_SYS_NAND_BASE
> - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE,
> CONFIG_SYS_NAND_BASE_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 10, BOOKE_PAGESZ_64K, 1),
> -#endif
> -#ifdef CONFIG_SYS_CPLD_BASE
> - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE,
> CONFIG_SYS_CPLD_BASE_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 11, BOOKE_PAGESZ_256K, 1),
> -#endif
> -
> -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
> - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
> CONFIG_SYS_DDR_SDRAM_BASE,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
> - 0, 12, BOOKE_PAGESZ_1G, 1),
> - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
> - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
> - 0, 13, BOOKE_PAGESZ_1G, 1)
> -#endif
> - /* entry 14 and 15 has been used hard coded, they will be disabled
> - * in cpu_init_f, so if needed more, will use entry 16 later.
> - */
> -};
> -
> -int num_tlb_entries = ARRAY_SIZE(tlb_table);
> diff --git a/configs/T1023RDB_NAND_defconfig
> b/configs/T1023RDB_NAND_defconfig
> deleted file mode 100644
> index 0dc1d29c8def..000000000000
> --- a/configs/T1023RDB_NAND_defconfig
> +++ /dev/null
> @@ -1,80 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0x30001000
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_SYS_MEMTEST_START=0x00200000
> -CONFIG_SYS_MEMTEST_END=0x00400000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_OFFSET=0x140000
> -CONFIG_SPL_TEXT_BASE=0xFFFD8000
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> -CONFIG_SPL=y
> -CONFIG_MPC85xx=y
> -CONFIG_TARGET_T1023RDB=y
> -CONFIG_SYS_CUSTOM_LDSCRIPT=y
> -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
> -CONFIG_BOOTDELAY=10
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_BOARD_EARLY_INIT_R=y
> -# CONFIG_SPL_FRAMEWORK is not set
> -CONFIG_SPL_NAND_BOOT=y
> -CONFIG_SPL_FSL_PBL=y
> -CONFIG_SPL_ENV_SUPPORT=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
> -CONFIG_SPL_NAND_SUPPORT=y
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_GREPENV=y
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_SYS_ALT_MEMTEST=y
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_SF=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_DATE=y
> -CONFIG_MP=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_CMD_MTDPARTS=y
> -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0
> =spife110000.1"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),
> 96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_IS_IN_NAND=y
> -CONFIG_FSL_CAAM=y
> -CONFIG_FSL_ESDHC=y
> -CONFIG_MTD=y
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_FLASH_CFI_MTD=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_MTD_RAW_NAND=y
> -CONFIG_SPI_FLASH=y
> -CONFIG_SF_DEFAULT_MODE=0
> -CONFIG_SF_DEFAULT_SPEED=10000000
> -CONFIG_SPI_FLASH_SPANSION=y
> -CONFIG_PHYLIB=y
> -CONFIG_PHY_AQUANTIA=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_E1000=y
> -CONFIG_FMAN_ENET=y
> -CONFIG_MII=y
> -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_FSL_ESPI=y
> -CONFIG_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_ADDR_MAP=y
> -CONFIG_SYS_NUM_ADDR_MAP=64
> -CONFIG_OF_LIBFDT=y
> diff --git a/configs/T1023RDB_SDCARD_defconfig
> b/configs/T1023RDB_SDCARD_defconfig
> deleted file mode 100644
> index 6cf2d6ce409e..000000000000
> --- a/configs/T1023RDB_SDCARD_defconfig
> +++ /dev/null
> @@ -1,77 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0x30001000
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_SYS_MEMTEST_START=0x00200000
> -CONFIG_SYS_MEMTEST_END=0x00400000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_OFFSET=0x100000
> -CONFIG_SPL_TEXT_BASE=0xFFFD8000
> -CONFIG_SPL_MMC_SUPPORT=y
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> -CONFIG_SPL=y
> -CONFIG_MPC85xx=y
> -CONFIG_TARGET_T1023RDB=y
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
> -CONFIG_BOOTDELAY=10
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_BOARD_EARLY_INIT_R=y
> -# CONFIG_SPL_FRAMEWORK is not set
> -CONFIG_SPL_MMC_BOOT=y
> -CONFIG_SPL_FSL_PBL=y
> -CONFIG_SPL_ENV_SUPPORT=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_GREPENV=y
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_SYS_ALT_MEMTEST=y
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_SF=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_DATE=y
> -CONFIG_MP=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_CMD_MTDPARTS=y
> -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0
> =spife110000.1"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),
> 96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_FSL_CAAM=y
> -CONFIG_FSL_ESDHC=y
> -CONFIG_MTD=y
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_FLASH_CFI_MTD=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_SPI_FLASH=y
> -CONFIG_SF_DEFAULT_MODE=0
> -CONFIG_SF_DEFAULT_SPEED=10000000
> -CONFIG_SPI_FLASH_SPANSION=y
> -CONFIG_PHYLIB=y
> -CONFIG_PHY_AQUANTIA=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_E1000=y
> -CONFIG_FMAN_ENET=y
> -CONFIG_MII=y
> -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_FSL_ESPI=y
> -CONFIG_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_ADDR_MAP=y
> -CONFIG_SYS_NUM_ADDR_MAP=64
> -CONFIG_OF_LIBFDT=y
> diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig
> b/configs/T1023RDB_SECURE_BOOT_defconfig
> deleted file mode 100644
> index 8fe44cbcec4f..000000000000
> --- a/configs/T1023RDB_SECURE_BOOT_defconfig
> +++ /dev/null
> @@ -1,67 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xEFF40000
> -CONFIG_SYS_MEMTEST_START=0x00200000
> -CONFIG_SYS_MEMTEST_END=0x00400000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_NXP_ESBC=y
> -CONFIG_MPC85xx=y
> -CONFIG_TARGET_T1023RDB=y
> -# CONFIG_SYS_MALLOC_F is not set
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_BOOTDELAY=10
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_BOARD_EARLY_INIT_R=y
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_GREPENV=y
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_SYS_ALT_MEMTEST=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_SF=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_DATE=y
> -CONFIG_MP=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_CMD_MTDPARTS=y
> -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0
> =spife110000.1"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),
> 96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> -CONFIG_DM=y
> -CONFIG_FSL_ESDHC=y
> -CONFIG_MTD=y
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_FLASH_CFI_MTD=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_SPI_FLASH=y
> -CONFIG_SF_DEFAULT_MODE=0
> -CONFIG_SF_DEFAULT_SPEED=10000000
> -CONFIG_SPI_FLASH_SPANSION=y
> -CONFIG_PHYLIB=y
> -CONFIG_PHY_AQUANTIA=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_E1000=y
> -CONFIG_FMAN_ENET=y
> -CONFIG_MII=y
> -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_FSL_ESPI=y
> -CONFIG_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_ADDR_MAP=y
> -CONFIG_SYS_NUM_ADDR_MAP=64
> -CONFIG_RSA=y
> -CONFIG_SPL_RSA=y
> -CONFIG_RSA_SOFTWARE_EXP=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/configs/T1023RDB_SPIFLASH_defconfig
> b/configs/T1023RDB_SPIFLASH_defconfig
> deleted file mode 100644
> index d9b0cf0535e0..000000000000
> --- a/configs/T1023RDB_SPIFLASH_defconfig
> +++ /dev/null
> @@ -1,79 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0x30001000
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_SYS_MEMTEST_START=0x00200000
> -CONFIG_SYS_MEMTEST_END=0x00400000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_OFFSET=0x100000
> -CONFIG_ENV_SECT_SIZE=0x40000
> -CONFIG_SPL_TEXT_BASE=0xFFFD8000
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> -CONFIG_SPL=y
> -CONFIG_SPL_SPI_FLASH_SUPPORT=y
> -CONFIG_SPL_SPI_SUPPORT=y
> -CONFIG_MPC85xx=y
> -CONFIG_TARGET_T1023RDB=y
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
> -CONFIG_BOOTDELAY=10
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_BOARD_EARLY_INIT_R=y
> -# CONFIG_SPL_FRAMEWORK is not set
> -CONFIG_SPL_SPI_BOOT=y
> -CONFIG_SPL_FSL_PBL=y
> -CONFIG_SPL_ENV_SUPPORT=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_GREPENV=y
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_SYS_ALT_MEMTEST=y
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_SF=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_DATE=y
> -CONFIG_MP=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_CMD_MTDPARTS=y
> -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0
> =spife110000.1"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),
> 96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_IS_IN_SPI_FLASH=y
> -CONFIG_FSL_CAAM=y
> -CONFIG_FSL_ESDHC=y
> -CONFIG_MTD=y
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_FLASH_CFI_MTD=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_SPI_FLASH=y
> -CONFIG_SF_DEFAULT_MODE=0
> -CONFIG_SF_DEFAULT_SPEED=10000000
> -CONFIG_SPI_FLASH_SPANSION=y
> -CONFIG_PHYLIB=y
> -CONFIG_PHY_AQUANTIA=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_E1000=y
> -CONFIG_FMAN_ENET=y
> -CONFIG_MII=y
> -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_FSL_ESPI=y
> -CONFIG_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_ADDR_MAP=y
> -CONFIG_SYS_NUM_ADDR_MAP=64
> -CONFIG_OF_LIBFDT=y
> diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
> deleted file mode 100644
> index 5756db7c4ba3..000000000000
> --- a/configs/T1023RDB_defconfig
> +++ /dev/null
> @@ -1,64 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xEFF40000
> -CONFIG_SYS_MEMTEST_START=0x00200000
> -CONFIG_SYS_MEMTEST_END=0x00400000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_MPC85xx=y
> -CONFIG_TARGET_T1023RDB=y
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_BOOTDELAY=10
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_BOARD_EARLY_INIT_R=y
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_GREPENV=y
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_SYS_ALT_MEMTEST=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_SF=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_DATE=y
> -CONFIG_MP=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_CMD_MTDPARTS=y
> -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0
> =spife110000.1"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),
> 96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_IS_IN_FLASH=y
> -CONFIG_ENV_ADDR=0xEFF20000
> -CONFIG_FSL_CAAM=y
> -CONFIG_FSL_ESDHC=y
> -CONFIG_MTD=y
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_FLASH_CFI_MTD=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_SPI_FLASH=y
> -CONFIG_SF_DEFAULT_MODE=0
> -CONFIG_SF_DEFAULT_SPEED=10000000
> -CONFIG_SPI_FLASH_SPANSION=y
> -CONFIG_PHYLIB=y
> -CONFIG_PHY_AQUANTIA=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_E1000=y
> -CONFIG_FMAN_ENET=y
> -CONFIG_MII=y
> -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_FSL_ESPI=y
> -CONFIG_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_ADDR_MAP=y
> -CONFIG_SYS_NUM_ADDR_MAP=64
> -CONFIG_OF_LIBFDT=y
> diff --git a/configs/T1024RDB_NAND_defconfig
> b/configs/T1024RDB_NAND_defconfig
> deleted file mode 100644
> index f9776ffe5551..000000000000
> --- a/configs/T1024RDB_NAND_defconfig
> +++ /dev/null
> @@ -1,93 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0x30001000
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_SYS_MEMTEST_START=0x00200000
> -CONFIG_SYS_MEMTEST_END=0x00400000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_OFFSET=0x100000
> -CONFIG_SPL_TEXT_BASE=0xFFFD8000
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> -CONFIG_SPL=y
> -CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
> -CONFIG_MPC85xx=y
> -CONFIG_TARGET_T1024RDB=y
> -CONFIG_SYS_CUSTOM_LDSCRIPT=y
> -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
> -CONFIG_BOOTDELAY=10
> -CONFIG_SILENT_CONSOLE=y
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_BOARD_EARLY_INIT_F=y
> -CONFIG_BOARD_EARLY_INIT_R=y
> -# CONFIG_SPL_FRAMEWORK is not set
> -CONFIG_SPL_NAND_BOOT=y
> -CONFIG_SPL_FSL_PBL=y
> -CONFIG_SPL_ENV_SUPPORT=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
> -CONFIG_SPL_NAND_SUPPORT=y
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_GREPENV=y
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_SYS_ALT_MEMTEST=y
> -CONFIG_CMD_DM=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_MP=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0
> =spife110000.1"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),
> 96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
> -CONFIG_OF_CONTROL=y
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_IS_IN_NAND=y
> -CONFIG_DM=y
> -CONFIG_FSL_CAAM=y
> -CONFIG_SYS_FSL_DDR3=y
> -CONFIG_DM_I2C=y
> -CONFIG_DM_MMC=y
> -CONFIG_FSL_ESDHC=y
> -CONFIG_MTD=y
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_FLASH_CFI_MTD=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_MTD_RAW_NAND=y
> -CONFIG_DM_SPI_FLASH=y
> -CONFIG_SF_DEFAULT_MODE=0
> -CONFIG_SF_DEFAULT_SPEED=10000000
> -CONFIG_SPI_FLASH_STMICRO=y
> -CONFIG_PHYLIB=y
> -CONFIG_PHY_AQUANTIA=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_DM_ETH=y
> -CONFIG_DM_MDIO=y
> -CONFIG_E1000=y
> -CONFIG_FMAN_ENET=y
> -CONFIG_MII=y
> -CONFIG_DM_PCI=y
> -CONFIG_DM_PCI_COMPAT=y
> -CONFIG_PCIE_FSL=y
> -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
> -CONFIG_DM_RTC=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_DM_SPI=y
> -CONFIG_FSL_ESPI=y
> -CONFIG_USB=y
> -CONFIG_DM_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_ADDR_MAP=y
> -CONFIG_SYS_NUM_ADDR_MAP=64
> diff --git a/configs/T1024RDB_SDCARD_defconfig
> b/configs/T1024RDB_SDCARD_defconfig
> deleted file mode 100644
> index 529522a52994..000000000000
> --- a/configs/T1024RDB_SDCARD_defconfig
> +++ /dev/null
> @@ -1,90 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0x30001000
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_SYS_MEMTEST_START=0x00200000
> -CONFIG_SYS_MEMTEST_END=0x00400000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_OFFSET=0x100000
> -CONFIG_SPL_TEXT_BASE=0xFFFD8000
> -CONFIG_SPL_MMC_SUPPORT=y
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> -CONFIG_SPL=y
> -CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
> -CONFIG_MPC85xx=y
> -CONFIG_TARGET_T1024RDB=y
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
> -CONFIG_BOOTDELAY=10
> -CONFIG_SILENT_CONSOLE=y
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_BOARD_EARLY_INIT_F=y
> -CONFIG_BOARD_EARLY_INIT_R=y
> -# CONFIG_SPL_FRAMEWORK is not set
> -CONFIG_SPL_MMC_BOOT=y
> -CONFIG_SPL_FSL_PBL=y
> -CONFIG_SPL_ENV_SUPPORT=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_GREPENV=y
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_SYS_ALT_MEMTEST=y
> -CONFIG_CMD_DM=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_MP=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0
> =spife110000.1"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),
> 96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
> -CONFIG_OF_CONTROL=y
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_DM=y
> -CONFIG_FSL_CAAM=y
> -CONFIG_SYS_FSL_DDR3=y
> -CONFIG_DM_I2C=y
> -CONFIG_DM_MMC=y
> -CONFIG_FSL_ESDHC=y
> -CONFIG_MTD=y
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_FLASH_CFI_MTD=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_DM_SPI_FLASH=y
> -CONFIG_SF_DEFAULT_MODE=0
> -CONFIG_SF_DEFAULT_SPEED=10000000
> -CONFIG_SPI_FLASH_STMICRO=y
> -CONFIG_PHYLIB=y
> -CONFIG_PHY_AQUANTIA=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_DM_ETH=y
> -CONFIG_DM_MDIO=y
> -CONFIG_E1000=y
> -CONFIG_FMAN_ENET=y
> -CONFIG_MII=y
> -CONFIG_DM_PCI=y
> -CONFIG_DM_PCI_COMPAT=y
> -CONFIG_PCIE_FSL=y
> -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
> -CONFIG_DM_RTC=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_DM_SPI=y
> -CONFIG_FSL_ESPI=y
> -CONFIG_USB=y
> -CONFIG_DM_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_ADDR_MAP=y
> -CONFIG_SYS_NUM_ADDR_MAP=64
> diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig
> b/configs/T1024RDB_SECURE_BOOT_defconfig
> deleted file mode 100644
> index f33c0022f910..000000000000
> --- a/configs/T1024RDB_SECURE_BOOT_defconfig
> +++ /dev/null
> @@ -1,71 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xEFF40000
> -CONFIG_SYS_MEMTEST_START=0x00200000
> -CONFIG_SYS_MEMTEST_END=0x00400000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_NXP_ESBC=y
> -CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
> -CONFIG_MPC85xx=y
> -CONFIG_TARGET_T1024RDB=y
> -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_BOOTDELAY=10
> -CONFIG_SILENT_CONSOLE=y
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_BOARD_EARLY_INIT_F=y
> -CONFIG_BOARD_EARLY_INIT_R=y
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_GREPENV=y
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_SYS_ALT_MEMTEST=y
> -CONFIG_CMD_DM=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_DATE=y
> -CONFIG_MP=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0
> =spife110000.1"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),
> 96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
> -CONFIG_OF_CONTROL=y
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_DM=y
> -CONFIG_SYS_FSL_DDR3=y
> -CONFIG_FSL_ESDHC=y
> -CONFIG_MTD=y
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_FLASH_CFI_MTD=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_DM_SPI_FLASH=y
> -CONFIG_SF_DEFAULT_MODE=0
> -CONFIG_SF_DEFAULT_SPEED=10000000
> -CONFIG_SPI_FLASH_STMICRO=y
> -CONFIG_PHYLIB=y
> -CONFIG_PHY_AQUANTIA=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_DM_ETH=y
> -CONFIG_DM_MDIO=y
> -CONFIG_FMAN_ENET=y
> -CONFIG_MII=y
> -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_DM_SPI=y
> -CONFIG_FSL_ESPI=y
> -CONFIG_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_ADDR_MAP=y
> -CONFIG_SYS_NUM_ADDR_MAP=64
> -CONFIG_RSA=y
> -CONFIG_SPL_RSA=y
> -CONFIG_RSA_SOFTWARE_EXP=y
> diff --git a/configs/T1024RDB_SPIFLASH_defconfig
> b/configs/T1024RDB_SPIFLASH_defconfig
> deleted file mode 100644
> index fe01675ed04a..000000000000
> --- a/configs/T1024RDB_SPIFLASH_defconfig
> +++ /dev/null
> @@ -1,92 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0x30001000
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_SYS_MEMTEST_START=0x00200000
> -CONFIG_SYS_MEMTEST_END=0x00400000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_OFFSET=0x100000
> -CONFIG_ENV_SECT_SIZE=0x10000
> -CONFIG_SPL_TEXT_BASE=0xFFFD8000
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> -CONFIG_SPL=y
> -CONFIG_SPL_SPI_FLASH_SUPPORT=y
> -CONFIG_SPL_SPI_SUPPORT=y
> -CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
> -CONFIG_MPC85xx=y
> -CONFIG_TARGET_T1024RDB=y
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
> -CONFIG_BOOTDELAY=10
> -CONFIG_SILENT_CONSOLE=y
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_BOARD_EARLY_INIT_F=y
> -CONFIG_BOARD_EARLY_INIT_R=y
> -# CONFIG_SPL_FRAMEWORK is not set
> -CONFIG_SPL_SPI_BOOT=y
> -CONFIG_SPL_FSL_PBL=y
> -CONFIG_SPL_ENV_SUPPORT=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_GREPENV=y
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_SYS_ALT_MEMTEST=y
> -CONFIG_CMD_DM=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_MP=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0
> =spife110000.1"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),
> 96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
> -CONFIG_OF_CONTROL=y
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_IS_IN_SPI_FLASH=y
> -CONFIG_DM=y
> -CONFIG_FSL_CAAM=y
> -CONFIG_SYS_FSL_DDR3=y
> -CONFIG_DM_I2C=y
> -CONFIG_DM_MMC=y
> -CONFIG_FSL_ESDHC=y
> -CONFIG_MTD=y
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_FLASH_CFI_MTD=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_DM_SPI_FLASH=y
> -CONFIG_SF_DEFAULT_MODE=0
> -CONFIG_SF_DEFAULT_SPEED=10000000
> -CONFIG_SPI_FLASH_STMICRO=y
> -CONFIG_PHYLIB=y
> -CONFIG_PHY_AQUANTIA=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_DM_ETH=y
> -CONFIG_DM_MDIO=y
> -CONFIG_E1000=y
> -CONFIG_FMAN_ENET=y
> -CONFIG_MII=y
> -CONFIG_DM_PCI=y
> -CONFIG_DM_PCI_COMPAT=y
> -CONFIG_PCIE_FSL=y
> -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
> -CONFIG_DM_RTC=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_DM_SPI=y
> -CONFIG_FSL_ESPI=y
> -CONFIG_USB=y
> -CONFIG_DM_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_ADDR_MAP=y
> -CONFIG_SYS_NUM_ADDR_MAP=64
> diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
> deleted file mode 100644
> index 4b95136694ab..000000000000
> --- a/configs/T1024RDB_defconfig
> +++ /dev/null
> @@ -1,78 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xEFF40000
> -CONFIG_SYS_MEMTEST_START=0x00200000
> -CONFIG_SYS_MEMTEST_END=0x00400000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
> -CONFIG_MPC85xx=y
> -CONFIG_TARGET_T1024RDB=y
> -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
> -CONFIG_FIT=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_BOOTDELAY=10
> -CONFIG_SILENT_CONSOLE=y
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_BOARD_EARLY_INIT_F=y
> -CONFIG_BOARD_EARLY_INIT_R=y
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_GREPENV=y
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_SYS_ALT_MEMTEST=y
> -CONFIG_CMD_DM=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_MP=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0
> =spife110000.1"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),
> 96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
> -CONFIG_OF_CONTROL=y
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_IS_IN_FLASH=y
> -CONFIG_ENV_ADDR=0xEFF20000
> -CONFIG_DM=y
> -CONFIG_FSL_CAAM=y
> -CONFIG_SYS_FSL_DDR3=y
> -CONFIG_DM_I2C=y
> -CONFIG_DM_MMC=y
> -CONFIG_FSL_ESDHC=y
> -CONFIG_MTD=y
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_FLASH_CFI_MTD=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_DM_SPI_FLASH=y
> -CONFIG_SF_DEFAULT_MODE=0
> -CONFIG_SF_DEFAULT_SPEED=10000000
> -CONFIG_SPI_FLASH_STMICRO=y
> -CONFIG_PHYLIB=y
> -CONFIG_PHY_AQUANTIA=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_DM_ETH=y
> -CONFIG_DM_MDIO=y
> -CONFIG_E1000=y
> -CONFIG_FMAN_ENET=y
> -CONFIG_MII=y
> -CONFIG_DM_PCI=y
> -CONFIG_DM_PCI_COMPAT=y
> -CONFIG_PCIE_FSL=y
> -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
> -CONFIG_DM_RTC=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_DM_SPI=y
> -CONFIG_FSL_ESPI=y
> -CONFIG_USB=y
> -CONFIG_DM_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_ADDR_MAP=y
> -CONFIG_SYS_NUM_ADDR_MAP=64
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 63d81fc14561..4ff35c4df591 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -708,7 +708,6 @@ config SYS_DPAA_QBMAN
> ARCH_B4420 || \
> ARCH_P1023 || \
> ARCH_P2041 || \
> - ARCH_T1023 || \
> ARCH_T1024 || \
> ARCH_T1040 || \
> ARCH_T1042 || \
> diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
> index b4ede61113fc..c988e4e9257f 100644
> --- a/drivers/net/fm/Makefile
> +++ b/drivers/net/fm/Makefile
> @@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_P4080) += p4080.o
> obj-$(CONFIG_ARCH_P5040) += p5040.o
> obj-$(CONFIG_ARCH_T1040) += t1040.o
> obj-$(CONFIG_ARCH_T1042) += t1040.o
> -obj-$(CONFIG_ARCH_T1023) += t1024.o
> obj-$(CONFIG_ARCH_T1024) += t1024.o
> obj-$(CONFIG_ARCH_T2080) += t2080.o
> obj-$(CONFIG_ARCH_T4240) += t4240.o
> diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
> deleted file mode 100644
> index 201da871bdb3..000000000000
> --- a/include/configs/T102xRDB.h
> +++ /dev/null
> @@ -1,709 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright 2014 Freescale Semiconductor, Inc.
> - * Copyright 2020 NXP
> - */
> -
> -/*
> - * T1024/T1023 RDB board configuration file
> - */
> -
> -#ifndef __T1024RDB_H
> -#define __T1024RDB_H
> -
> -#include <linux/stringify.h>
> -
> -/* High Level Configuration Options */
> -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
> -#define CONFIG_ENABLE_36BIT_PHYS
> -
> -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
> -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
> -
> -/* support deep sleep */
> -#ifdef CONFIG_ARCH_T1024
> -#define CONFIG_DEEP_SLEEP
> -#endif
> -
> -#ifdef CONFIG_RAMBOOT_PBL
> -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
> -#define CONFIG_SPL_FLUSH_IMAGE
> -#define CONFIG_SPL_PAD_TO 0x40000
> -#define CONFIG_SPL_MAX_SIZE 0x28000
> -#define RESET_VECTOR_OFFSET 0x27FFC
> -#define BOOT_PAGE_OFFSET 0x27000
> -#ifdef CONFIG_SPL_BUILD
> -#define CONFIG_SPL_SKIP_RELOCATE
> -#define CONFIG_SPL_COMMON_INIT_DDR
> -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
> -#endif
> -
> -#ifdef CONFIG_MTD_RAW_NAND
> -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
> -#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
> -#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
> -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
> -#if defined(CONFIG_TARGET_T1024RDB)
> -#define CONFIG_SYS_FSL_PBL_RCW
> board/freescale/t102xrdb/t1024_nand_rcw.cfg
> -#elif defined(CONFIG_TARGET_T1023RDB)
> -#define CONFIG_SYS_FSL_PBL_RCW
> board/freescale/t102xrdb/t1023_nand_rcw.cfg
> -#endif
> -#endif
> -
> -#ifdef CONFIG_SPIFLASH
> -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
> -#define CONFIG_SPL_SPI_FLASH_MINIMAL
> -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
> -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
> -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
> -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
> -#ifndef CONFIG_SPL_BUILD
> -#define CONFIG_SYS_MPC85XX_NO_RESETVEC
> -#endif
> -#if defined(CONFIG_TARGET_T1024RDB)
> -#define CONFIG_SYS_FSL_PBL_RCW
> board/freescale/t102xrdb/t1024_spi_rcw.cfg
> -#elif defined(CONFIG_TARGET_T1023RDB)
> -#define CONFIG_SYS_FSL_PBL_RCW
> board/freescale/t102xrdb/t1023_spi_rcw.cfg
> -#endif
> -#endif
> -
> -#ifdef CONFIG_SDCARD
> -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
> -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
> -#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
> -#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
> -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
> -#ifndef CONFIG_SPL_BUILD
> -#define CONFIG_SYS_MPC85XX_NO_RESETVEC
> -#endif
> -#if defined(CONFIG_TARGET_T1024RDB)
> -#define CONFIG_SYS_FSL_PBL_RCW
> board/freescale/t102xrdb/t1024_sd_rcw.cfg
> -#elif defined(CONFIG_TARGET_T1023RDB)
> -#define CONFIG_SYS_FSL_PBL_RCW
> board/freescale/t102xrdb/t1023_sd_rcw.cfg
> -#endif
> -#endif
> -
> -#endif /* CONFIG_RAMBOOT_PBL */
> -
> -#ifndef CONFIG_RESET_VECTOR_ADDRESS
> -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
> -#endif
> -
> -/* PCIe Boot - Master */
> -#define CONFIG_SRIO_PCIE_BOOT_MASTER
> -/*
> - * for slave u-boot IMAGE instored in master memory space,
> - * PHYS must be aligned based on the SIZE
> - */
> -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
> -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
> -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
> -#else
> -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
> -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
> -#endif
> -/*
> - * for slave UCODE and ENV instored in master memory space,
> - * PHYS must be aligned based on the SIZE
> - */
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
> -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS
> 0x3ffe00000ull
> -#else
> -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
> -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
> -#endif
> -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
> -/* slave core release by master*/
> -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
> -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release
> core 0 */
> -
> -/* PCIe Boot - Slave */
> -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
> -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
> -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
> - (0x300000000ull |
> CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
> -/* Set 1M boot space for PCIe boot */
> -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR
> (CONFIG_SYS_TEXT_BASE & 0xfff00000)
> -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
> - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
> -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
> -#endif
> -
> -#ifndef __ASSEMBLY__
> -unsigned long get_board_sys_clk(void);
> -unsigned long get_board_ddr_clk(void);
> -#endif
> -
> -#define CONFIG_SYS_CLK_FREQ 100000000
> -#define CONFIG_DDR_CLK_FREQ 100000000
> -
> -/*
> - * These can be toggled for performance analysis, otherwise use default.
> - */
> -#define CONFIG_SYS_CACHE_STASHING
> -#define CONFIG_BACKSIDE_L2_CACHE
> -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
> -#define CONFIG_BTB /* toggle branch predition */
> -#define CONFIG_DDR_ECC
> -#ifdef CONFIG_DDR_ECC
> -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
> -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
> -#endif
> -
> -/*
> - * Config the L3 Cache as L3 SRAM
> - */
> -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
> -#define CONFIG_SYS_L3_SIZE (256 << 10)
> -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 *
> 1024)
> -#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
> -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12
> * 1024)
> -#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
> -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 *
> 1024)
> -
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_DCSRBAR 0xf0000000
> -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
> -#endif
> -
> -/* EEPROM */
> -#define CONFIG_ID_EEPROM
> -#define CONFIG_SYS_I2C_EEPROM_NXID
> -#define CONFIG_SYS_EEPROM_BUS_NUM 0
> -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
> -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
> -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
> -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
> -
> -/*
> - * DDR Setup
> - */
> -#define CONFIG_VERY_BIG_RAM
> -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
> -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
> -#define CONFIG_DIMM_SLOTS_PER_CTLR 1
> -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 *
> CONFIG_DIMM_SLOTS_PER_CTLR)
> -#if defined(CONFIG_TARGET_T1024RDB)
> -#define CONFIG_DDR_SPD
> -#define CONFIG_SYS_SPD_BUS_NUM 0
> -#define SPD_EEPROM_ADDRESS 0x51
> -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
> -#elif defined(CONFIG_TARGET_T1023RDB)
> -#define CONFIG_SYS_DDR_RAW_TIMING
> -#define CONFIG_SYS_SDRAM_SIZE 2048
> -#endif
> -
> -/*
> - * IFC Definitions
> - */
> -#define CONFIG_SYS_FLASH_BASE 0xe8000000
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull |
> CONFIG_SYS_FLASH_BASE)
> -#else
> -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
> -#endif
> -
> -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
> -#define CONFIG_SYS_NOR0_CSPR
> (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
> - CSPR_PORT_SIZE_16 | \
> - CSPR_MSEL_NOR | \
> - CSPR_V)
> -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
> -
> -/* NOR Flash Timing Params */
> -#if defined(CONFIG_TARGET_T1024RDB)
> -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
> -#elif defined(CONFIG_TARGET_T1023RDB)
> -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
> - CSOR_NAND_TRHZ_80 |
> CSOR_NOR_ADM_SHFT_MODE_EN)
> -#endif
> -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
> - FTIM0_NOR_TEADC(0x5) | \
> - FTIM0_NOR_TEAHC(0x5))
> -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
> - FTIM1_NOR_TRAD_NOR(0x1A) |\
> - FTIM1_NOR_TSEQRAD_NOR(0x13))
> -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
> - FTIM2_NOR_TCH(0x4) | \
> - FTIM2_NOR_TWPH(0x0E) | \
> - FTIM2_NOR_TWP(0x1c))
> -#define CONFIG_SYS_NOR_FTIM3 0x0
> -
> -#define CONFIG_SYS_FLASH_QUIET_TEST
> -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1
> */
> -
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
> -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout
> (ms) */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms)
> */
> -
> -#define CONFIG_SYS_FLASH_EMPTY_INFO
> -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
> -
> -#ifdef CONFIG_TARGET_T1024RDB
> -/* CPLD on IFC */
> -#define CONFIG_SYS_CPLD_BASE 0xffdf0000
> -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull |
> CONFIG_SYS_CPLD_BASE)
> -#define CONFIG_SYS_CSPR2_EXT (0xf)
> -#define CONFIG_SYS_CSPR2
> (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
> - | CSPR_PORT_SIZE_8 \
> - | CSPR_MSEL_GPCM \
> - | CSPR_V)
> -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
> -#define CONFIG_SYS_CSOR2 0x0
> -
> -/* CPLD Timing parameters for IFC CS2 */
> -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
> - FTIM0_GPCM_TEADC(0x0e) | \
> - FTIM0_GPCM_TEAHC(0x0e))
> -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
> - FTIM1_GPCM_TRAD(0x1f))
> -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
> - FTIM2_GPCM_TCH(0x8) | \
> - FTIM2_GPCM_TWP(0x1f))
> -#define CONFIG_SYS_CS2_FTIM3 0x0
> -#endif
> -
> -/* NAND Flash on IFC */
> -#define CONFIG_NAND_FSL_IFC
> -#define CONFIG_SYS_NAND_BASE 0xff800000
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull |
> CONFIG_SYS_NAND_BASE)
> -#else
> -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
> -#endif
> -#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
> -#define CONFIG_SYS_NAND_CSPR
> (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
> - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
> - | CSPR_MSEL_NAND /* MSEL = NAND */ \
> - | CSPR_V)
> -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
> -
> -#if defined(CONFIG_TARGET_T1024RDB)
> -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on
> encode */ \
> - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
> - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
> - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
> - | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
> - | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
> - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
> -#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
> -#elif defined(CONFIG_TARGET_T1023RDB)
> -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC
> on encode */ \
> - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
> - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
> - | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
> - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
> - | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
> - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
> -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
> -#endif
> -
> -#define CONFIG_SYS_NAND_ONFI_DETECTION
> -/* ONFI NAND Flash mode0 Timing Params */
> -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
> - FTIM0_NAND_TWP(0x18) | \
> - FTIM0_NAND_TWCHT(0x07) | \
> - FTIM0_NAND_TWH(0x0a))
> -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
> - FTIM1_NAND_TWBE(0x39) | \
> - FTIM1_NAND_TRR(0x0e) | \
> - FTIM1_NAND_TRP(0x18))
> -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
> - FTIM2_NAND_TREH(0x0a) | \
> - FTIM2_NAND_TWHRE(0x1e))
> -#define CONFIG_SYS_NAND_FTIM3 0x0
> -
> -#define CONFIG_SYS_NAND_DDR_LAW 11
> -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
> -#define CONFIG_SYS_MAX_NAND_DEVICE 1
> -
> -#if defined(CONFIG_MTD_RAW_NAND)
> -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
> -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
> -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
> -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
> -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
> -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
> -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
> -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
> -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
> -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
> -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
> -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
> -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
> -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
> -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
> -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
> -#else
> -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
> -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
> -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
> -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
> -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
> -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
> -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
> -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
> -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
> -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
> -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
> -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
> -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
> -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
> -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
> -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
> -#endif
> -
> -#ifdef CONFIG_SPL_BUILD
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
> -#else
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> -#endif
> -
> -#if defined(CONFIG_RAMBOOT_PBL)
> -#define CONFIG_SYS_RAMBOOT
> -#endif
> -
> -#define CONFIG_HWCONFIG
> -
> -/* define to use L1 as initial stack */
> -#define CONFIG_L1_INIT_RAM
> -#define CONFIG_SYS_INIT_RAM_LOCK
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address
> */
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
> -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
> -/* The assembler doesn't like typecast */
> -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
> - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
> - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
> -#else
> -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1
> address */
> -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
> -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW
> CONFIG_SYS_INIT_RAM_ADDR_PHYS
> -#endif
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
> -
> -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
> - GENERATED_GBL_DATA_SIZE)
> -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
> -
> -#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
> -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
> -
> -/* Serial Port */
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
> -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
> -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
> -
> -/* Video */
> -#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
> -#ifdef CONFIG_FSL_DIU_FB
> -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
> -#define CONFIG_VIDEO_LOGO
> -#define CONFIG_VIDEO_BMP_LOGO
> -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
> -/*
> - * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow,
> so
> - * disable empty flash sector detection, which is I/O-intensive.
> - */
> -#undef CONFIG_SYS_FLASH_EMPTY_INFO
> -#endif
> -
> -/* I2C */
> -#ifndef CONFIG_DM_I2C
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
> -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
> -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
> -#else
> -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
> -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
> -#endif
> -
> -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
> -#define I2C_PCA6408_BUS_NUM 1
> -#define I2C_PCA6408_ADDR 0x20
> -
> -/* I2C bus multiplexer */
> -#define I2C_MUX_CH_DEFAULT 0x8
> -
> -/*
> - * RTC configuration
> - */
> -#define RTC
> -#define CONFIG_RTC_DS1337 1
> -#define CONFIG_SYS_I2C_RTC_ADDR 0x68
> -
> -/*
> - * eSPI - Enhanced SPI
> - */
> -
> -/*
> - * General PCIe
> - * Memory space is mapped 1-1, but I/O space must start from 0.
> - */
> -#define CONFIG_PCIE1 /* PCIE controller 1 */
> -#define CONFIG_PCIE2 /* PCIE controller 2 */
> -#define CONFIG_PCIE3 /* PCIE controller 3 */
> -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
> -
> -#ifdef CONFIG_PCI
> -/* controller 1, direct to uli, tgtid 3, Base address 20000 */
> -#ifdef CONFIG_PCIE1
> -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
> -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
> -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
> -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
> -#endif
> -
> -/* controller 2, Slot 2, tgtid 2, Base address 201000 */
> -#ifdef CONFIG_PCIE2
> -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
> -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
> -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
> -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
> -#endif
> -
> -/* controller 3, Slot 1, tgtid 1, Base address 202000 */
> -#ifdef CONFIG_PCIE3
> -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
> -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
> -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
> -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
> -#endif
> -
> -#if !defined(CONFIG_DM_PCI)
> -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
> -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
> -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
> -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
> -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
> -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
> -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
> -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
> -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
> -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
> -#define CONFIG_PCI_INDIRECT_BRIDGE
> -#endif
> -
> -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -#endif /* CONFIG_PCI */
> -
> -/*
> - * USB
> - */
> -#define CONFIG_HAS_FSL_DR_USB
> -
> -#ifdef CONFIG_HAS_FSL_DR_USB
> -#define CONFIG_USB_EHCI_FSL
> -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> -#endif
> -
> -/*
> - * SDHC
> - */
> -#ifdef CONFIG_MMC
> -#define CONFIG_SYS_FSL_ESDHC_ADDR
> CONFIG_SYS_MPC85xx_ESDHC_ADDR
> -#endif
> -
> -/* Qman/Bman */
> -#ifndef CONFIG_NOBQFMAN
> -#define CONFIG_SYS_BMAN_NUM_PORTALS 10
> -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
> -#else
> -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
> -#endif
> -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
> -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
> -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
> -#define CONFIG_SYS_BMAN_CENA_BASE
> CONFIG_SYS_BMAN_MEM_BASE
> -#define CONFIG_SYS_BMAN_CENA_SIZE
> (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
> -#define CONFIG_SYS_BMAN_CINH_BASE
> (CONFIG_SYS_BMAN_MEM_BASE + \
> - CONFIG_SYS_BMAN_CENA_SIZE)
> -#define CONFIG_SYS_BMAN_CINH_SIZE
> (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
> -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
> -#define CONFIG_SYS_QMAN_NUM_PORTALS 10
> -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
> -#else
> -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
> -#endif
> -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
> -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
> -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
> -#define CONFIG_SYS_QMAN_CENA_BASE
> CONFIG_SYS_QMAN_MEM_BASE
> -#define CONFIG_SYS_QMAN_CENA_SIZE
> (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
> -#define CONFIG_SYS_QMAN_CINH_BASE
> (CONFIG_SYS_QMAN_MEM_BASE + \
> - CONFIG_SYS_QMAN_CENA_SIZE)
> -#define CONFIG_SYS_QMAN_CINH_SIZE
> (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
> -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
> -
> -#define CONFIG_SYS_DPAA_FMAN
> -
> -/* Default address of microcode for the Linux FMan driver */
> -#if defined(CONFIG_SPIFLASH)
> -/*
> - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
> - * env, so we got 0x110000.
> - */
> -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
> -#define CONFIG_SYS_QE_FW_ADDR 0x130000
> -#elif defined(CONFIG_SDCARD)
> -/*
> - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image
> is
> - * about 1MB (2048 blocks), Env is stored after the image, and the env size is
> - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
> - */
> -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
> -#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
> -#elif defined(CONFIG_MTD_RAW_NAND)
> -#if defined(CONFIG_TARGET_T1024RDB)
> -#define CONFIG_SYS_FMAN_FW_ADDR (3 *
> CONFIG_SYS_NAND_BLOCK_SIZE)
> -#define CONFIG_SYS_QE_FW_ADDR (4 *
> CONFIG_SYS_NAND_BLOCK_SIZE)
> -#elif defined(CONFIG_TARGET_T1023RDB)
> -#define CONFIG_SYS_FMAN_FW_ADDR (11 *
> CONFIG_SYS_NAND_BLOCK_SIZE)
> -#define CONFIG_SYS_QE_FW_ADDR (12 *
> CONFIG_SYS_NAND_BLOCK_SIZE)
> -#endif
> -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
> -/*
> - * Slave has no ucode locally, it can fetch this from remote. When
> implementing
> - * in two corenet boards, slave's ucode could be stored in master's memory
> - * space, the address can be mapped from slave TLB->slave LAW->
> - * slave SRIO or PCIE outbound window->master inbound window->
> - * master LAW->the ucode address in master's memory space.
> - */
> -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
> -#else
> -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
> -#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
> -#endif
> -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
> -#define CONFIG_SYS_FDT_PAD (0x3000 +
> CONFIG_SYS_QE_FMAN_FW_LENGTH)
> -#endif /* CONFIG_NOBQFMAN */
> -
> -#ifdef CONFIG_SYS_DPAA_FMAN
> -#if defined(CONFIG_TARGET_T1024RDB)
> -#define RGMII_PHY1_ADDR 0x2
> -#define RGMII_PHY2_ADDR 0x6
> -#define SGMII_AQR_PHY_ADDR 0x2
> -#define FM1_10GEC1_PHY_ADDR 0x1
> -#elif defined(CONFIG_TARGET_T1023RDB)
> -#define RGMII_PHY1_ADDR 0x1
> -#define SGMII_RTK_PHY_ADDR 0x3
> -#define SGMII_AQR_PHY_ADDR 0x2
> -#endif
> -#endif
> -
> -#ifdef CONFIG_FMAN_ENET
> -#define CONFIG_ETHPRIME "FM1 at DTSEC4"
> -#endif
> -
> -/*
> - * Dynamic MTD Partition support with mtdparts
> - */
> -
> -/*
> - * Environment
> - */
> -#define CONFIG_LOADS_ECHO /* echo on for serial download */
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address
> */
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 64 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
> -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip
> size */
> -
> -#ifdef CONFIG_CMD_KGDB
> -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial
> port */
> -#endif
> -
> -/*
> - * Environment Configuration
> - */
> -#define CONFIG_ROOTPATH "/opt/nfsroot"
> -#define CONFIG_BOOTFILE "uImage"
> -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server
> */
> -#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm
> */
> -#define __USB_PHY_TYPE utmi
> -
> -#ifdef CONFIG_ARCH_T1024
> -#define CONFIG_BOARDNAME t1024rdb
> -#define BANK_INTLV cs0_cs1
> -#else
> -#define CONFIG_BOARDNAME t1023rdb
> -#define BANK_INTLV null
> -#endif
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
> - "bank_intlv=" __stringify(BANK_INTLV) "\0" \
> - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
> - "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
> - "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
> - __stringify(CONFIG_BOARDNAME) ".dtb\0" \
> - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
> - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
> - "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
> - "netdev=eth0\0" \
> - "tftpflash=tftpboot $loadaddr $uboot && " \
> - "protect off $ubootaddr +$filesize && " \
> - "erase $ubootaddr +$filesize && " \
> - "cp.b $loadaddr $ubootaddr $filesize && " \
> - "protect on $ubootaddr +$filesize && " \
> - "cmp.b $loadaddr $ubootaddr $filesize\0" \
> - "consoledev=ttyS0\0" \
> - "ramdiskaddr=2000000\0" \
> - "fdtaddr=1e00000\0" \
> - "bdev=sda3\0"
> -
> -#define CONFIG_LINUX \
> - "setenv bootargs root=/dev/ram rw " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "setenv ramdiskaddr 0x02000000;" \
> - "setenv fdtaddr 0x00c00000;" \
> - "setenv loadaddr 0x1000000;" \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr"
> -
> -#define CONFIG_NFSBOOTCOMMAND \
> - "setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=$serverip:$rootpath " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr - $fdtaddr"
> -
> -#define CONFIG_BOOTCOMMAND CONFIG_LINUX
> -
> -#include <asm/fsl_secure_boot.h>
> -
> -#endif /* __T1024RDB_H */
> --
> 2.17.1
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