[PATCH V2] net: dwc_eth_qos: Pad descriptors to cacheline size

Stephen Warren swarren at wwwdotorg.org
Wed Jan 6 22:49:22 CET 2021

On 1/6/21 2:10 PM, Marek Vasut wrote:
> On 1/6/21 10:06 PM, Stephen Warren wrote:
> [...]
>>>>> diff --git a/include/configs/tegra-common-post.h
>>>>> b/include/configs/tegra-common-post.h
>>>>> -#define CONFIG_SYS_NONCACHED_MEMORY    (1 << 20)    /* 1 MiB */
>>>> This is wrong; there are other devices that are used on Tegra that
>>>> require the noncached memory pool, e.g. the r8169 device.
>>> Isn't r8169 PCI device ? Shouldn't the r8169 driver be fixed instead ?
>> IIRC, the r8169 hardware doesn't have the same descriptor stride
>> capability that the EQoS hardware does, so it isn't possible to fix that
>> driver. Thierry Reding may remember more details since IIRC he worked on
>> adding the noncached support to the r8169 driver; see d58acdcbfb33 "net:
>> rtl8169: Use non-cached memory if available".
> But rtl8169 is PCI device, should that even be affected at all ?

The CPU cache needs to be consistent with the accesses performed by the
PCIe device. At least on Tegra (and in general on ARM IIUC), PCIe isn't
cache-coherent with CPU caches (although IIRC on x86 it is, which is
probably what led to the r8169 HW design, where cache line size wasn't
taken into account). So, on ARM the CPU needs to do a bunch of cache
invalidate/flush operations to make this happen, irrespective of whether
the relevant device is built-in, PCIe, or whatever.

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