[PATCH V3] net: dwc_eth_qos: Pad descriptors to cacheline size

Patrice CHOTARD patrice.chotard at foss.st.com
Fri Jan 8 09:01:16 CET 2021

Hi Marek

On 1/7/21 7:16 PM, Marek Vasut wrote:
> On 1/7/21 5:33 PM, Stephen Warren wrote:
>> On 1/7/21 3:12 AM, Marek Vasut wrote:
>>> The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
>>> after the descriptor. Use this to pad the descriptors to cacheline size and
>>> remove the need for noncached memory altogether. Moreover, this lets Tegra
>>> use the generic cache flush / invalidate operations.
>> Tested-by: Stephen Warren <swarren at nvidia.com>
>> Reviewed-by: Stephen Warren <swarren at nvidia.com>
> Thanks.
> This also really needs a TB/RB from ST before this is applied.

Tested-by: Patrice Chotard <patrice.chotard at foss.st.com>

Tested on a stm32mp157c-ev1 board



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