[PATCH V3] net: dwc_eth_qos: Pad descriptors to cacheline size

Tom Rini trini at konsulko.com
Tue Jan 19 21:01:32 CET 2021

On Thu, Jan 07, 2021 at 11:12:16AM +0100, Marek Vasut wrote:

> The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
> after the descriptor. Use this to pad the descriptors to cacheline size and
> remove the need for noncached memory altogether. Moreover, this lets Tegra
> use the generic cache flush / invalidate operations.
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Joe Hershberger <joe.hershberger at ni.com>
> Cc: Patrice Chotard <patrice.chotard at st.com>
> Cc: Patrick Delaunay <patrick.delaunay at st.com>
> Cc: Ramon Fried <rfried.dev at gmail.com>
> Cc: Stephen Warren <swarren at nvidia.com>
> Tested-by: Stephen Warren <swarren at nvidia.com>
> Reviewed-by: Stephen Warren <swarren at nvidia.com>
> Tested-by: Patrice Chotard <patrice.chotard at foss.st.com>

Applied to u-boot/master, thanks!

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