[PATCH 8/9] arm: dts: imx8mm-venice-gw7901.dts: fix dsa switch configuration

Tim Harvey tharvey at gateworks.com
Thu Jul 1 01:50:09 CEST 2021


Fix the dsa switch config:
- remove the unnecessary phy-mode from the switch itself
- added the necessary fixed-link node to the non-cpu ports required
  for U-Boot DSA

Signed-off-by: Tim Harvey <tharvey at gateworks.com>
---
 arch/arm/dts/imx8mm-venice-gw7901.dts | 37 ++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts
index 0216facb2a..124e1e4e70 100644
--- a/arch/arm/dts/imx8mm-venice-gw7901.dts
+++ b/arch/arm/dts/imx8mm-venice-gw7901.dts
@@ -577,7 +577,6 @@
 		pinctrl-0 = <&pinctrl_ksz>;
 		interrupt-parent = <&gpio4>;
 		interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
-		phy-mode = "rgmii-id";
 
 		ports {
 			#address-cells = <1>;
@@ -587,24 +586,32 @@
 				reg = <0>;
 				label = "lan1";
 				local-mac-address = [00 00 00 00 00 00];
+				phy-handle = <&sw_phy0>;
+				phy-mode = "internal";
 			};
 
 			lan2: port at 1 {
 				reg = <1>;
 				label = "lan2";
 				local-mac-address = [00 00 00 00 00 00];
+				phy-handle = <&sw_phy1>;
+				phy-mode = "internal";
 			};
 
 			lan3: port at 2 {
 				reg = <2>;
 				label = "lan3";
 				local-mac-address = [00 00 00 00 00 00];
+				phy-handle = <&sw_phy2>;
+				phy-mode = "internal";
 			};
 
 			lan4: port at 3 {
 				reg = <3>;
 				label = "lan4";
 				local-mac-address = [00 00 00 00 00 00];
+				phy-handle = <&sw_phy3>;
+				phy-mode = "internal";
 			};
 
 			port at 5 {
@@ -619,6 +626,34 @@
 				};
 			};
 		};
+
+		mdios {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mdio at 0 {
+				reg = <0>;
+				compatible = "microchip,ksz-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sw_phy0: ethernet-phy at 0 {
+					reg = <0x0>;
+				};
+
+				sw_phy1: ethernet-phy at 1 {
+					reg = <0x1>;
+				};
+
+				sw_phy2: ethernet-phy at 2 {
+					reg = <0x2>;
+				};
+
+				sw_phy3: ethernet-phy at 3 {
+					reg = <0x3>;
+				};
+			};
+		};
 	};
 
 	crypto at 60 {
-- 
2.17.1



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