[PATCH 07/14] clk: ast2600: Add RSACLK control for ARCY

[Chia-Wei Wang]

Add RSACLK enable for ARCY, the HW RSA/ECC crypto engine
of ASPEED AST26xx SoCs.

Signed-off-by: Chia-Wei Wang <chiawei_wang at aspeedtech.com>
---
 arch/arm/include/asm/arch-aspeed/scu_ast2600.h |  1 +
 drivers/clk/aspeed/clk_ast2600.c               | 15 +++++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
index d7b500f656..27f4e9f994 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
@@ -8,6 +8,7 @@
 #define SCU_UNLOCK_KEY			0x1688a8a8
 
 #define SCU_CLKGATE1_EMMC			BIT(27)
+#define SCU_CLKGATE1_ARCY			BIT(24)
 #define SCU_CLKGATE1_MAC2			BIT(21)
 #define SCU_CLKGATE1_MAC1			BIT(20)
 #define SCU_CLKGATE1_USB_HUB			BIT(14)
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index 69128fd3c4..bf3379fce2 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -1030,6 +1030,18 @@ static ulong ast2600_enable_haceclk(struct ast2600_scu *scu)
 	return 0;
 }
 
+static ulong ast2600_enable_rsaclk(struct ast2600_scu *scu)
+{
+	uint32_t clkgate_bit;
+
+	clkgate_bit = SCU_CLKGATE1_ARCY;
+
+	writel(clkgate_bit, &scu->clkgate_clr1);
+	mdelay(20);
+
+	return 0;
+}
+
 static int ast2600_clk_enable(struct clk *clk)
 {
 	struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
@@ -1071,6 +1083,9 @@ static int ast2600_clk_enable(struct clk *clk)
 	case ASPEED_CLK_GATE_YCLK:
 		ast2600_enable_haceclk(priv->scu);
 		break;
+	case ASPEED_CLK_GATE_RSACLK:
+		ast2600_enable_rsaclk(priv->scu);
+		break;
 	default:
 		pr_err("can't enable clk\n");
 		return -ENOENT;
-- 
2.17.1