[PATCH v2 2/2] arm: imx8m: add support for Advantech RSB-3720

[Peng Fan (OSS)]

Hi Paul,

On 2021/7/15 8:50, Ying-Chun Liu wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Add initial support for Advantech RSB-3720 board.
> The initial support includes:
>   - MMC
>   - eMMC
>   - I2C
>   - FEC
>   - Serial console
> 
> Signed-off-by: Darren Huang <darren.huang at advantech.com.tw>
> Signed-off-by: Kevin12.Chen <Kevin12.Chen at advantech.com.tw>
> Signed-off-by: Phill.Liu <Phill.Liu at advantech.com.tw>
> Signed-off-by: Tim Liang <tim.liang at advantech.com.tw>
> Signed-off-by: wei.zeng <wei.zeng at advantech.com.cn>
> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> Cc: uboot-imx <uboot-imx at nxp.com>
> ---
>   arch/arm/dts/Makefile                         |    3 +
>   arch/arm/mach-imx/imx8m/Kconfig               |   15 +
>   board/freescale/imx8mp_rsb3720a1/Kconfig      |   14 +
>   board/freescale/imx8mp_rsb3720a1/MAINTAINERS  |    7 +
>   board/freescale/imx8mp_rsb3720a1/Makefile     |   24 +
>   .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c       |  391 ++++
>   .../imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg  |   11 +
>   .../lpddr4_timing_rsb3720a1_4G.c              | 1848 ++++++++++++++++
>   .../lpddr4_timing_rsb3720a1_6G.c              | 1875 +++++++++++++++++
>   board/freescale/imx8mp_rsb3720a1/spl.c        |  270 +++
>   configs/imx8mp_rsb3720a1_4G_defconfig         |  158 ++
>   configs/imx8mp_rsb3720a1_6G_defconfig         |  159 ++
>   include/configs/imx8mp_rsb3720.h              |  273 +++
>   13 files changed, 5048 insertions(+)
>   create mode 100644 board/freescale/imx8mp_rsb3720a1/Kconfig
>   create mode 100644 board/freescale/imx8mp_rsb3720a1/MAINTAINERS
>   create mode 100644 board/freescale/imx8mp_rsb3720a1/Makefile
>   create mode 100644 board/freescale/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
>   create mode 100644 board/freescale/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg
>   create mode 100644 board/freescale/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_4G.c
>   create mode 100644 board/freescale/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_6G.c
>   create mode 100644 board/freescale/imx8mp_rsb3720a1/spl.c
>   create mode 100644 configs/imx8mp_rsb3720a1_4G_defconfig
>   create mode 100644 configs/imx8mp_rsb3720a1_6G_defconfig
>   create mode 100644 include/configs/imx8mp_rsb3720.h

freescale/nxp is not the vendor is the board I think.
But if you prefer to leave it here, it should be ok.

> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 708ce2d094..ba458f3909 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1118,6 +1118,9 @@ dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
>   dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
>   
>   dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
> +ifneq ($(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)$(CONFIG_TARGET_IMX8MP_RSB3720A1_6G),)
> +dtb-y += imx8mp-rsb3720-a1.dtb
> +endif
>   
>   dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
>   
> diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
> index 0669363c0f..042efb1695 100644
> --- a/arch/arm/mach-imx/imx8m/Kconfig
> +++ b/arch/arm/mach-imx/imx8m/Kconfig
> @@ -137,6 +137,20 @@ config TARGET_IMX8MM_CL_IOT_GATE
>   	select IMX8MM
>   	select SUPPORT_SPL
>   	select IMX8M_LPDDR4
> +
> +config TARGET_IMX8MP_RSB3720A1_4G
> +	bool "Support i.MX8MP RSB3720A1 4G"
> +	select BINMAN
> +	select IMX8MP
> +	select SUPPORT_SPL
> +	select IMX8M_LPDDR4
> +
> +config TARGET_IMX8MP_RSB3720A1_6G
> +	bool "Support i.MX8MP RSB3720A1 6G"
> +	select BINMAN
> +	select IMX8MP
> +	select SUPPORT_SPL
> +	select IMX8M_LPDDR4
>   endchoice
>   
>   source "board/beacon/imx8mm/Kconfig"
> @@ -147,6 +161,7 @@ source "board/freescale/imx8mq_evk/Kconfig"
>   source "board/freescale/imx8mm_evk/Kconfig"
>   source "board/freescale/imx8mn_evk/Kconfig"
>   source "board/freescale/imx8mp_evk/Kconfig"
> +source "board/freescale/imx8mp_rsb3720a1/Kconfig"
>   source "board/gateworks/venice/Kconfig"
>   source "board/google/imx8mq_phanbell/Kconfig"
>   source "board/phytec/phycore_imx8mm/Kconfig"
> diff --git a/board/freescale/imx8mp_rsb3720a1/Kconfig b/board/freescale/imx8mp_rsb3720a1/Kconfig
> new file mode 100644
> index 0000000000..62c391ccca
> --- /dev/null
> +++ b/board/freescale/imx8mp_rsb3720a1/Kconfig
> @@ -0,0 +1,14 @@
> +if TARGET_IMX8MP_RSB3720A1_4G || TARGET_IMX8MP_RSB3720A1_6G
> +
> +config SYS_BOARD
> +	default "imx8mp_rsb3720a1"
> +
> +config SYS_VENDOR
> +	default "freescale"
> +
> +config SYS_CONFIG_NAME
> +	default "imx8mp_rsb3720"
> +
> +source "board/freescale/common/Kconfig"
> +
> +endif
> diff --git a/board/freescale/imx8mp_rsb3720a1/MAINTAINERS b/board/freescale/imx8mp_rsb3720a1/MAINTAINERS
> new file mode 100644
> index 0000000000..e806b770a5
> --- /dev/null
> +++ b/board/freescale/imx8mp_rsb3720a1/MAINTAINERS
> @@ -0,0 +1,7 @@
> +i.MX8MP RSB3720 BOARD
> +M:	Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> +S:	Maintained
> +F:	board/freescale/imx8mp_rsb3720a1/
> +F:	include/configs/imx8mp_rsb3720a1.h
> +F:	configs/imx8mp_rsb3720a1_4G_defconfig
> +F:	configs/imx8mp_rsb3720a1_6G_defconfig
> diff --git a/board/freescale/imx8mp_rsb3720a1/Makefile b/board/freescale/imx8mp_rsb3720a1/Makefile
> new file mode 100644
> index 0000000000..ae5b8b83eb
> --- /dev/null
> +++ b/board/freescale/imx8mp_rsb3720a1/Makefile
> @@ -0,0 +1,24 @@
> +#
> +# Copyright 2019 NXP
> +# Copyright 2021 Linaro
> +#
> +# SPDX-License-Identifier:      GPL-2.0+
> +#
> +
> +ifdef CONFIG_TARGET_IMX8MP_RSB3720A1_6G
> +obj-y += imx8mp_rsb3720a1.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_rsb3720a1_6G.o
> +endif
> +endif
> +
> +ifdef CONFIG_TARGET_IMX8MP_RSB3720A1_4G
> +obj-y += imx8mp_rsb3720a1.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_rsb3720a1_4G.o
> +endif
> +endif
> diff --git a/board/freescale/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/freescale/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
> new file mode 100644
> index 0000000000..9d13ce064b
> --- /dev/null
> +++ b/board/freescale/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
> @@ -0,0 +1,391 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + * Copyright 2021 Linaro
> + */
> +
> +#include <common.h>
> +#include <dwc3-uboot.h>
> +#include <errno.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <spl.h>
> +#include <usb.h>
> +#include <asm/io.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm-generic/gpio.h>
> +#include <asm/arch/imx8mp_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-imx/gpio.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <asm/arch/clock.h>
> +#include <asm/mach-imx/dma.h>
> +#include <linux/delay.h>
> +#include <power/pmic.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> +#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
> +
> +static iomux_v3_cfg_t const uart_pads[] = {
> +	MX8MP_PAD_ECSPI1_SCLK__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const wdog_pads[] = {
> +	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> +};
> +
> +#ifdef CONFIG_NAND_MXS
> +static void setup_gpmi_nand(void)
> +{
> +	init_nand_clk();
> +}
> +#endif
> +
> +int board_early_init_f(void)
> +{
> +	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> +
> +	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
> +
> +	set_wdog_reset(wdog);
> +
> +	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
> +
> +	init_uart_clk(2);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_OF_BOARD_SETUP
> +int ft_board_setup(void *blob, struct bd_info *bd)
> +{
> +	return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_FEC_MXC
> +#define FEC_RST_PAD IMX_GPIO_NR(4, 2)
> +static iomux_v3_cfg_t const fec1_rst_pads[] = {
> +	MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_iomux_fec(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
> +					 ARRAY_SIZE(fec1_rst_pads));
> +
> +	gpio_request(FEC_RST_PAD, "fec1_rst");
> +	gpio_direction_output(FEC_RST_PAD, 0);
> +	mdelay(15);
> +	gpio_direction_output(FEC_RST_PAD, 1);
> +	mdelay(100);
> +}
> +
> +static int setup_fec(void)
> +{
> +	struct iomuxc_gpr_base_regs *gpr =
> +		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> +
> +	setup_iomux_fec();
> +
> +	/* Enable RGMII TX clk output */
> +	setbits_le32(&gpr->gpr[1], BIT(22));
> +
> +	//return set_clk_enet(ENET_125MHZ);

Drop this, if you not need.

> +	return 0;
> +}
> +#endif /* CONFIG_FEC_MXC */
> +
> +#ifdef CONFIG_DWC_ETH_QOS
> +#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
> +static iomux_v3_cfg_t const eqos_rst_pads[] = {
> +	MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_iomux_eqos(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
> +					 ARRAY_SIZE(eqos_rst_pads));
> +
> +	gpio_request(EQOS_RST_PAD, "eqos_rst");
> +	gpio_direction_output(EQOS_RST_PAD, 0);
> +	mdelay(15);
> +	gpio_direction_output(EQOS_RST_PAD, 1);
> +	mdelay(100);
> +}
> +
> +static int setup_eqos(void)
> +{
> +	struct iomuxc_gpr_base_regs *gpr =
> +		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> +
> +	setup_iomux_eqos();
> +
> +	/* set INTF as RGMII, enable RGMII TXC clock */
> +	clrsetbits_le32(&gpr->gpr[1],
> +			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
> +	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
> +
> +	return set_clk_eqos(ENET_125MHZ);
> +}
> +#endif /* CONFIG_DWC_ETH_QOS */
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> +	if (IS_ENABLED(CONFIG_FEC_MXC) || IS_ENABLED(CONFIG_DWC_ETH_QOS)) {
> +		/* enable rgmii rxc skew and phy mode select to RGMII copper */
> +		phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> +		phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> +
> +		phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> +		phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> +		phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> +		phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +
> +		if (phydev->drv->config)
> +			phydev->drv->config(phydev);
> +	}
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_USB_DWC3

i.MX8MP DWC3 support has not landed in upstream.

> +#define USB_PHY_CTRL0			0xF0040
> +#define USB_PHY_CTRL0_REF_SSP_EN	BIT(2)
> +
> +#define USB_PHY_CTRL1			0xF0044
> +#define USB_PHY_CTRL1_RESET		BIT(0)
> +#define USB_PHY_CTRL1_COMMONONN		BIT(1)
> +#define USB_PHY_CTRL1_ATERESET		BIT(3)
> +#define USB_PHY_CTRL1_VDATSRCENB0	BIT(19)
> +#define USB_PHY_CTRL1_VDATDETENB0	BIT(20)
> +
> +#define USB_PHY_CTRL2			0xF0048
> +#define USB_PHY_CTRL2_TXENABLEN0	BIT(8)
> +
> +#define USB_PHY_CTRL6			0xF0058
> +
> +#define HSIO_GPR_BASE                               (0x32F10000U)
> +#define HSIO_GPR_REG_0                              (HSIO_GPR_BASE)
> +#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT    (1)
> +#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN          (0x1U << \
> +				HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT)
> +
> +#define USB1_BASE_ADDR          0x38100000
> +
> +static struct dwc3_device dwc3_device_data = {
> +#ifdef CONFIG_SPL_BUILD
> +	.maximum_speed = USB_SPEED_HIGH,
> +#else
> +	.maximum_speed = USB_SPEED_SUPER,
> +#endif
> +	.base = USB1_BASE_ADDR,
> +	.dr_mode = USB_DR_MODE_PERIPHERAL,
> +	.index = 0,
> +};
> +
> +int usb_gadget_handle_interrupts(void)
> +{
> +	dwc3_uboot_handle_interrupt(0);
> +	return 0;
> +}
> +
> +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
> +{
> +	u32 RegData;
> +
> +	/* enable usb clock via hsio gpr */
> +	RegData = readl(HSIO_GPR_REG_0);
> +	RegData |= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN;
> +	writel(RegData, HSIO_GPR_REG_0);
> +
> +	/* USB3.0 PHY signal fsel for 100M ref */
> +	RegData = readl(dwc3->base + USB_PHY_CTRL0);
> +	RegData = (RegData & 0xfffff81f) | (0x2a << 5);
> +	writel(RegData, dwc3->base + USB_PHY_CTRL0);
> +
> +	RegData = readl(dwc3->base + USB_PHY_CTRL6);
> +	RegData &= ~0x1;
> +	writel(RegData, dwc3->base + USB_PHY_CTRL6);
> +
> +	RegData = readl(dwc3->base + USB_PHY_CTRL1);
> +	RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
> +			USB_PHY_CTRL1_COMMONONN);
> +	RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
> +	writel(RegData, dwc3->base + USB_PHY_CTRL1);
> +
> +	RegData = readl(dwc3->base + USB_PHY_CTRL0);
> +	RegData |= USB_PHY_CTRL0_REF_SSP_EN;
> +	writel(RegData, dwc3->base + USB_PHY_CTRL0);
> +
> +	RegData = readl(dwc3->base + USB_PHY_CTRL2);
> +	RegData |= USB_PHY_CTRL2_TXENABLEN0;
> +	writel(RegData, dwc3->base + USB_PHY_CTRL2);
> +
> +	RegData = readl(dwc3->base + USB_PHY_CTRL1);
> +	RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
> +	writel(RegData, dwc3->base + USB_PHY_CTRL1);
> +}
> +#endif /* CONFIG_USB_DWC3 */
> +
> +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
> +#define FSL_SIP_GPC			0xC2000000
> +#define FSL_SIP_CONFIG_GPC_PM_DOMAIN	0x03
> +
> +#ifdef CONFIG_SPL_BUILD
> +static u32 gpc_pu_m_core_offset[11] = {
> +	0xc00, 0xc40, 0xc80, 0xcc0,
> +	0xdc0, 0xe00, 0xe40, 0xe80,
> +	0xec0, 0xf00, 0xf40,
> +};
> +
> +#define PGC_PCR				0
> +
> +void imx_gpc_set_m_core_pgc(unsigned int offset, bool pdn)
> +{
> +	u32 val;
> +	uintptr_t reg = GPC_BASE_ADDR + offset;
> +
> +	val = readl(reg);
> +	val &= ~(0x1 << PGC_PCR);
> +
> +	if (pdn)
> +		val |= 0x1 << PGC_PCR;
> +	writel(val, reg);
> +}
> +
> +void imx8m_usb_power_domain(u32 domain_id, bool on)
> +{
> +	u32 val;
> +	uintptr_t reg;
> +
> +	imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], true);
> +
> +	reg = GPC_BASE_ADDR + (on ? 0xf8 : 0x104);
> +	val = 1 << (domain_id > 3 ? (domain_id + 3) : domain_id);
> +	writel(val, reg);
> +	while (readl(reg) & val)
> +		;
> +	imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], false);
> +}
> +#endif
> +
> +int imx8m_usb_power(int usb_id, bool on)
> +{
> +	if (usb_id > 1)
> +		return -EINVAL;
> +
> +#ifdef CONFIG_SPL_BUILD
> +	imx8m_usb_power_domain(2 + usb_id, on);

You need usb storage in SPL stage?

> +#else
> +	unsigned long ret = 0;
> +	//	ret = call_imx_sip(FSL_SIP_GPC,
> +	//		FSL_SIP_CONFIG_GPC_PM_DOMAIN, 2 + usb_id, on, 0);

Drop this is not need.

> +	if (ret)
> +		return -EPERM;
> +#endif
> +
> +	return 0;
> +}
> +
> +#define USB2_PWR_EN IMX_GPIO_NR(1, 14)
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> +	int ret = 0;
> +
> +	imx8m_usb_power(index, true);
> +
> +	if (index == 0 && init == USB_INIT_DEVICE) {
> +		dwc3_nxp_usb_phy_init(&dwc3_device_data);
> +		return dwc3_uboot_init(&dwc3_device_data);
> +	} else if (index == 0 && init == USB_INIT_HOST) {
> +		return ret;
> +	} else if (index == 1 && init == USB_INIT_HOST) {
> +		/* Enable GPIO1_IO14 for 5V VBUS */
> +		gpio_request(USB2_PWR_EN, "usb2_pwr");
> +		gpio_direction_output(USB2_PWR_EN, 1);
> +	}
> +
> +	return 0;
> +}
> +
> +int board_usb_cleanup(int index, enum usb_init_type init)
> +{
> +	int ret = 0;
> +
> +	if (index == 0 && init == USB_INIT_DEVICE) {
> +		dwc3_uboot_exit(index);
> +	} else if (index == 1 && init == USB_INIT_HOST) {
> +		/* Disable GPIO1_IO14 for 5V VBUS */
> +		gpio_direction_output(USB2_PWR_EN, 0);
> +	}
> +
> +	imx8m_usb_power(index, false);
> +
> +	return ret;
> +}
> +#endif
> +
> +#define DISPMIX				13
> +#define MIPI				15
> +
> +#define WDOG_TRIG IMX_GPIO_NR(4, 20)
> +
> +static iomux_v3_cfg_t wdt_trig[] = {
> +	MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_iomux_wdt(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(wdt_trig, ARRAY_SIZE(wdt_trig));
> +	gpio_request(WDOG_TRIG, "wdt_trig");
> +	gpio_direction_output(WDOG_TRIG, 1);
> +}
> +
> +int board_init(void)
> +{
> +#ifdef CONFIG_FEC_MXC
> +	setup_fec();
> +#endif
> +
> +#ifdef CONFIG_DWC_ETH_QOS
> +	/* clock, pin, gpr */
> +	setup_eqos();
> +#endif
> +
> +#ifdef CONFIG_NAND_MXS
> +	setup_gpmi_nand();
> +#endif
> +
> +	setup_iomux_wdt();
> +
> +	return 0;
> +}
> +
> +int board_late_init(void)
> +{
> +	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
> +		env_set("board_name", "RSB3720A1");
> +		env_set("board_rev", "iMX8MP");
> +	}
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_SPL_MMC_SUPPORT
> +#define UBOOT_RAW_SECTOR_OFFSET 0x40
> +unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
> +{
> +	u32 boot_dev = spl_boot_device();
> +
> +	switch (boot_dev) {
> +	case BOOT_DEVICE_MMC2:
> +		return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
> +	default:
> +		return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
> +	}
> +}
> +#endif /* CONFIG_SPL_MMC_SUPPORT */
> diff --git a/board/freescale/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg b/board/freescale/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg
> new file mode 100644
> index 0000000000..e061d0da53
> --- /dev/null
> +++ b/board/freescale/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019 NXP
> + * Copyright 2021 NXP
> + */
> +
> +#define __ASSEMBLY__
> +
> +ROM_VERSION	v2
> +BOOT_FROM	sd
> +LOADER		mkimage.flash.mkimage	0x920000
> diff --git a/board/freescale/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_4G.c b/board/freescale/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_4G.c
> new file mode 100644
> index 0000000000..e7ed32e251
> --- /dev/null
> +++ b/board/freescale/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_4G.c
> @@ -0,0 +1,1848 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +#include <linux/kernel.h>
> +#include <asm/arch/ddr.h>
> +
> +struct dram_cfg_param ddr_ddrc_cfg[] = {
> +	/** Initialize DDRC registers **/
> +	{ 0x3d400304, 0x1 },
> +	{ 0x3d400030, 0x1 },
> +	{ 0x3d400000, 0xa3080020 },
> +	{ 0x3d400020, 0x323 },
> +	{ 0x3d400024, 0x1e84800 },
> +	{ 0x3d400064, 0x7a0118 },
> +	{ 0x3d4000d0, 0xc00307a3 },
> +	{ 0x3d4000d4, 0xc50000 },
> +	{ 0x3d4000dc, 0xf4003f },
> +	{ 0x3d4000e0, 0x330000 },
> +	{ 0x3d4000e8, 0x660048 },
> +	{ 0x3d4000ec, 0x160048 },
> +	{ 0x3d400100, 0x2028222a },
> +	{ 0x3d400104, 0x807bf },
> +	{ 0x3d40010c, 0xe0e000 },
> +	{ 0x3d400110, 0x12040a12 },
> +	{ 0x3d400114, 0x2050f0f },
> +	{ 0x3d400118, 0x1010009 },
> +	{ 0x3d40011c, 0x501 },
> +	{ 0x3d400130, 0x20800 },
> +	{ 0x3d400134, 0xe100002 },
> +	{ 0x3d400138, 0x120 },
> +	{ 0x3d400144, 0xc80064 },
> +	{ 0x3d400180, 0x3e8001e },
> +	{ 0x3d400184, 0x3207a12 },
> +	{ 0x3d400188, 0x0 },
> +	{ 0x3d400190, 0x49f820e },
> +	{ 0x3d400194, 0x80303 },
> +	{ 0x3d4001b4, 0x1f0e },
> +	{ 0x3d4001a0, 0xe0400018 },
> +	{ 0x3d4001a4, 0xdf00e4 },
> +	{ 0x3d4001a8, 0x80000000 },
> +	{ 0x3d4001b0, 0x11 },
> +	{ 0x3d4001c0, 0x1 },
> +	{ 0x3d4001c4, 0x1 },
> +	{ 0x3d4000f4, 0xc99 },
> +	{ 0x3d400108, 0x9121c1c },
> +	{ 0x3d400200, 0x17 },
> +	{ 0x3d40020c, 0x0 },
> +	{ 0x3d400210, 0x1f1f },
> +	{ 0x3d400204, 0x80808 },
> +	{ 0x3d400214, 0x7070707 },
> +	{ 0x3d400218, 0x7070707 },
> +	{ 0x3d40021c, 0xf07 },
> +	{ 0x3d400250, 0x1f05 },
> +	{ 0x3d400254, 0x1f },
> +	{ 0x3d400264, 0x90003ff },
> +	{ 0x3d40026c, 0x20003ff },
> +	{ 0x3d400400, 0x111 },
> +	{ 0x3d400408, 0x72ff },
> +	{ 0x3d400494, 0x1000e00 },
> +	{ 0x3d400498, 0x3ff0000 },
> +	{ 0x3d40049c, 0x1000e00 },
> +	{ 0x3d4004a0, 0x3ff0000 },
> +	{ 0x3d402020, 0x21 },
> +	{ 0x3d402024, 0x30d400 },
> +	{ 0x3d402050, 0x20d040 },
> +	{ 0x3d402064, 0xc001c },
> +	{ 0x3d4020dc, 0x840000 },
> +	{ 0x3d4020e0, 0x330000 },
> +	{ 0x3d4020e8, 0x660048 },
> +	{ 0x3d4020ec, 0x160048 },
> +	{ 0x3d402100, 0xa040305 },
> +	{ 0x3d402104, 0x30407 },
> +	{ 0x3d402108, 0x203060b },
> +	{ 0x3d40210c, 0x505000 },
> +	{ 0x3d402110, 0x2040202 },
> +	{ 0x3d402114, 0x2030202 },
> +	{ 0x3d402118, 0x1010004 },
> +	{ 0x3d40211c, 0x301 },
> +	{ 0x3d402130, 0x20300 },
> +	{ 0x3d402134, 0xa100002 },
> +	{ 0x3d402138, 0x1d },
> +	{ 0x3d402144, 0x14000a },
> +	{ 0x3d402180, 0x640004 },
> +	{ 0x3d402190, 0x3818200 },
> +	{ 0x3d402194, 0x80303 },
> +	{ 0x3d4021b4, 0x100 },
> +	{ 0x3d4020f4, 0xc99 },
> +	{ 0x3d403020, 0x21 },
> +	{ 0x3d403024, 0xc3500 },
> +	{ 0x3d403050, 0x20d040 },
> +	{ 0x3d403064, 0x30007 },
> +	{ 0x3d4030dc, 0x840000 },
> +	{ 0x3d4030e0, 0x330000 },
> +	{ 0x3d4030e8, 0x660048 },
> +	{ 0x3d4030ec, 0x160048 },
> +	{ 0x3d403100, 0xa010102 },
> +	{ 0x3d403104, 0x30404 },
> +	{ 0x3d403108, 0x203060b },
> +	{ 0x3d40310c, 0x505000 },
> +	{ 0x3d403110, 0x2040202 },
> +	{ 0x3d403114, 0x2030202 },
> +	{ 0x3d403118, 0x1010004 },
> +	{ 0x3d40311c, 0x301 },
> +	{ 0x3d403130, 0x20300 },
> +	{ 0x3d403134, 0xa100002 },
> +	{ 0x3d403138, 0x8 },
> +	{ 0x3d403144, 0x50003 },
> +	{ 0x3d403180, 0x190004 },
> +	{ 0x3d403190, 0x3818200 },
> +	{ 0x3d403194, 0x80303 },
> +	{ 0x3d4031b4, 0x100 },
> +	{ 0x3d4030f4, 0xc99 },
> +	{ 0x3d400028, 0x0 },
> +};
> +
> +/* PHY Initialize Configuration */
> +struct dram_cfg_param ddr_ddrphy_cfg[] = {
> +	{ 0x100a0, 0x0 },
> +	{ 0x100a1, 0x1 },
> +	{ 0x100a2, 0x2 },
> +	{ 0x100a3, 0x3 },
> +	{ 0x100a4, 0x4 },
> +	{ 0x100a5, 0x5 },
> +	{ 0x100a6, 0x6 },
> +	{ 0x100a7, 0x7 },
> +	{ 0x110a0, 0x0 },
> +	{ 0x110a1, 0x1 },
> +	{ 0x110a2, 0x3 },
> +	{ 0x110a3, 0x4 },
> +	{ 0x110a4, 0x5 },
> +	{ 0x110a5, 0x2 },
> +	{ 0x110a6, 0x7 },
> +	{ 0x110a7, 0x6 },
> +	{ 0x120a0, 0x0 },
> +	{ 0x120a1, 0x1 },
> +	{ 0x120a2, 0x3 },
> +	{ 0x120a3, 0x2 },
> +	{ 0x120a4, 0x5 },
> +	{ 0x120a5, 0x4 },
> +	{ 0x120a6, 0x7 },
> +	{ 0x120a7, 0x6 },
> +	{ 0x130a0, 0x0 },
> +	{ 0x130a1, 0x1 },
> +	{ 0x130a2, 0x2 },
> +	{ 0x130a3, 0x3 },
> +	{ 0x130a4, 0x4 },
> +	{ 0x130a5, 0x5 },
> +	{ 0x130a6, 0x6 },
> +	{ 0x130a7, 0x7 },
> +	{ 0x1005f, 0x1ff },
> +	{ 0x1015f, 0x1ff },
> +	{ 0x1105f, 0x1ff },
> +	{ 0x1115f, 0x1ff },
> +	{ 0x1205f, 0x1ff },
> +	{ 0x1215f, 0x1ff },
> +	{ 0x1305f, 0x1ff },
> +	{ 0x1315f, 0x1ff },
> +	{ 0x11005f, 0x1ff },
> +	{ 0x11015f, 0x1ff },
> +	{ 0x11105f, 0x1ff },
> +	{ 0x11115f, 0x1ff },
> +	{ 0x11205f, 0x1ff },
> +	{ 0x11215f, 0x1ff },
> +	{ 0x11305f, 0x1ff },
> +	{ 0x11315f, 0x1ff },
> +	{ 0x21005f, 0x1ff },
> +	{ 0x21015f, 0x1ff },
> +	{ 0x21105f, 0x1ff },
> +	{ 0x21115f, 0x1ff },
> +	{ 0x21205f, 0x1ff },
> +	{ 0x21215f, 0x1ff },
> +	{ 0x21305f, 0x1ff },
> +	{ 0x21315f, 0x1ff },
> +	{ 0x55, 0x1ff },
> +	{ 0x1055, 0x1ff },
> +	{ 0x2055, 0x1ff },
> +	{ 0x3055, 0x1ff },
> +	{ 0x4055, 0x1ff },
> +	{ 0x5055, 0x1ff },
> +	{ 0x6055, 0x1ff },
> +	{ 0x7055, 0x1ff },
> +	{ 0x8055, 0x1ff },
> +	{ 0x9055, 0x1ff },
> +	{ 0x200c5, 0x18 },
> +	{ 0x1200c5, 0x7 },
> +	{ 0x2200c5, 0x7 },
> +	{ 0x2002e, 0x2 },
> +	{ 0x12002e, 0x2 },
> +	{ 0x22002e, 0x2 },
> +	{ 0x90204, 0x0 },
> +	{ 0x190204, 0x0 },
> +	{ 0x290204, 0x0 },
> +	{ 0x20024, 0x1e3 },
> +	{ 0x2003a, 0x2 },
> +	{ 0x120024, 0x1e3 },
> +	{ 0x2003a, 0x2 },
> +	{ 0x220024, 0x1e3 },
> +	{ 0x2003a, 0x2 },
> +	{ 0x20056, 0x3 },
> +	{ 0x120056, 0x3 },
> +	{ 0x220056, 0x3 },
> +	{ 0x1004d, 0xe00 },
> +	{ 0x1014d, 0xe00 },
> +	{ 0x1104d, 0xe00 },
> +	{ 0x1114d, 0xe00 },
> +	{ 0x1204d, 0xe00 },
> +	{ 0x1214d, 0xe00 },
> +	{ 0x1304d, 0xe00 },
> +	{ 0x1314d, 0xe00 },
> +	{ 0x11004d, 0xe00 },
> +	{ 0x11014d, 0xe00 },
> +	{ 0x11104d, 0xe00 },
> +	{ 0x11114d, 0xe00 },
> +	{ 0x11204d, 0xe00 },
> +	{ 0x11214d, 0xe00 },
> +	{ 0x11304d, 0xe00 },
> +	{ 0x11314d, 0xe00 },
> +	{ 0x21004d, 0xe00 },
> +	{ 0x21014d, 0xe00 },
> +	{ 0x21104d, 0xe00 },
> +	{ 0x21114d, 0xe00 },
> +	{ 0x21204d, 0xe00 },
> +	{ 0x21214d, 0xe00 },
> +	{ 0x21304d, 0xe00 },
> +	{ 0x21314d, 0xe00 },
> +	{ 0x10049, 0xeba },
> +	{ 0x10149, 0xeba },
> +	{ 0x11049, 0xeba },
> +	{ 0x11149, 0xeba },
> +	{ 0x12049, 0xeba },
> +	{ 0x12149, 0xeba },
> +	{ 0x13049, 0xeba },
> +	{ 0x13149, 0xeba },
> +	{ 0x110049, 0xeba },
> +	{ 0x110149, 0xeba },
> +	{ 0x111049, 0xeba },
> +	{ 0x111149, 0xeba },
> +	{ 0x112049, 0xeba },
> +	{ 0x112149, 0xeba },
> +	{ 0x113049, 0xeba },
> +	{ 0x113149, 0xeba },
> +	{ 0x210049, 0xeba },
> +	{ 0x210149, 0xeba },
> +	{ 0x211049, 0xeba },
> +	{ 0x211149, 0xeba },
> +	{ 0x212049, 0xeba },
> +	{ 0x212149, 0xeba },
> +	{ 0x213049, 0xeba },
> +	{ 0x213149, 0xeba },
> +	{ 0x43, 0x63 },
> +	{ 0x1043, 0x63 },
> +	{ 0x2043, 0x63 },
> +	{ 0x3043, 0x63 },
> +	{ 0x4043, 0x63 },
> +	{ 0x5043, 0x63 },
> +	{ 0x6043, 0x63 },
> +	{ 0x7043, 0x63 },
> +	{ 0x8043, 0x63 },
> +	{ 0x9043, 0x63 },
> +	{ 0x20018, 0x3 },
> +	{ 0x20075, 0x4 },
> +	{ 0x20050, 0x0 },
> +	{ 0x20008, 0x3e8 },
> +	{ 0x120008, 0x64 },
> +	{ 0x220008, 0x19 },
> +	{ 0x20088, 0x9 },
> +	{ 0x200b2, 0x104 },
> +	{ 0x10043, 0x5a1 },
> +	{ 0x10143, 0x5a1 },
> +	{ 0x11043, 0x5a1 },
> +	{ 0x11143, 0x5a1 },
> +	{ 0x12043, 0x5a1 },
> +	{ 0x12143, 0x5a1 },
> +	{ 0x13043, 0x5a1 },
> +	{ 0x13143, 0x5a1 },
> +	{ 0x1200b2, 0x104 },
> +	{ 0x110043, 0x5a1 },
> +	{ 0x110143, 0x5a1 },
> +	{ 0x111043, 0x5a1 },
> +	{ 0x111143, 0x5a1 },
> +	{ 0x112043, 0x5a1 },
> +	{ 0x112143, 0x5a1 },
> +	{ 0x113043, 0x5a1 },
> +	{ 0x113143, 0x5a1 },
> +	{ 0x2200b2, 0x104 },
> +	{ 0x210043, 0x5a1 },
> +	{ 0x210143, 0x5a1 },
> +	{ 0x211043, 0x5a1 },
> +	{ 0x211143, 0x5a1 },
> +	{ 0x212043, 0x5a1 },
> +	{ 0x212143, 0x5a1 },
> +	{ 0x213043, 0x5a1 },
> +	{ 0x213143, 0x5a1 },
> +	{ 0x200fa, 0x1 },
> +	{ 0x1200fa, 0x1 },
> +	{ 0x2200fa, 0x1 },
> +	{ 0x20019, 0x1 },
> +	{ 0x120019, 0x1 },
> +	{ 0x220019, 0x1 },
> +	{ 0x200f0, 0x660 },
> +	{ 0x200f1, 0x0 },
> +	{ 0x200f2, 0x4444 },
> +	{ 0x200f3, 0x8888 },
> +	{ 0x200f4, 0x5665 },
> +	{ 0x200f5, 0x0 },
> +	{ 0x200f6, 0x0 },
> +	{ 0x200f7, 0xf000 },
> +	{ 0x20025, 0x0 },
> +	{ 0x2002d, 0x0 },
> +	{ 0x12002d, 0x0 },
> +	{ 0x22002d, 0x0 },
> +	{ 0x2007d, 0x212 },
> +	{ 0x12007d, 0x212 },
> +	{ 0x22007d, 0x212 },
> +	{ 0x2007c, 0x61 },
> +	{ 0x12007c, 0x61 },
> +	{ 0x22007c, 0x61 },
> +	{ 0x1004a, 0x500 },
> +	{ 0x1104a, 0x500 },
> +	{ 0x1204a, 0x500 },
> +	{ 0x1304a, 0x500 },
> +	{ 0x2002c, 0x0 },
> +};
> +
> +/* ddr phy trained csr */
> +struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
> +	{ 0x200b2, 0x0 },
> +	{ 0x1200b2, 0x0 },
> +	{ 0x2200b2, 0x0 },
> +	{ 0x200cb, 0x0 },
> +	{ 0x10043, 0x0 },
> +	{ 0x110043, 0x0 },
> +	{ 0x210043, 0x0 },
> +	{ 0x10143, 0x0 },
> +	{ 0x110143, 0x0 },
> +	{ 0x210143, 0x0 },
> +	{ 0x11043, 0x0 },
> +	{ 0x111043, 0x0 },
> +	{ 0x211043, 0x0 },
> +	{ 0x11143, 0x0 },
> +	{ 0x111143, 0x0 },
> +	{ 0x211143, 0x0 },
> +	{ 0x12043, 0x0 },
> +	{ 0x112043, 0x0 },
> +	{ 0x212043, 0x0 },
> +	{ 0x12143, 0x0 },
> +	{ 0x112143, 0x0 },
> +	{ 0x212143, 0x0 },
> +	{ 0x13043, 0x0 },
> +	{ 0x113043, 0x0 },
> +	{ 0x213043, 0x0 },
> +	{ 0x13143, 0x0 },
> +	{ 0x113143, 0x0 },
> +	{ 0x213143, 0x0 },
> +	{ 0x80, 0x0 },
> +	{ 0x100080, 0x0 },
> +	{ 0x200080, 0x0 },
> +	{ 0x1080, 0x0 },
> +	{ 0x101080, 0x0 },
> +	{ 0x201080, 0x0 },
> +	{ 0x2080, 0x0 },
> +	{ 0x102080, 0x0 },
> +	{ 0x202080, 0x0 },
> +	{ 0x3080, 0x0 },
> +	{ 0x103080, 0x0 },
> +	{ 0x203080, 0x0 },
> +	{ 0x4080, 0x0 },
> +	{ 0x104080, 0x0 },
> +	{ 0x204080, 0x0 },
> +	{ 0x5080, 0x0 },
> +	{ 0x105080, 0x0 },
> +	{ 0x205080, 0x0 },
> +	{ 0x6080, 0x0 },
> +	{ 0x106080, 0x0 },
> +	{ 0x206080, 0x0 },
> +	{ 0x7080, 0x0 },
> +	{ 0x107080, 0x0 },
> +	{ 0x207080, 0x0 },
> +	{ 0x8080, 0x0 },
> +	{ 0x108080, 0x0 },
> +	{ 0x208080, 0x0 },
> +	{ 0x9080, 0x0 },
> +	{ 0x109080, 0x0 },
> +	{ 0x209080, 0x0 },
> +	{ 0x10080, 0x0 },
> +	{ 0x110080, 0x0 },
> +	{ 0x210080, 0x0 },
> +	{ 0x10180, 0x0 },
> +	{ 0x110180, 0x0 },
> +	{ 0x210180, 0x0 },
> +	{ 0x11080, 0x0 },
> +	{ 0x111080, 0x0 },
> +	{ 0x211080, 0x0 },
> +	{ 0x11180, 0x0 },
> +	{ 0x111180, 0x0 },
> +	{ 0x211180, 0x0 },
> +	{ 0x12080, 0x0 },
> +	{ 0x112080, 0x0 },
> +	{ 0x212080, 0x0 },
> +	{ 0x12180, 0x0 },
> +	{ 0x112180, 0x0 },
> +	{ 0x212180, 0x0 },
> +	{ 0x13080, 0x0 },
> +	{ 0x113080, 0x0 },
> +	{ 0x213080, 0x0 },
> +	{ 0x13180, 0x0 },
> +	{ 0x113180, 0x0 },
> +	{ 0x213180, 0x0 },
> +	{ 0x10081, 0x0 },
> +	{ 0x110081, 0x0 },
> +	{ 0x210081, 0x0 },
> +	{ 0x10181, 0x0 },
> +	{ 0x110181, 0x0 },
> +	{ 0x210181, 0x0 },
> +	{ 0x11081, 0x0 },
> +	{ 0x111081, 0x0 },
> +	{ 0x211081, 0x0 },
> +	{ 0x11181, 0x0 },
> +	{ 0x111181, 0x0 },
> +	{ 0x211181, 0x0 },
> +	{ 0x12081, 0x0 },
> +	{ 0x112081, 0x0 },
> +	{ 0x212081, 0x0 },
> +	{ 0x12181, 0x0 },
> +	{ 0x112181, 0x0 },
> +	{ 0x212181, 0x0 },
> +	{ 0x13081, 0x0 },
> +	{ 0x113081, 0x0 },
> +	{ 0x213081, 0x0 },
> +	{ 0x13181, 0x0 },
> +	{ 0x113181, 0x0 },
> +	{ 0x213181, 0x0 },
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> +	{ 0x10662, 0x0 },
> +	{ 0x10762, 0x0 },
> +	{ 0x10862, 0x0 },
> +	{ 0x11062, 0x0 },
> +	{ 0x11162, 0x0 },
> +	{ 0x11262, 0x0 },
> +	{ 0x11362, 0x0 },
> +	{ 0x11462, 0x0 },
> +	{ 0x11562, 0x0 },
> +	{ 0x11662, 0x0 },
> +	{ 0x11762, 0x0 },
> +	{ 0x11862, 0x0 },
> +	{ 0x12062, 0x0 },
> +	{ 0x12162, 0x0 },
> +	{ 0x12262, 0x0 },
> +	{ 0x12362, 0x0 },
> +	{ 0x12462, 0x0 },
> +	{ 0x12562, 0x0 },
> +	{ 0x12662, 0x0 },
> +	{ 0x12762, 0x0 },
> +	{ 0x12862, 0x0 },
> +	{ 0x13062, 0x0 },
> +	{ 0x13162, 0x0 },
> +	{ 0x13262, 0x0 },
> +	{ 0x13362, 0x0 },
> +	{ 0x13462, 0x0 },
> +	{ 0x13562, 0x0 },
> +	{ 0x13662, 0x0 },
> +	{ 0x13762, 0x0 },
> +	{ 0x13862, 0x0 },
> +	{ 0x20077, 0x0 },
> +	{ 0x10001, 0x0 },
> +	{ 0x11001, 0x0 },
> +	{ 0x12001, 0x0 },
> +	{ 0x13001, 0x0 },
> +	{ 0x10040, 0x0 },
> +	{ 0x10140, 0x0 },
> +	{ 0x10240, 0x0 },
> +	{ 0x10340, 0x0 },
> +	{ 0x10440, 0x0 },
> +	{ 0x10540, 0x0 },
> +	{ 0x10640, 0x0 },
> +	{ 0x10740, 0x0 },
> +	{ 0x10840, 0x0 },
> +	{ 0x10030, 0x0 },
> +	{ 0x10130, 0x0 },
> +	{ 0x10230, 0x0 },
> +	{ 0x10330, 0x0 },
> +	{ 0x10430, 0x0 },
> +	{ 0x10530, 0x0 },
> +	{ 0x10630, 0x0 },
> +	{ 0x10730, 0x0 },
> +	{ 0x10830, 0x0 },
> +	{ 0x11040, 0x0 },
> +	{ 0x11140, 0x0 },
> +	{ 0x11240, 0x0 },
> +	{ 0x11340, 0x0 },
> +	{ 0x11440, 0x0 },
> +	{ 0x11540, 0x0 },
> +	{ 0x11640, 0x0 },
> +	{ 0x11740, 0x0 },
> +	{ 0x11840, 0x0 },
> +	{ 0x11030, 0x0 },
> +	{ 0x11130, 0x0 },
> +	{ 0x11230, 0x0 },
> +	{ 0x11330, 0x0 },
> +	{ 0x11430, 0x0 },
> +	{ 0x11530, 0x0 },
> +	{ 0x11630, 0x0 },
> +	{ 0x11730, 0x0 },
> +	{ 0x11830, 0x0 },
> +	{ 0x12040, 0x0 },
> +	{ 0x12140, 0x0 },
> +	{ 0x12240, 0x0 },
> +	{ 0x12340, 0x0 },
> +	{ 0x12440, 0x0 },
> +	{ 0x12540, 0x0 },
> +	{ 0x12640, 0x0 },
> +	{ 0x12740, 0x0 },
> +	{ 0x12840, 0x0 },
> +	{ 0x12030, 0x0 },
> +	{ 0x12130, 0x0 },
> +	{ 0x12230, 0x0 },
> +	{ 0x12330, 0x0 },
> +	{ 0x12430, 0x0 },
> +	{ 0x12530, 0x0 },
> +	{ 0x12630, 0x0 },
> +	{ 0x12730, 0x0 },
> +	{ 0x12830, 0x0 },
> +	{ 0x13040, 0x0 },
> +	{ 0x13140, 0x0 },
> +	{ 0x13240, 0x0 },
> +	{ 0x13340, 0x0 },
> +	{ 0x13440, 0x0 },
> +	{ 0x13540, 0x0 },
> +	{ 0x13640, 0x0 },
> +	{ 0x13740, 0x0 },
> +	{ 0x13840, 0x0 },
> +	{ 0x13030, 0x0 },
> +	{ 0x13130, 0x0 },
> +	{ 0x13230, 0x0 },
> +	{ 0x13330, 0x0 },
> +	{ 0x13430, 0x0 },
> +	{ 0x13530, 0x0 },
> +	{ 0x13630, 0x0 },
> +	{ 0x13730, 0x0 },
> +	{ 0x13830, 0x0 },
> +};
> +
> +/* P0 message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp0_cfg[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x54003, 0xfa0 },
> +	{ 0x54004, 0x2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, 0x14 },
> +	{ 0x54008, 0x131f },
> +	{ 0x54009, 0xc8 },
> +	{ 0x5400b, 0x2 },
> +	{ 0x5400f, 0x100 },
> +	{ 0x54012, 0x310 },
> +	{ 0x54019, 0x3ff4 },
> +	{ 0x5401a, 0x33 },
> +	{ 0x5401b, 0x4866 },
> +	{ 0x5401c, 0x4800 },
> +	{ 0x5401e, 0x16 },
> +	{ 0x5401f, 0x3ff4 },
> +	{ 0x54020, 0x33 },
> +	{ 0x54021, 0x4866 },
> +	{ 0x54022, 0x4800 },
> +	{ 0x54024, 0x16 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, 0x3 },
> +	{ 0x54032, 0xf400 },
> +	{ 0x54033, 0x333f },
> +	{ 0x54034, 0x6600 },
> +	{ 0x54035, 0x48 },
> +	{ 0x54036, 0x48 },
> +	{ 0x54037, 0x1600 },
> +	{ 0x54038, 0xf400 },
> +	{ 0x54039, 0x333f },
> +	{ 0x5403a, 0x6600 },
> +	{ 0x5403b, 0x48 },
> +	{ 0x5403c, 0x48 },
> +	{ 0x5403d, 0x1600 },
> +	{ 0xd0000, 0x1 },
> +};
> +
> +/* P1 message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp1_cfg[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x54002, 0x101 },
> +	{ 0x54003, 0x190 },
> +	{ 0x54004, 0x2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, 0x14 },
> +	{ 0x54008, 0x121f },
> +	{ 0x54009, 0xc8 },
> +	{ 0x5400b, 0x2 },
> +	{ 0x5400f, 0x100 },
> +	{ 0x54012, 0x310 },
> +	{ 0x54019, 0x84 },
> +	{ 0x5401a, 0x33 },
> +	{ 0x5401b, 0x4866 },
> +	{ 0x5401c, 0x4800 },
> +	{ 0x5401e, 0x16 },
> +	{ 0x5401f, 0x84 },
> +	{ 0x54020, 0x33 },
> +	{ 0x54021, 0x4866 },
> +	{ 0x54022, 0x4800 },
> +	{ 0x54024, 0x16 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, 0x3 },
> +	{ 0x54032, 0x8400 },
> +	{ 0x54033, 0x3300 },
> +	{ 0x54034, 0x6600 },
> +	{ 0x54035, 0x48 },
> +	{ 0x54036, 0x48 },
> +	{ 0x54037, 0x1600 },
> +	{ 0x54038, 0x8400 },
> +	{ 0x54039, 0x3300 },
> +	{ 0x5403a, 0x6600 },
> +	{ 0x5403b, 0x48 },
> +	{ 0x5403c, 0x48 },
> +	{ 0x5403d, 0x1600 },
> +	{ 0xd0000, 0x1 },
> +};
> +
> +/* P2 message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp2_cfg[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x54002, 0x102 },
> +	{ 0x54003, 0x64 },
> +	{ 0x54004, 0x2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, 0x14 },
> +	{ 0x54008, 0x121f },
> +	{ 0x54009, 0xc8 },
> +	{ 0x5400b, 0x2 },
> +	{ 0x5400f, 0x100 },
> +	{ 0x54012, 0x310 },
> +	{ 0x54019, 0x84 },
> +	{ 0x5401a, 0x33 },
> +	{ 0x5401b, 0x4866 },
> +	{ 0x5401c, 0x4800 },
> +	{ 0x5401e, 0x16 },
> +	{ 0x5401f, 0x84 },
> +	{ 0x54020, 0x33 },
> +	{ 0x54021, 0x4866 },
> +	{ 0x54022, 0x4800 },
> +	{ 0x54024, 0x16 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, 0x3 },
> +	{ 0x54032, 0x8400 },
> +	{ 0x54033, 0x3300 },
> +	{ 0x54034, 0x6600 },
> +	{ 0x54035, 0x48 },
> +	{ 0x54036, 0x48 },
> +	{ 0x54037, 0x1600 },
> +	{ 0x54038, 0x8400 },
> +	{ 0x54039, 0x3300 },
> +	{ 0x5403a, 0x6600 },
> +	{ 0x5403b, 0x48 },
> +	{ 0x5403c, 0x48 },
> +	{ 0x5403d, 0x1600 },
> +	{ 0xd0000, 0x1 },
> +};
> +
> +/* P0 2D message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x54003, 0xfa0 },
> +	{ 0x54004, 0x2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, 0x14 },
> +	{ 0x54008, 0x61 },
> +	{ 0x54009, 0xc8 },
> +	{ 0x5400b, 0x2 },
> +	{ 0x5400d, 0x100 },
> +	{ 0x5400f, 0x100 },
> +	{ 0x54010, 0x1f7f },
> +	{ 0x54012, 0x310 },
> +	{ 0x54019, 0x3ff4 },
> +	{ 0x5401a, 0x33 },
> +	{ 0x5401b, 0x4866 },
> +	{ 0x5401c, 0x4800 },
> +	{ 0x5401e, 0x16 },
> +	{ 0x5401f, 0x3ff4 },
> +	{ 0x54020, 0x33 },
> +	{ 0x54021, 0x4866 },
> +	{ 0x54022, 0x4800 },
> +	{ 0x54024, 0x16 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, 0x3 },
> +	{ 0x54032, 0xf400 },
> +	{ 0x54033, 0x333f },
> +	{ 0x54034, 0x6600 },
> +	{ 0x54035, 0x48 },
> +	{ 0x54036, 0x48 },
> +	{ 0x54037, 0x1600 },
> +	{ 0x54038, 0xf400 },
> +	{ 0x54039, 0x333f },
> +	{ 0x5403a, 0x6600 },
> +	{ 0x5403b, 0x48 },
> +	{ 0x5403c, 0x48 },
> +	{ 0x5403d, 0x1600 },
> +	{ 0xd0000, 0x1 },
> +};
> +
> +/* DRAM PHY init engine image */
> +struct dram_cfg_param ddr_phy_pie[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x90000, 0x10 },
> +	{ 0x90001, 0x400 },
> +	{ 0x90002, 0x10e },
> +	{ 0x90003, 0x0 },
> +	{ 0x90004, 0x0 },
> +	{ 0x90005, 0x8 },
> +	{ 0x90029, 0xb },
> +	{ 0x9002a, 0x480 },
> +	{ 0x9002b, 0x109 },
> +	{ 0x9002c, 0x8 },
> +	{ 0x9002d, 0x448 },
> +	{ 0x9002e, 0x139 },
> +	{ 0x9002f, 0x8 },
> +	{ 0x90030, 0x478 },
> +	{ 0x90031, 0x109 },
> +	{ 0x90032, 0x0 },
> +	{ 0x90033, 0xe8 },
> +	{ 0x90034, 0x109 },
> +	{ 0x90035, 0x2 },
> +	{ 0x90036, 0x10 },
> +	{ 0x90037, 0x139 },
> +	{ 0x90038, 0xb },
> +	{ 0x90039, 0x7c0 },
> +	{ 0x9003a, 0x139 },
> +	{ 0x9003b, 0x44 },
> +	{ 0x9003c, 0x633 },
> +	{ 0x9003d, 0x159 },
> +	{ 0x9003e, 0x14f },
> +	{ 0x9003f, 0x630 },
> +	{ 0x90040, 0x159 },
> +	{ 0x90041, 0x47 },
> +	{ 0x90042, 0x633 },
> +	{ 0x90043, 0x149 },
> +	{ 0x90044, 0x4f },
> +	{ 0x90045, 0x633 },
> +	{ 0x90046, 0x179 },
> +	{ 0x90047, 0x8 },
> +	{ 0x90048, 0xe0 },
> +	{ 0x90049, 0x109 },
> +	{ 0x9004a, 0x0 },
> +	{ 0x9004b, 0x7c8 },
> +	{ 0x9004c, 0x109 },
> +	{ 0x9004d, 0x0 },
> +	{ 0x9004e, 0x1 },
> +	{ 0x9004f, 0x8 },
> +	{ 0x90050, 0x0 },
> +	{ 0x90051, 0x45a },
> +	{ 0x90052, 0x9 },
> +	{ 0x90053, 0x0 },
> +	{ 0x90054, 0x448 },
> +	{ 0x90055, 0x109 },
> +	{ 0x90056, 0x40 },
> +	{ 0x90057, 0x633 },
> +	{ 0x90058, 0x179 },
> +	{ 0x90059, 0x1 },
> +	{ 0x9005a, 0x618 },
> +	{ 0x9005b, 0x109 },
> +	{ 0x9005c, 0x40c0 },
> +	{ 0x9005d, 0x633 },
> +	{ 0x9005e, 0x149 },
> +	{ 0x9005f, 0x8 },
> +	{ 0x90060, 0x4 },
> +	{ 0x90061, 0x48 },
> +	{ 0x90062, 0x4040 },
> +	{ 0x90063, 0x633 },
> +	{ 0x90064, 0x149 },
> +	{ 0x90065, 0x0 },
> +	{ 0x90066, 0x4 },
> +	{ 0x90067, 0x48 },
> +	{ 0x90068, 0x40 },
> +	{ 0x90069, 0x633 },
> +	{ 0x9006a, 0x149 },
> +	{ 0x9006b, 0x10 },
> +	{ 0x9006c, 0x4 },
> +	{ 0x9006d, 0x18 },
> +	{ 0x9006e, 0x0 },
> +	{ 0x9006f, 0x4 },
> +	{ 0x90070, 0x78 },
> +	{ 0x90071, 0x549 },
> +	{ 0x90072, 0x633 },
> +	{ 0x90073, 0x159 },
> +	{ 0x90074, 0xd49 },
> +	{ 0x90075, 0x633 },
> +	{ 0x90076, 0x159 },
> +	{ 0x90077, 0x94a },
> +	{ 0x90078, 0x633 },
> +	{ 0x90079, 0x159 },
> +	{ 0x9007a, 0x441 },
> +	{ 0x9007b, 0x633 },
> +	{ 0x9007c, 0x149 },
> +	{ 0x9007d, 0x42 },
> +	{ 0x9007e, 0x633 },
> +	{ 0x9007f, 0x149 },
> +	{ 0x90080, 0x1 },
> +	{ 0x90081, 0x633 },
> +	{ 0x90082, 0x149 },
> +	{ 0x90083, 0x0 },
> +	{ 0x90084, 0xe0 },
> +	{ 0x90085, 0x109 },
> +	{ 0x90086, 0xa },
> +	{ 0x90087, 0x10 },
> +	{ 0x90088, 0x109 },
> +	{ 0x90089, 0x9 },
> +	{ 0x9008a, 0x3c0 },
> +	{ 0x9008b, 0x149 },
> +	{ 0x9008c, 0x9 },
> +	{ 0x9008d, 0x3c0 },
> +	{ 0x9008e, 0x159 },
> +	{ 0x9008f, 0x18 },
> +	{ 0x90090, 0x10 },
> +	{ 0x90091, 0x109 },
> +	{ 0x90092, 0x0 },
> +	{ 0x90093, 0x3c0 },
> +	{ 0x90094, 0x109 },
> +	{ 0x90095, 0x18 },
> +	{ 0x90096, 0x4 },
> +	{ 0x90097, 0x48 },
> +	{ 0x90098, 0x18 },
> +	{ 0x90099, 0x4 },
> +	{ 0x9009a, 0x58 },
> +	{ 0x9009b, 0xb },
> +	{ 0x9009c, 0x10 },
> +	{ 0x9009d, 0x109 },
> +	{ 0x9009e, 0x1 },
> +	{ 0x9009f, 0x10 },
> +	{ 0x900a0, 0x109 },
> +	{ 0x900a1, 0x5 },
> +	{ 0x900a2, 0x7c0 },
> +	{ 0x900a3, 0x109 },
> +	{ 0x40000, 0x811 },
> +	{ 0x40020, 0x880 },
> +	{ 0x40040, 0x0 },
> +	{ 0x40060, 0x0 },
> +	{ 0x40001, 0x4008 },
> +	{ 0x40021, 0x83 },
> +	{ 0x40041, 0x4f },
> +	{ 0x40061, 0x0 },
> +	{ 0x40002, 0x4040 },
> +	{ 0x40022, 0x83 },
> +	{ 0x40042, 0x51 },
> +	{ 0x40062, 0x0 },
> +	{ 0x40003, 0x811 },
> +	{ 0x40023, 0x880 },
> +	{ 0x40043, 0x0 },
> +	{ 0x40063, 0x0 },
> +	{ 0x40004, 0x720 },
> +	{ 0x40024, 0xf },
> +	{ 0x40044, 0x1740 },
> +	{ 0x40064, 0x0 },
> +	{ 0x40005, 0x16 },
> +	{ 0x40025, 0x83 },
> +	{ 0x40045, 0x4b },
> +	{ 0x40065, 0x0 },
> +	{ 0x40006, 0x716 },
> +	{ 0x40026, 0xf },
> +	{ 0x40046, 0x2001 },
> +	{ 0x40066, 0x0 },
> +	{ 0x40007, 0x716 },
> +	{ 0x40027, 0xf },
> +	{ 0x40047, 0x2800 },
> +	{ 0x40067, 0x0 },
> +	{ 0x40008, 0x716 },
> +	{ 0x40028, 0xf },
> +	{ 0x40048, 0xf00 },
> +	{ 0x40068, 0x0 },
> +	{ 0x40009, 0x720 },
> +	{ 0x40029, 0xf },
> +	{ 0x40049, 0x1400 },
> +	{ 0x40069, 0x0 },
> +	{ 0x4000a, 0xe08 },
> +	{ 0x4002a, 0xc15 },
> +	{ 0x4004a, 0x0 },
> +	{ 0x4006a, 0x0 },
> +	{ 0x4000b, 0x625 },
> +	{ 0x4002b, 0x15 },
> +	{ 0x4004b, 0x0 },
> +	{ 0x4006b, 0x0 },
> +	{ 0x4000c, 0x4028 },
> +	{ 0x4002c, 0x80 },
> +	{ 0x4004c, 0x0 },
> +	{ 0x4006c, 0x0 },
> +	{ 0x4000d, 0xe08 },
> +	{ 0x4002d, 0xc1a },
> +	{ 0x4004d, 0x0 },
> +	{ 0x4006d, 0x0 },
> +	{ 0x4000e, 0x625 },
> +	{ 0x4002e, 0x1a },
> +	{ 0x4004e, 0x0 },
> +	{ 0x4006e, 0x0 },
> +	{ 0x4000f, 0x4040 },
> +	{ 0x4002f, 0x80 },
> +	{ 0x4004f, 0x0 },
> +	{ 0x4006f, 0x0 },
> +	{ 0x40010, 0x2604 },
> +	{ 0x40030, 0x15 },
> +	{ 0x40050, 0x0 },
> +	{ 0x40070, 0x0 },
> +	{ 0x40011, 0x708 },
> +	{ 0x40031, 0x5 },
> +	{ 0x40051, 0x0 },
> +	{ 0x40071, 0x2002 },
> +	{ 0x40012, 0x8 },
> +	{ 0x40032, 0x80 },
> +	{ 0x40052, 0x0 },
> +	{ 0x40072, 0x0 },
> +	{ 0x40013, 0x2604 },
> +	{ 0x40033, 0x1a },
> +	{ 0x40053, 0x0 },
> +	{ 0x40073, 0x0 },
> +	{ 0x40014, 0x708 },
> +	{ 0x40034, 0xa },
> +	{ 0x40054, 0x0 },
> +	{ 0x40074, 0x2002 },
> +	{ 0x40015, 0x4040 },
> +	{ 0x40035, 0x80 },
> +	{ 0x40055, 0x0 },
> +	{ 0x40075, 0x0 },
> +	{ 0x40016, 0x60a },
> +	{ 0x40036, 0x15 },
> +	{ 0x40056, 0x1200 },
> +	{ 0x40076, 0x0 },
> +	{ 0x40017, 0x61a },
> +	{ 0x40037, 0x15 },
> +	{ 0x40057, 0x1300 },
> +	{ 0x40077, 0x0 },
> +	{ 0x40018, 0x60a },
> +	{ 0x40038, 0x1a },
> +	{ 0x40058, 0x1200 },
> +	{ 0x40078, 0x0 },
> +	{ 0x40019, 0x642 },
> +	{ 0x40039, 0x1a },
> +	{ 0x40059, 0x1300 },
> +	{ 0x40079, 0x0 },
> +	{ 0x4001a, 0x4808 },
> +	{ 0x4003a, 0x880 },
> +	{ 0x4005a, 0x0 },
> +	{ 0x4007a, 0x0 },
> +	{ 0x900a4, 0x0 },
> +	{ 0x900a5, 0x790 },
> +	{ 0x900a6, 0x11a },
> +	{ 0x900a7, 0x8 },
> +	{ 0x900a8, 0x7aa },
> +	{ 0x900a9, 0x2a },
> +	{ 0x900aa, 0x10 },
> +	{ 0x900ab, 0x7b2 },
> +	{ 0x900ac, 0x2a },
> +	{ 0x900ad, 0x0 },
> +	{ 0x900ae, 0x7c8 },
> +	{ 0x900af, 0x109 },
> +	{ 0x900b0, 0x10 },
> +	{ 0x900b1, 0x10 },
> +	{ 0x900b2, 0x109 },
> +	{ 0x900b3, 0x10 },
> +	{ 0x900b4, 0x2a8 },
> +	{ 0x900b5, 0x129 },
> +	{ 0x900b6, 0x8 },
> +	{ 0x900b7, 0x370 },
> +	{ 0x900b8, 0x129 },
> +	{ 0x900b9, 0xa },
> +	{ 0x900ba, 0x3c8 },
> +	{ 0x900bb, 0x1a9 },
> +	{ 0x900bc, 0xc },
> +	{ 0x900bd, 0x408 },
> +	{ 0x900be, 0x199 },
> +	{ 0x900bf, 0x14 },
> +	{ 0x900c0, 0x790 },
> +	{ 0x900c1, 0x11a },
> +	{ 0x900c2, 0x8 },
> +	{ 0x900c3, 0x4 },
> +	{ 0x900c4, 0x18 },
> +	{ 0x900c5, 0xe },
> +	{ 0x900c6, 0x408 },
> +	{ 0x900c7, 0x199 },
> +	{ 0x900c8, 0x8 },
> +	{ 0x900c9, 0x8568 },
> +	{ 0x900ca, 0x108 },
> +	{ 0x900cb, 0x18 },
> +	{ 0x900cc, 0x790 },
> +	{ 0x900cd, 0x16a },
> +	{ 0x900ce, 0x8 },
> +	{ 0x900cf, 0x1d8 },
> +	{ 0x900d0, 0x169 },
> +	{ 0x900d1, 0x10 },
> +	{ 0x900d2, 0x8558 },
> +	{ 0x900d3, 0x168 },
> +	{ 0x900d4, 0x70 },
> +	{ 0x900d5, 0x788 },
> +	{ 0x900d6, 0x16a },
> +	{ 0x900d7, 0x1ff8 },
> +	{ 0x900d8, 0x85a8 },
> +	{ 0x900d9, 0x1e8 },
> +	{ 0x900da, 0x50 },
> +	{ 0x900db, 0x798 },
> +	{ 0x900dc, 0x16a },
> +	{ 0x900dd, 0x60 },
> +	{ 0x900de, 0x7a0 },
> +	{ 0x900df, 0x16a },
> +	{ 0x900e0, 0x8 },
> +	{ 0x900e1, 0x8310 },
> +	{ 0x900e2, 0x168 },
> +	{ 0x900e3, 0x8 },
> +	{ 0x900e4, 0xa310 },
> +	{ 0x900e5, 0x168 },
> +	{ 0x900e6, 0xa },
> +	{ 0x900e7, 0x408 },
> +	{ 0x900e8, 0x169 },
> +	{ 0x900e9, 0x6e },
> +	{ 0x900ea, 0x0 },
> +	{ 0x900eb, 0x68 },
> +	{ 0x900ec, 0x0 },
> +	{ 0x900ed, 0x408 },
> +	{ 0x900ee, 0x169 },
> +	{ 0x900ef, 0x0 },
> +	{ 0x900f0, 0x8310 },
> +	{ 0x900f1, 0x168 },
> +	{ 0x900f2, 0x0 },
> +	{ 0x900f3, 0xa310 },
> +	{ 0x900f4, 0x168 },
> +	{ 0x900f5, 0x1ff8 },
> +	{ 0x900f6, 0x85a8 },
> +	{ 0x900f7, 0x1e8 },
> +	{ 0x900f8, 0x68 },
> +	{ 0x900f9, 0x798 },
> +	{ 0x900fa, 0x16a },
> +	{ 0x900fb, 0x78 },
> +	{ 0x900fc, 0x7a0 },
> +	{ 0x900fd, 0x16a },
> +	{ 0x900fe, 0x68 },
> +	{ 0x900ff, 0x790 },
> +	{ 0x90100, 0x16a },
> +	{ 0x90101, 0x8 },
> +	{ 0x90102, 0x8b10 },
> +	{ 0x90103, 0x168 },
> +	{ 0x90104, 0x8 },
> +	{ 0x90105, 0xab10 },
> +	{ 0x90106, 0x168 },
> +	{ 0x90107, 0xa },
> +	{ 0x90108, 0x408 },
> +	{ 0x90109, 0x169 },
> +	{ 0x9010a, 0x58 },
> +	{ 0x9010b, 0x0 },
> +	{ 0x9010c, 0x68 },
> +	{ 0x9010d, 0x0 },
> +	{ 0x9010e, 0x408 },
> +	{ 0x9010f, 0x169 },
> +	{ 0x90110, 0x0 },
> +	{ 0x90111, 0x8b10 },
> +	{ 0x90112, 0x168 },
> +	{ 0x90113, 0x1 },
> +	{ 0x90114, 0xab10 },
> +	{ 0x90115, 0x168 },
> +	{ 0x90116, 0x0 },
> +	{ 0x90117, 0x1d8 },
> +	{ 0x90118, 0x169 },
> +	{ 0x90119, 0x80 },
> +	{ 0x9011a, 0x790 },
> +	{ 0x9011b, 0x16a },
> +	{ 0x9011c, 0x18 },
> +	{ 0x9011d, 0x7aa },
> +	{ 0x9011e, 0x6a },
> +	{ 0x9011f, 0xa },
> +	{ 0x90120, 0x0 },
> +	{ 0x90121, 0x1e9 },
> +	{ 0x90122, 0x8 },
> +	{ 0x90123, 0x8080 },
> +	{ 0x90124, 0x108 },
> +	{ 0x90125, 0xf },
> +	{ 0x90126, 0x408 },
> +	{ 0x90127, 0x169 },
> +	{ 0x90128, 0xc },
> +	{ 0x90129, 0x0 },
> +	{ 0x9012a, 0x68 },
> +	{ 0x9012b, 0x9 },
> +	{ 0x9012c, 0x0 },
> +	{ 0x9012d, 0x1a9 },
> +	{ 0x9012e, 0x0 },
> +	{ 0x9012f, 0x408 },
> +	{ 0x90130, 0x169 },
> +	{ 0x90131, 0x0 },
> +	{ 0x90132, 0x8080 },
> +	{ 0x90133, 0x108 },
> +	{ 0x90134, 0x8 },
> +	{ 0x90135, 0x7aa },
> +	{ 0x90136, 0x6a },
> +	{ 0x90137, 0x0 },
> +	{ 0x90138, 0x8568 },
> +	{ 0x90139, 0x108 },
> +	{ 0x9013a, 0xb7 },
> +	{ 0x9013b, 0x790 },
> +	{ 0x9013c, 0x16a },
> +	{ 0x9013d, 0x1f },
> +	{ 0x9013e, 0x0 },
> +	{ 0x9013f, 0x68 },
> +	{ 0x90140, 0x8 },
> +	{ 0x90141, 0x8558 },
> +	{ 0x90142, 0x168 },
> +	{ 0x90143, 0xf },
> +	{ 0x90144, 0x408 },
> +	{ 0x90145, 0x169 },
> +	{ 0x90146, 0xd },
> +	{ 0x90147, 0x0 },
> +	{ 0x90148, 0x68 },
> +	{ 0x90149, 0x0 },
> +	{ 0x9014a, 0x408 },
> +	{ 0x9014b, 0x169 },
> +	{ 0x9014c, 0x0 },
> +	{ 0x9014d, 0x8558 },
> +	{ 0x9014e, 0x168 },
> +	{ 0x9014f, 0x8 },
> +	{ 0x90150, 0x3c8 },
> +	{ 0x90151, 0x1a9 },
> +	{ 0x90152, 0x3 },
> +	{ 0x90153, 0x370 },
> +	{ 0x90154, 0x129 },
> +	{ 0x90155, 0x20 },
> +	{ 0x90156, 0x2aa },
> +	{ 0x90157, 0x9 },
> +	{ 0x90158, 0x0 },
> +	{ 0x90159, 0x400 },
> +	{ 0x9015a, 0x10e },
> +	{ 0x9015b, 0x8 },
> +	{ 0x9015c, 0xe8 },
> +	{ 0x9015d, 0x109 },
> +	{ 0x9015e, 0x0 },
> +	{ 0x9015f, 0x8140 },
> +	{ 0x90160, 0x10c },
> +	{ 0x90161, 0x10 },
> +	{ 0x90162, 0x8138 },
> +	{ 0x90163, 0x10c },
> +	{ 0x90164, 0x8 },
> +	{ 0x90165, 0x7c8 },
> +	{ 0x90166, 0x101 },
> +	{ 0x90167, 0x8 },
> +	{ 0x90168, 0x448 },
> +	{ 0x90169, 0x109 },
> +	{ 0x9016a, 0xf },
> +	{ 0x9016b, 0x7c0 },
> +	{ 0x9016c, 0x109 },
> +	{ 0x9016d, 0x0 },
> +	{ 0x9016e, 0xe8 },
> +	{ 0x9016f, 0x109 },
> +	{ 0x90170, 0x47 },
> +	{ 0x90171, 0x630 },
> +	{ 0x90172, 0x109 },
> +	{ 0x90173, 0x8 },
> +	{ 0x90174, 0x618 },
> +	{ 0x90175, 0x109 },
> +	{ 0x90176, 0x8 },
> +	{ 0x90177, 0xe0 },
> +	{ 0x90178, 0x109 },
> +	{ 0x90179, 0x0 },
> +	{ 0x9017a, 0x7c8 },
> +	{ 0x9017b, 0x109 },
> +	{ 0x9017c, 0x8 },
> +	{ 0x9017d, 0x8140 },
> +	{ 0x9017e, 0x10c },
> +	{ 0x9017f, 0x0 },
> +	{ 0x90180, 0x478 },
> +	{ 0x90181, 0x109 },
> +	{ 0x90182, 0x0 },
> +	{ 0x90183, 0x1 },
> +	{ 0x90184, 0x8 },
> +	{ 0x90185, 0x8 },
> +	{ 0x90186, 0x4 },
> +	{ 0x90187, 0x8 },
> +	{ 0x90188, 0x8 },
> +	{ 0x90189, 0x7c8 },
> +	{ 0x9018a, 0x101 },
> +	{ 0x90006, 0x0 },
> +	{ 0x90007, 0x0 },
> +	{ 0x90008, 0x8 },
> +	{ 0x90009, 0x0 },
> +	{ 0x9000a, 0x0 },
> +	{ 0x9000b, 0x0 },
> +	{ 0xd00e7, 0x400 },
> +	{ 0x90017, 0x0 },
> +	{ 0x9001f, 0x29 },
> +	{ 0x90026, 0x6a },
> +	{ 0x400d0, 0x0 },
> +	{ 0x400d1, 0x101 },
> +	{ 0x400d2, 0x105 },
> +	{ 0x400d3, 0x107 },
> +	{ 0x400d4, 0x10f },
> +	{ 0x400d5, 0x202 },
> +	{ 0x400d6, 0x20a },
> +	{ 0x400d7, 0x20b },
> +	{ 0x2003a, 0x2 },
> +	{ 0x2000b, 0x7d },
> +	{ 0x2000c, 0xfa },
> +	{ 0x2000d, 0x9c4 },
> +	{ 0x2000e, 0x2c },
> +	{ 0x12000b, 0xc },
> +	{ 0x12000c, 0x19 },
> +	{ 0x12000d, 0xfa },
> +	{ 0x12000e, 0x10 },
> +	{ 0x22000b, 0x3 },
> +	{ 0x22000c, 0x6 },
> +	{ 0x22000d, 0x3e },
> +	{ 0x22000e, 0x10 },
> +	{ 0x9000c, 0x0 },
> +	{ 0x9000d, 0x173 },
> +	{ 0x9000e, 0x60 },
> +	{ 0x9000f, 0x6110 },
> +	{ 0x90010, 0x2152 },
> +	{ 0x90011, 0xdfbd },
> +	{ 0x90012, 0x2060 },
> +	{ 0x90013, 0x6152 },
> +	{ 0x20010, 0x5a },
> +	{ 0x20011, 0x3 },
> +	{ 0x40080, 0xe0 },
> +	{ 0x40081, 0x12 },
> +	{ 0x40082, 0xe0 },
> +	{ 0x40083, 0x12 },
> +	{ 0x40084, 0xe0 },
> +	{ 0x40085, 0x12 },
> +	{ 0x140080, 0xe0 },
> +	{ 0x140081, 0x12 },
> +	{ 0x140082, 0xe0 },
> +	{ 0x140083, 0x12 },
> +	{ 0x140084, 0xe0 },
> +	{ 0x140085, 0x12 },
> +	{ 0x240080, 0xe0 },
> +	{ 0x240081, 0x12 },
> +	{ 0x240082, 0xe0 },
> +	{ 0x240083, 0x12 },
> +	{ 0x240084, 0xe0 },
> +	{ 0x240085, 0x12 },
> +	{ 0x400fd, 0xf },
> +	{ 0x10011, 0x1 },
> +	{ 0x10012, 0x1 },
> +	{ 0x10013, 0x180 },
> +	{ 0x10018, 0x1 },
> +	{ 0x10002, 0x6209 },
> +	{ 0x100b2, 0x1 },
> +	{ 0x101b4, 0x1 },
> +	{ 0x102b4, 0x1 },
> +	{ 0x103b4, 0x1 },
> +	{ 0x104b4, 0x1 },
> +	{ 0x105b4, 0x1 },
> +	{ 0x106b4, 0x1 },
> +	{ 0x107b4, 0x1 },
> +	{ 0x108b4, 0x1 },
> +	{ 0x11011, 0x1 },
> +	{ 0x11012, 0x1 },
> +	{ 0x11013, 0x180 },
> +	{ 0x11018, 0x1 },
> +	{ 0x11002, 0x6209 },
> +	{ 0x110b2, 0x1 },
> +	{ 0x111b4, 0x1 },
> +	{ 0x112b4, 0x1 },
> +	{ 0x113b4, 0x1 },
> +	{ 0x114b4, 0x1 },
> +	{ 0x115b4, 0x1 },
> +	{ 0x116b4, 0x1 },
> +	{ 0x117b4, 0x1 },
> +	{ 0x118b4, 0x1 },
> +	{ 0x12011, 0x1 },
> +	{ 0x12012, 0x1 },
> +	{ 0x12013, 0x180 },
> +	{ 0x12018, 0x1 },
> +	{ 0x12002, 0x6209 },
> +	{ 0x120b2, 0x1 },
> +	{ 0x121b4, 0x1 },
> +	{ 0x122b4, 0x1 },
> +	{ 0x123b4, 0x1 },
> +	{ 0x124b4, 0x1 },
> +	{ 0x125b4, 0x1 },
> +	{ 0x126b4, 0x1 },
> +	{ 0x127b4, 0x1 },
> +	{ 0x128b4, 0x1 },
> +	{ 0x13011, 0x1 },
> +	{ 0x13012, 0x1 },
> +	{ 0x13013, 0x180 },
> +	{ 0x13018, 0x1 },
> +	{ 0x13002, 0x6209 },
> +	{ 0x130b2, 0x1 },
> +	{ 0x131b4, 0x1 },
> +	{ 0x132b4, 0x1 },
> +	{ 0x133b4, 0x1 },
> +	{ 0x134b4, 0x1 },
> +	{ 0x135b4, 0x1 },
> +	{ 0x136b4, 0x1 },
> +	{ 0x137b4, 0x1 },
> +	{ 0x138b4, 0x1 },
> +	{ 0x20089, 0x1 },
> +	{ 0x20088, 0x19 },
> +	{ 0xc0080, 0x2 },
> +	{ 0xd0000, 0x1 }
> +};
> +
> +struct dram_fsp_msg ddr_dram_fsp_msg[] = {
> +	{
> +		/* P0 4000mts 1D */
> +		.drate = 4000,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp0_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
> +	},
> +	{
> +		/* P1 400mts 1D */
> +		.drate = 400,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp1_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
> +	},
> +	{
> +		/* P2 100mts 1D */
> +		.drate = 100,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp2_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
> +	},
> +	{
> +		/* P0 4000mts 2D */
> +		.drate = 4000,
> +		.fw_type = FW_2D_IMAGE,
> +		.fsp_cfg = ddr_fsp0_2d_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
> +	},
> +};
> +
> +/* ddr timing config params */
> +struct dram_timing_info dram_timing = {
> +	.ddrc_cfg = ddr_ddrc_cfg,
> +	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
> +	.ddrphy_cfg = ddr_ddrphy_cfg,
> +	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
> +	.fsp_msg = ddr_dram_fsp_msg,
> +	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
> +	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
> +	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
> +	.ddrphy_pie = ddr_phy_pie,
> +	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
> +	.fsp_table = { 4000, 400, 100, },
> +};
> +
> diff --git a/board/freescale/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_6G.c b/board/freescale/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_6G.c
> new file mode 100644
> index 0000000000..6ca18a3181
> --- /dev/null
> +++ b/board/freescale/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_6G.c
> @@ -0,0 +1,1875 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +#include <linux/kernel.h>
> +#include <asm/arch/ddr.h>
> +
> +struct dram_cfg_param ddr_ddrc_cfg[] = {
> +	/** Initialize DDRC registers **/
> +	{ 0x3d400304, 0x1 },
> +	{ 0x3d400030, 0x1 },
> +	{ 0x3d400000, 0xa3080020 },
> +	{ 0x3d400020, 0x1323 },
> +	{ 0x3d400024, 0x1e84800 },
> +	{ 0x3d400064, 0x7a0118 },
> +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
> +	{ 0x3d400070, 0x01027f44 },
> +#endif
> +	{ 0x3d4000d0, 0xc00307a3 },
> +	{ 0x3d4000d4, 0xc50000 },
> +	{ 0x3d4000dc, 0xf4003f },
> +	{ 0x3d4000e0, 0x330000 },
> +	{ 0x3d4000e8, 0x460048 },
> +	{ 0x3d4000ec, 0x150048 },
> +	{ 0x3d400100, 0x2028222a },
> +	{ 0x3d400104, 0x807bf },
> +	{ 0x3d40010c, 0xe0e000 },
> +	{ 0x3d400110, 0x12040a12 },
> +	{ 0x3d400114, 0x2050f0f },
> +	{ 0x3d400118, 0x1010009 },
> +	{ 0x3d40011c, 0x501 },
> +	{ 0x3d400130, 0x20800 },
> +	{ 0x3d400134, 0xe100002 },
> +	{ 0x3d400138, 0x120 },
> +	{ 0x3d400144, 0xc80064 },
> +	{ 0x3d400180, 0x3e8001e },
> +	{ 0x3d400184, 0x3207a12 },
> +	{ 0x3d400188, 0x0 },
> +	{ 0x3d400190, 0x49f820e },
> +	{ 0x3d400194, 0x80303 },
> +	{ 0x3d4001b4, 0x1f0e },
> +	{ 0x3d4001a0, 0xe0400018 },
> +	{ 0x3d4001a4, 0xdf00e4 },
> +	{ 0x3d4001a8, 0x80000000 },
> +	{ 0x3d4001b0, 0x11 },
> +	{ 0x3d4001c0, 0x1 },
> +	{ 0x3d4001c4, 0x1 },
> +	{ 0x3d4000f4, 0xc99 },
> +	{ 0x3d400108, 0x9121c1c },
> +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
> +	{ 0x3d400200, 0x13 },
> +	{ 0x3d40020c, 0x13131300 },
> +	{ 0x3d400210, 0x1f1f },
> +	{ 0x3d400204, 0x50505 },
> +	{ 0x3d400214, 0x4040404 },
> +	{ 0x3d400218, 0x68040404 },
> +#else
> +	{ 0x3d400200, 0x16 },
> +	{ 0x3d40020c, 0x0 },
> +	{ 0x3d400210, 0x1f1f },
> +	{ 0x3d400204, 0x80808 },
> +	{ 0x3d400214, 0x7070707 },
> +	{ 0x3d400218, 0x68070707 },
> +#endif
> +	{ 0x3d40021c, 0xf08 },
> +	{ 0x3d400250, 0x00001705 },
> +	{ 0x3d400254, 0x2c },
> +	{ 0x3d40025c, 0x4000030 },
> +	{ 0x3d400264, 0x900093e7 },
> +	{ 0x3d40026c, 0x2005574 },
> +	{ 0x3d400400, 0x111 },
> +	{ 0x3d400404, 0x72ff },
> +	{ 0x3d400408, 0x72ff },
> +	{ 0x3d400494, 0x2100e07 },
> +	{ 0x3d400498, 0x620096 },
> +	{ 0x3d40049c, 0x1100e07 },
> +	{ 0x3d4004a0, 0xc8012c },
> +	{ 0x3d402020, 0x21 },
> +	{ 0x3d402024, 0x7d00 },
> +	{ 0x3d402050, 0x20d040 },
> +	{ 0x3d402064, 0xc001c },
> +	{ 0x3d4020dc, 0x840000 },
> +	{ 0x3d4020e0, 0x310000 },
> +	{ 0x3d4020e8, 0x66004d },
> +	{ 0x3d4020ec, 0x16004d },
> +	{ 0x3d402100, 0xa040305 },
> +	{ 0x3d402104, 0x30407 },
> +	{ 0x3d402108, 0x203060b },
> +	{ 0x3d40210c, 0x505000 },
> +	{ 0x3d402110, 0x2040202 },
> +	{ 0x3d402114, 0x2030202 },
> +	{ 0x3d402118, 0x1010004 },
> +	{ 0x3d40211c, 0x301 },
> +	{ 0x3d402130, 0x20300 },
> +	{ 0x3d402134, 0xa100002 },
> +	{ 0x3d402138, 0x1d },
> +	{ 0x3d402144, 0x14000a },
> +	{ 0x3d402180, 0x640004 },
> +	{ 0x3d402190, 0x3818200 },
> +	{ 0x3d402194, 0x80303 },
> +	{ 0x3d4021b4, 0x100 },
> +	{ 0x3d4020f4, 0xc99 },
> +	{ 0x3d403020, 0x21 },
> +	{ 0x3d403024, 0x30d400 },
> +	{ 0x3d403050, 0x20d040 },
> +	{ 0x3d403064, 0x30007 },
> +	{ 0x3d4030dc, 0x840000 },
> +	{ 0x3d4030e0, 0x310000 },
> +	{ 0x3d4030e8, 0x66004d },
> +	{ 0x3d4030ec, 0x16004d },
> +	{ 0x3d403100, 0xa010102 },
> +	{ 0x3d403104, 0x30404 },
> +	{ 0x3d403108, 0x203060b },
> +	{ 0x3d40310c, 0x505000 },
> +	{ 0x3d403110, 0x2040202 },
> +	{ 0x3d403114, 0x2030202 },
> +	{ 0x3d403118, 0x1010004 },
> +	{ 0x3d40311c, 0x301 },
> +	{ 0x3d403130, 0x20300 },
> +	{ 0x3d403134, 0xa100002 },
> +	{ 0x3d403138, 0x8 },
> +	{ 0x3d403144, 0x50003 },
> +	{ 0x3d403180, 0x190004 },
> +	{ 0x3d403190, 0x3818200 },
> +	{ 0x3d403194, 0x80303 },
> +	{ 0x3d4031b4, 0x100 },
> +	{ 0x3d400028, 0x0 },
> +};
> +
> +/* PHY Initialize Configuration */
> +struct dram_cfg_param ddr_ddrphy_cfg[] = {
> +	{ 0x100a0, 0x0 },
> +	{ 0x100a1, 0x1 },
> +	{ 0x100a2, 0x2 },
> +	{ 0x100a3, 0x3 },
> +	{ 0x100a4, 0x4 },
> +	{ 0x100a5, 0x5 },
> +	{ 0x100a6, 0x6 },
> +	{ 0x100a7, 0x7 },
> +	{ 0x110a0, 0x0 },
> +	{ 0x110a1, 0x1 },
> +	{ 0x110a2, 0x3 },
> +	{ 0x110a3, 0x4 },
> +	{ 0x110a4, 0x5 },
> +	{ 0x110a5, 0x2 },
> +	{ 0x110a6, 0x7 },
> +	{ 0x110a7, 0x6 },
> +	{ 0x120a0, 0x0 },
> +	{ 0x120a1, 0x1 },
> +	{ 0x120a2, 0x3 },
> +	{ 0x120a3, 0x2 },
> +	{ 0x120a4, 0x5 },
> +	{ 0x120a5, 0x4 },
> +	{ 0x120a6, 0x7 },
> +	{ 0x120a7, 0x6 },
> +	{ 0x130a0, 0x0 },
> +	{ 0x130a1, 0x1 },
> +	{ 0x130a2, 0x2 },
> +	{ 0x130a3, 0x3 },
> +	{ 0x130a4, 0x4 },
> +	{ 0x130a5, 0x5 },
> +	{ 0x130a6, 0x6 },
> +	{ 0x130a7, 0x7 },
> +	{ 0x1005f, 0x1ff },
> +	{ 0x1015f, 0x1ff },
> +	{ 0x1105f, 0x1ff },
> +	{ 0x1115f, 0x1ff },
> +	{ 0x1205f, 0x1ff },
> +	{ 0x1215f, 0x1ff },
> +	{ 0x1305f, 0x1ff },
> +	{ 0x1315f, 0x1ff },
> +	{ 0x11005f, 0x1ff },
> +	{ 0x11015f, 0x1ff },
> +	{ 0x11105f, 0x1ff },
> +	{ 0x11115f, 0x1ff },
> +	{ 0x11205f, 0x1ff },
> +	{ 0x11215f, 0x1ff },
> +	{ 0x11305f, 0x1ff },
> +	{ 0x11315f, 0x1ff },
> +	{ 0x21005f, 0x1ff },
> +	{ 0x21015f, 0x1ff },
> +	{ 0x21105f, 0x1ff },
> +	{ 0x21115f, 0x1ff },
> +	{ 0x21205f, 0x1ff },
> +	{ 0x21215f, 0x1ff },
> +	{ 0x21305f, 0x1ff },
> +	{ 0x21315f, 0x1ff },
> +	{ 0x55, 0x1ff },
> +	{ 0x1055, 0x1ff },
> +	{ 0x2055, 0x1ff },
> +	{ 0x3055, 0x1ff },
> +	{ 0x4055, 0x1ff },
> +	{ 0x5055, 0x1ff },
> +	{ 0x6055, 0x1ff },
> +	{ 0x7055, 0x1ff },
> +	{ 0x8055, 0x1ff },
> +	{ 0x9055, 0x1ff },
> +	{ 0x200c5, 0x18 },
> +	{ 0x1200c5, 0x7 },
> +	{ 0x2200c5, 0x7 },
> +	{ 0x2002e, 0x2 },
> +	{ 0x12002e, 0x2 },
> +	{ 0x22002e, 0x2 },
> +	{ 0x90204, 0x0 },
> +	{ 0x190204, 0x0 },
> +	{ 0x290204, 0x0 },
> +	{ 0x20024, 0x1e3 },
> +	{ 0x2003a, 0x2 },
> +	{ 0x120024, 0x1e3 },
> +	{ 0x2003a, 0x2 },
> +	{ 0x220024, 0x1e3 },
> +	{ 0x2003a, 0x2 },
> +	{ 0x20056, 0x3 },
> +	{ 0x120056, 0x3 },
> +	{ 0x220056, 0x3 },
> +	{ 0x1004d, 0xe00 },
> +	{ 0x1014d, 0xe00 },
> +	{ 0x1104d, 0xe00 },
> +	{ 0x1114d, 0xe00 },
> +	{ 0x1204d, 0xe00 },
> +	{ 0x1214d, 0xe00 },
> +	{ 0x1304d, 0xe00 },
> +	{ 0x1314d, 0xe00 },
> +	{ 0x11004d, 0xe00 },
> +	{ 0x11014d, 0xe00 },
> +	{ 0x11104d, 0xe00 },
> +	{ 0x11114d, 0xe00 },
> +	{ 0x11204d, 0xe00 },
> +	{ 0x11214d, 0xe00 },
> +	{ 0x11304d, 0xe00 },
> +	{ 0x11314d, 0xe00 },
> +	{ 0x21004d, 0xe00 },
> +	{ 0x21014d, 0xe00 },
> +	{ 0x21104d, 0xe00 },
> +	{ 0x21114d, 0xe00 },
> +	{ 0x21204d, 0xe00 },
> +	{ 0x21214d, 0xe00 },
> +	{ 0x21304d, 0xe00 },
> +	{ 0x21314d, 0xe00 },
> +	{ 0x10049, 0xeba },
> +	{ 0x10149, 0xeba },
> +	{ 0x11049, 0xeba },
> +	{ 0x11149, 0xeba },
> +	{ 0x12049, 0xeba },
> +	{ 0x12149, 0xeba },
> +	{ 0x13049, 0xeba },
> +	{ 0x13149, 0xeba },
> +	{ 0x110049, 0xeba },
> +	{ 0x110149, 0xeba },
> +	{ 0x111049, 0xeba },
> +	{ 0x111149, 0xeba },
> +	{ 0x112049, 0xeba },
> +	{ 0x112149, 0xeba },
> +	{ 0x113049, 0xeba },
> +	{ 0x113149, 0xeba },
> +	{ 0x210049, 0xeba },
> +	{ 0x210149, 0xeba },
> +	{ 0x211049, 0xeba },
> +	{ 0x211149, 0xeba },
> +	{ 0x212049, 0xeba },
> +	{ 0x212149, 0xeba },
> +	{ 0x213049, 0xeba },
> +	{ 0x213149, 0xeba },
> +	{ 0x43, 0x63 },
> +	{ 0x1043, 0x63 },
> +	{ 0x2043, 0x63 },
> +	{ 0x3043, 0x63 },
> +	{ 0x4043, 0x63 },
> +	{ 0x5043, 0x63 },
> +	{ 0x6043, 0x63 },
> +	{ 0x7043, 0x63 },
> +	{ 0x8043, 0x63 },
> +	{ 0x9043, 0x63 },
> +	{ 0x20018, 0x3 },
> +	{ 0x20075, 0x4 },
> +	{ 0x20050, 0x0 },
> +	{ 0x20008, 0x3e8 },
> +	{ 0x120008, 0x64 },
> +	{ 0x220008, 0x19 },
> +	{ 0x20088, 0x9 },
> +	{ 0x200b2, 0x104 },
> +	{ 0x10043, 0x5a1 },
> +	{ 0x10143, 0x5a1 },
> +	{ 0x11043, 0x5a1 },
> +	{ 0x11143, 0x5a1 },
> +	{ 0x12043, 0x5a1 },
> +	{ 0x12143, 0x5a1 },
> +	{ 0x13043, 0x5a1 },
> +	{ 0x13143, 0x5a1 },
> +	{ 0x1200b2, 0x104 },
> +	{ 0x110043, 0x5a1 },
> +	{ 0x110143, 0x5a1 },
> +	{ 0x111043, 0x5a1 },
> +	{ 0x111143, 0x5a1 },
> +	{ 0x112043, 0x5a1 },
> +	{ 0x112143, 0x5a1 },
> +	{ 0x113043, 0x5a1 },
> +	{ 0x113143, 0x5a1 },
> +	{ 0x2200b2, 0x104 },
> +	{ 0x210043, 0x5a1 },
> +	{ 0x210143, 0x5a1 },
> +	{ 0x211043, 0x5a1 },
> +	{ 0x211143, 0x5a1 },
> +	{ 0x212043, 0x5a1 },
> +	{ 0x212143, 0x5a1 },
> +	{ 0x213043, 0x5a1 },
> +	{ 0x213143, 0x5a1 },
> +	{ 0x200fa, 0x1 },
> +	{ 0x1200fa, 0x1 },
> +	{ 0x2200fa, 0x1 },
> +	{ 0x20019, 0x1 },
> +	{ 0x120019, 0x1 },
> +	{ 0x220019, 0x1 },
> +	{ 0x200f0, 0x660 },
> +	{ 0x200f1, 0x0 },
> +	{ 0x200f2, 0x4444 },
> +	{ 0x200f3, 0x8888 },
> +	{ 0x200f4, 0x5665 },
> +	{ 0x200f5, 0x0 },
> +	{ 0x200f6, 0x0 },
> +	{ 0x200f7, 0xf000 },
> +	{ 0x20025, 0x0 },
> +	{ 0x2002d, 0x0 },
> +	{ 0x12002d, 0x0 },
> +	{ 0x22002d, 0x0 },
> +	{ 0x2007d, 0x212 },
> +	{ 0x12007d, 0x212 },
> +	{ 0x22007d, 0x212 },
> +	{ 0x2007c, 0x61 },
> +	{ 0x12007c, 0x61 },
> +	{ 0x22007c, 0x61 },
> +	{ 0x1004a, 0x500 },
> +	{ 0x1104a, 0x500 },
> +	{ 0x1204a, 0x500 },
> +	{ 0x1304a, 0x500 },
> +	{ 0x2002c, 0x0 },
> +};
> +
> +/* ddr phy trained csr */
> +struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
> +	{ 0x200b2, 0x0 },
> +	{ 0x1200b2, 0x0 },
> +	{ 0x2200b2, 0x0 },
> +	{ 0x200cb, 0x0 },
> +	{ 0x10043, 0x0 },
> +	{ 0x110043, 0x0 },
> +	{ 0x210043, 0x0 },
> +	{ 0x10143, 0x0 },
> +	{ 0x110143, 0x0 },
> +	{ 0x210143, 0x0 },
> +	{ 0x11043, 0x0 },
> +	{ 0x111043, 0x0 },
> +	{ 0x211043, 0x0 },
> +	{ 0x11143, 0x0 },
> +	{ 0x111143, 0x0 },
> +	{ 0x211143, 0x0 },
> +	{ 0x12043, 0x0 },
> +	{ 0x112043, 0x0 },
> +	{ 0x212043, 0x0 },
> +	{ 0x12143, 0x0 },
> +	{ 0x112143, 0x0 },
> +	{ 0x212143, 0x0 },
> +	{ 0x13043, 0x0 },
> +	{ 0x113043, 0x0 },
> +	{ 0x213043, 0x0 },
> +	{ 0x13143, 0x0 },
> +	{ 0x113143, 0x0 },
> +	{ 0x213143, 0x0 },
> +	{ 0x80, 0x0 },
> +	{ 0x100080, 0x0 },
> +	{ 0x200080, 0x0 },
> +	{ 0x1080, 0x0 },
> +	{ 0x101080, 0x0 },
> +	{ 0x201080, 0x0 },
> +	{ 0x2080, 0x0 },
> +	{ 0x102080, 0x0 },
> +	{ 0x202080, 0x0 },
> +	{ 0x3080, 0x0 },
> +	{ 0x103080, 0x0 },
> +	{ 0x203080, 0x0 },
> +	{ 0x4080, 0x0 },
> +	{ 0x104080, 0x0 },
> +	{ 0x204080, 0x0 },
> +	{ 0x5080, 0x0 },
> +	{ 0x105080, 0x0 },
> +	{ 0x205080, 0x0 },
> +	{ 0x6080, 0x0 },
> +	{ 0x106080, 0x0 },
> +	{ 0x206080, 0x0 },
> +	{ 0x7080, 0x0 },
> +	{ 0x107080, 0x0 },
> +	{ 0x207080, 0x0 },
> +	{ 0x8080, 0x0 },
> +	{ 0x108080, 0x0 },
> +	{ 0x208080, 0x0 },
> +	{ 0x9080, 0x0 },
> +	{ 0x109080, 0x0 },
> +	{ 0x209080, 0x0 },
> +	{ 0x10080, 0x0 },
> +	{ 0x110080, 0x0 },
> +	{ 0x210080, 0x0 },
> +	{ 0x10180, 0x0 },
> +	{ 0x110180, 0x0 },
> +	{ 0x210180, 0x0 },
> +	{ 0x11080, 0x0 },
> +	{ 0x111080, 0x0 },
> +	{ 0x211080, 0x0 },
> +	{ 0x11180, 0x0 },
> +	{ 0x111180, 0x0 },
> +	{ 0x211180, 0x0 },
> +	{ 0x12080, 0x0 },
> +	{ 0x112080, 0x0 },
> +	{ 0x212080, 0x0 },
> +	{ 0x12180, 0x0 },
> +	{ 0x112180, 0x0 },
> +	{ 0x212180, 0x0 },
> +	{ 0x13080, 0x0 },
> +	{ 0x113080, 0x0 },
> +	{ 0x213080, 0x0 },
> +	{ 0x13180, 0x0 },
> +	{ 0x113180, 0x0 },
> +	{ 0x213180, 0x0 },
> +	{ 0x10081, 0x0 },
> +	{ 0x110081, 0x0 },
> +	{ 0x210081, 0x0 },
> +	{ 0x10181, 0x0 },
> +	{ 0x110181, 0x0 },
> +	{ 0x210181, 0x0 },
> +	{ 0x11081, 0x0 },
> +	{ 0x111081, 0x0 },
> +	{ 0x211081, 0x0 },
> +	{ 0x11181, 0x0 },
> +	{ 0x111181, 0x0 },
> +	{ 0x211181, 0x0 },
> +	{ 0x12081, 0x0 },
> +	{ 0x112081, 0x0 },
> +	{ 0x212081, 0x0 },
> +	{ 0x12181, 0x0 },
> +	{ 0x112181, 0x0 },
> +	{ 0x212181, 0x0 },
> +	{ 0x13081, 0x0 },
> +	{ 0x113081, 0x0 },
> +	{ 0x213081, 0x0 },
> +	{ 0x13181, 0x0 },
> +	{ 0x113181, 0x0 },
> +	{ 0x213181, 0x0 },
> +	{ 0x100d0, 0x0 },
> +	{ 0x1100d0, 0x0 },
> +	{ 0x2100d0, 0x0 },
> +	{ 0x101d0, 0x0 },
> +	{ 0x1101d0, 0x0 },
> +	{ 0x2101d0, 0x0 },
> +	{ 0x110d0, 0x0 },
> +	{ 0x1110d0, 0x0 },
> +	{ 0x2110d0, 0x0 },
> +	{ 0x111d0, 0x0 },
> +	{ 0x1111d0, 0x0 },
> +	{ 0x2111d0, 0x0 },
> +	{ 0x120d0, 0x0 },
> +	{ 0x1120d0, 0x0 },
> +	{ 0x2120d0, 0x0 },
> +	{ 0x121d0, 0x0 },
> +	{ 0x1121d0, 0x0 },
> +	{ 0x2121d0, 0x0 },
> +	{ 0x130d0, 0x0 },
> +	{ 0x1130d0, 0x0 },
> +	{ 0x2130d0, 0x0 },
> +	{ 0x131d0, 0x0 },
> +	{ 0x1131d0, 0x0 },
> +	{ 0x2131d0, 0x0 },
> +	{ 0x100d1, 0x0 },
> +	{ 0x1100d1, 0x0 },
> +	{ 0x2100d1, 0x0 },
> +	{ 0x101d1, 0x0 },
> +	{ 0x1101d1, 0x0 },
> +	{ 0x2101d1, 0x0 },
> +	{ 0x110d1, 0x0 },
> +	{ 0x1110d1, 0x0 },
> +	{ 0x2110d1, 0x0 },
> +	{ 0x111d1, 0x0 },
> +	{ 0x1111d1, 0x0 },
> +	{ 0x2111d1, 0x0 },
> +	{ 0x120d1, 0x0 },
> +	{ 0x1120d1, 0x0 },
> +	{ 0x2120d1, 0x0 },
> +	{ 0x121d1, 0x0 },
> +	{ 0x1121d1, 0x0 },
> +	{ 0x2121d1, 0x0 },
> +	{ 0x130d1, 0x0 },
> +	{ 0x1130d1, 0x0 },
> +	{ 0x2130d1, 0x0 },
> +	{ 0x131d1, 0x0 },
> +	{ 0x1131d1, 0x0 },
> +	{ 0x2131d1, 0x0 },
> +	{ 0x10068, 0x0 },
> +	{ 0x10168, 0x0 },
> +	{ 0x10268, 0x0 },
> +	{ 0x10368, 0x0 },
> +	{ 0x10468, 0x0 },
> +	{ 0x10568, 0x0 },
> +	{ 0x10668, 0x0 },
> +	{ 0x10768, 0x0 },
> +	{ 0x10868, 0x0 },
> +	{ 0x11068, 0x0 },
> +	{ 0x11168, 0x0 },
> +	{ 0x11268, 0x0 },
> +	{ 0x11368, 0x0 },
> +	{ 0x11468, 0x0 },
> +	{ 0x11568, 0x0 },
> +	{ 0x11668, 0x0 },
> +	{ 0x11768, 0x0 },
> +	{ 0x11868, 0x0 },
> +	{ 0x12068, 0x0 },
> +	{ 0x12168, 0x0 },
> +	{ 0x12268, 0x0 },
> +	{ 0x12368, 0x0 },
> +	{ 0x12468, 0x0 },
> +	{ 0x12568, 0x0 },
> +	{ 0x12668, 0x0 },
> +	{ 0x12768, 0x0 },
> +	{ 0x12868, 0x0 },
> +	{ 0x13068, 0x0 },
> +	{ 0x13168, 0x0 },
> +	{ 0x13268, 0x0 },
> +	{ 0x13368, 0x0 },
> +	{ 0x13468, 0x0 },
> +	{ 0x13568, 0x0 },
> +	{ 0x13668, 0x0 },
> +	{ 0x13768, 0x0 },
> +	{ 0x13868, 0x0 },
> +	{ 0x10069, 0x0 },
> +	{ 0x10169, 0x0 },
> +	{ 0x10269, 0x0 },
> +	{ 0x10369, 0x0 },
> +	{ 0x10469, 0x0 },
> +	{ 0x10569, 0x0 },
> +	{ 0x10669, 0x0 },
> +	{ 0x10769, 0x0 },
> +	{ 0x10869, 0x0 },
> +	{ 0x11069, 0x0 },
> +	{ 0x11169, 0x0 },
> +	{ 0x11269, 0x0 },
> +	{ 0x11369, 0x0 },
> +	{ 0x11469, 0x0 },
> +	{ 0x11569, 0x0 },
> +	{ 0x11669, 0x0 },
> +	{ 0x11769, 0x0 },
> +	{ 0x11869, 0x0 },
> +	{ 0x12069, 0x0 },
> +	{ 0x12169, 0x0 },
> +	{ 0x12269, 0x0 },
> +	{ 0x12369, 0x0 },
> +	{ 0x12469, 0x0 },
> +	{ 0x12569, 0x0 },
> +	{ 0x12669, 0x0 },
> +	{ 0x12769, 0x0 },
> +	{ 0x12869, 0x0 },
> +	{ 0x13069, 0x0 },
> +	{ 0x13169, 0x0 },
> +	{ 0x13269, 0x0 },
> +	{ 0x13369, 0x0 },
> +	{ 0x13469, 0x0 },
> +	{ 0x13569, 0x0 },
> +	{ 0x13669, 0x0 },
> +	{ 0x13769, 0x0 },
> +	{ 0x13869, 0x0 },
> +	{ 0x1008c, 0x0 },
> +	{ 0x11008c, 0x0 },
> +	{ 0x21008c, 0x0 },
> +	{ 0x1018c, 0x0 },
> +	{ 0x11018c, 0x0 },
> +	{ 0x21018c, 0x0 },
> +	{ 0x1108c, 0x0 },
> +	{ 0x11108c, 0x0 },
> +	{ 0x21108c, 0x0 },
> +	{ 0x1118c, 0x0 },
> +	{ 0x11118c, 0x0 },
> +	{ 0x21118c, 0x0 },
> +	{ 0x1208c, 0x0 },
> +	{ 0x11208c, 0x0 },
> +	{ 0x21208c, 0x0 },
> +	{ 0x1218c, 0x0 },
> +	{ 0x11218c, 0x0 },
> +	{ 0x21218c, 0x0 },
> +	{ 0x1308c, 0x0 },
> +	{ 0x11308c, 0x0 },
> +	{ 0x21308c, 0x0 },
> +	{ 0x1318c, 0x0 },
> +	{ 0x11318c, 0x0 },
> +	{ 0x21318c, 0x0 },
> +	{ 0x1008d, 0x0 },
> +	{ 0x11008d, 0x0 },
> +	{ 0x21008d, 0x0 },
> +	{ 0x1018d, 0x0 },
> +	{ 0x11018d, 0x0 },
> +	{ 0x21018d, 0x0 },
> +	{ 0x1108d, 0x0 },
> +	{ 0x11108d, 0x0 },
> +	{ 0x21108d, 0x0 },
> +	{ 0x1118d, 0x0 },
> +	{ 0x11118d, 0x0 },
> +	{ 0x21118d, 0x0 },
> +	{ 0x1208d, 0x0 },
> +	{ 0x11208d, 0x0 },
> +	{ 0x21208d, 0x0 },
> +	{ 0x1218d, 0x0 },
> +	{ 0x11218d, 0x0 },
> +	{ 0x21218d, 0x0 },
> +	{ 0x1308d, 0x0 },
> +	{ 0x11308d, 0x0 },
> +	{ 0x21308d, 0x0 },
> +	{ 0x1318d, 0x0 },
> +	{ 0x11318d, 0x0 },
> +	{ 0x21318d, 0x0 },
> +	{ 0x100c0, 0x0 },
> +	{ 0x1100c0, 0x0 },
> +	{ 0x2100c0, 0x0 },
> +	{ 0x101c0, 0x0 },
> +	{ 0x1101c0, 0x0 },
> +	{ 0x2101c0, 0x0 },
> +	{ 0x102c0, 0x0 },
> +	{ 0x1102c0, 0x0 },
> +	{ 0x2102c0, 0x0 },
> +	{ 0x103c0, 0x0 },
> +	{ 0x1103c0, 0x0 },
> +	{ 0x2103c0, 0x0 },
> +	{ 0x104c0, 0x0 },
> +	{ 0x1104c0, 0x0 },
> +	{ 0x2104c0, 0x0 },
> +	{ 0x105c0, 0x0 },
> +	{ 0x1105c0, 0x0 },
> +	{ 0x2105c0, 0x0 },
> +	{ 0x106c0, 0x0 },
> +	{ 0x1106c0, 0x0 },
> +	{ 0x2106c0, 0x0 },
> +	{ 0x107c0, 0x0 },
> +	{ 0x1107c0, 0x0 },
> +	{ 0x2107c0, 0x0 },
> +	{ 0x108c0, 0x0 },
> +	{ 0x1108c0, 0x0 },
> +	{ 0x2108c0, 0x0 },
> +	{ 0x110c0, 0x0 },
> +	{ 0x1110c0, 0x0 },
> +	{ 0x2110c0, 0x0 },
> +	{ 0x111c0, 0x0 },
> +	{ 0x1111c0, 0x0 },
> +	{ 0x2111c0, 0x0 },
> +	{ 0x112c0, 0x0 },
> +	{ 0x1112c0, 0x0 },
> +	{ 0x2112c0, 0x0 },
> +	{ 0x113c0, 0x0 },
> +	{ 0x1113c0, 0x0 },
> +	{ 0x2113c0, 0x0 },
> +	{ 0x114c0, 0x0 },
> +	{ 0x1114c0, 0x0 },
> +	{ 0x2114c0, 0x0 },
> +	{ 0x115c0, 0x0 },
> +	{ 0x1115c0, 0x0 },
> +	{ 0x2115c0, 0x0 },
> +	{ 0x116c0, 0x0 },
> +	{ 0x1116c0, 0x0 },
> +	{ 0x2116c0, 0x0 },
> +	{ 0x117c0, 0x0 },
> +	{ 0x1117c0, 0x0 },
> +	{ 0x2117c0, 0x0 },
> +	{ 0x118c0, 0x0 },
> +	{ 0x1118c0, 0x0 },
> +	{ 0x2118c0, 0x0 },
> +	{ 0x120c0, 0x0 },
> +	{ 0x1120c0, 0x0 },
> +	{ 0x2120c0, 0x0 },
> +	{ 0x121c0, 0x0 },
> +	{ 0x1121c0, 0x0 },
> +	{ 0x2121c0, 0x0 },
> +	{ 0x122c0, 0x0 },
> +	{ 0x1122c0, 0x0 },
> +	{ 0x2122c0, 0x0 },
> +	{ 0x123c0, 0x0 },
> +	{ 0x1123c0, 0x0 },
> +	{ 0x2123c0, 0x0 },
> +	{ 0x124c0, 0x0 },
> +	{ 0x1124c0, 0x0 },
> +	{ 0x2124c0, 0x0 },
> +	{ 0x125c0, 0x0 },
> +	{ 0x1125c0, 0x0 },
> +	{ 0x2125c0, 0x0 },
> +	{ 0x126c0, 0x0 },
> +	{ 0x1126c0, 0x0 },
> +	{ 0x2126c0, 0x0 },
> +	{ 0x127c0, 0x0 },
> +	{ 0x1127c0, 0x0 },
> +	{ 0x2127c0, 0x0 },
> +	{ 0x128c0, 0x0 },
> +	{ 0x1128c0, 0x0 },
> +	{ 0x2128c0, 0x0 },
> +	{ 0x130c0, 0x0 },
> +	{ 0x1130c0, 0x0 },
> +	{ 0x2130c0, 0x0 },
> +	{ 0x131c0, 0x0 },
> +	{ 0x1131c0, 0x0 },
> +	{ 0x2131c0, 0x0 },
> +	{ 0x132c0, 0x0 },
> +	{ 0x1132c0, 0x0 },
> +	{ 0x2132c0, 0x0 },
> +	{ 0x133c0, 0x0 },
> +	{ 0x1133c0, 0x0 },
> +	{ 0x2133c0, 0x0 },
> +	{ 0x134c0, 0x0 },
> +	{ 0x1134c0, 0x0 },
> +	{ 0x2134c0, 0x0 },
> +	{ 0x135c0, 0x0 },
> +	{ 0x1135c0, 0x0 },
> +	{ 0x2135c0, 0x0 },
> +	{ 0x136c0, 0x0 },
> +	{ 0x1136c0, 0x0 },
> +	{ 0x2136c0, 0x0 },
> +	{ 0x137c0, 0x0 },
> +	{ 0x1137c0, 0x0 },
> +	{ 0x2137c0, 0x0 },
> +	{ 0x138c0, 0x0 },
> +	{ 0x1138c0, 0x0 },
> +	{ 0x2138c0, 0x0 },
> +	{ 0x100c1, 0x0 },
> +	{ 0x1100c1, 0x0 },
> +	{ 0x2100c1, 0x0 },
> +	{ 0x101c1, 0x0 },
> +	{ 0x1101c1, 0x0 },
> +	{ 0x2101c1, 0x0 },
> +	{ 0x102c1, 0x0 },
> +	{ 0x1102c1, 0x0 },
> +	{ 0x2102c1, 0x0 },
> +	{ 0x103c1, 0x0 },
> +	{ 0x1103c1, 0x0 },
> +	{ 0x2103c1, 0x0 },
> +	{ 0x104c1, 0x0 },
> +	{ 0x1104c1, 0x0 },
> +	{ 0x2104c1, 0x0 },
> +	{ 0x105c1, 0x0 },
> +	{ 0x1105c1, 0x0 },
> +	{ 0x2105c1, 0x0 },
> +	{ 0x106c1, 0x0 },
> +	{ 0x1106c1, 0x0 },
> +	{ 0x2106c1, 0x0 },
> +	{ 0x107c1, 0x0 },
> +	{ 0x1107c1, 0x0 },
> +	{ 0x2107c1, 0x0 },
> +	{ 0x108c1, 0x0 },
> +	{ 0x1108c1, 0x0 },
> +	{ 0x2108c1, 0x0 },
> +	{ 0x110c1, 0x0 },
> +	{ 0x1110c1, 0x0 },
> +	{ 0x2110c1, 0x0 },
> +	{ 0x111c1, 0x0 },
> +	{ 0x1111c1, 0x0 },
> +	{ 0x2111c1, 0x0 },
> +	{ 0x112c1, 0x0 },
> +	{ 0x1112c1, 0x0 },
> +	{ 0x2112c1, 0x0 },
> +	{ 0x113c1, 0x0 },
> +	{ 0x1113c1, 0x0 },
> +	{ 0x2113c1, 0x0 },
> +	{ 0x114c1, 0x0 },
> +	{ 0x1114c1, 0x0 },
> +	{ 0x2114c1, 0x0 },
> +	{ 0x115c1, 0x0 },
> +	{ 0x1115c1, 0x0 },
> +	{ 0x2115c1, 0x0 },
> +	{ 0x116c1, 0x0 },
> +	{ 0x1116c1, 0x0 },
> +	{ 0x2116c1, 0x0 },
> +	{ 0x117c1, 0x0 },
> +	{ 0x1117c1, 0x0 },
> +	{ 0x2117c1, 0x0 },
> +	{ 0x118c1, 0x0 },
> +	{ 0x1118c1, 0x0 },
> +	{ 0x2118c1, 0x0 },
> +	{ 0x120c1, 0x0 },
> +	{ 0x1120c1, 0x0 },
> +	{ 0x2120c1, 0x0 },
> +	{ 0x121c1, 0x0 },
> +	{ 0x1121c1, 0x0 },
> +	{ 0x2121c1, 0x0 },
> +	{ 0x122c1, 0x0 },
> +	{ 0x1122c1, 0x0 },
> +	{ 0x2122c1, 0x0 },
> +	{ 0x123c1, 0x0 },
> +	{ 0x1123c1, 0x0 },
> +	{ 0x2123c1, 0x0 },
> +	{ 0x124c1, 0x0 },
> +	{ 0x1124c1, 0x0 },
> +	{ 0x2124c1, 0x0 },
> +	{ 0x125c1, 0x0 },
> +	{ 0x1125c1, 0x0 },
> +	{ 0x2125c1, 0x0 },
> +	{ 0x126c1, 0x0 },
> +	{ 0x1126c1, 0x0 },
> +	{ 0x2126c1, 0x0 },
> +	{ 0x127c1, 0x0 },
> +	{ 0x1127c1, 0x0 },
> +	{ 0x2127c1, 0x0 },
> +	{ 0x128c1, 0x0 },
> +	{ 0x1128c1, 0x0 },
> +	{ 0x2128c1, 0x0 },
> +	{ 0x130c1, 0x0 },
> +	{ 0x1130c1, 0x0 },
> +	{ 0x2130c1, 0x0 },
> +	{ 0x131c1, 0x0 },
> +	{ 0x1131c1, 0x0 },
> +	{ 0x2131c1, 0x0 },
> +	{ 0x132c1, 0x0 },
> +	{ 0x1132c1, 0x0 },
> +	{ 0x2132c1, 0x0 },
> +	{ 0x133c1, 0x0 },
> +	{ 0x1133c1, 0x0 },
> +	{ 0x2133c1, 0x0 },
> +	{ 0x134c1, 0x0 },
> +	{ 0x1134c1, 0x0 },
> +	{ 0x2134c1, 0x0 },
> +	{ 0x135c1, 0x0 },
> +	{ 0x1135c1, 0x0 },
> +	{ 0x2135c1, 0x0 },
> +	{ 0x136c1, 0x0 },
> +	{ 0x1136c1, 0x0 },
> +	{ 0x2136c1, 0x0 },
> +	{ 0x137c1, 0x0 },
> +	{ 0x1137c1, 0x0 },
> +	{ 0x2137c1, 0x0 },
> +	{ 0x138c1, 0x0 },
> +	{ 0x1138c1, 0x0 },
> +	{ 0x2138c1, 0x0 },
> +	{ 0x10020, 0x0 },
> +	{ 0x110020, 0x0 },
> +	{ 0x210020, 0x0 },
> +	{ 0x11020, 0x0 },
> +	{ 0x111020, 0x0 },
> +	{ 0x211020, 0x0 },
> +	{ 0x12020, 0x0 },
> +	{ 0x112020, 0x0 },
> +	{ 0x212020, 0x0 },
> +	{ 0x13020, 0x0 },
> +	{ 0x113020, 0x0 },
> +	{ 0x213020, 0x0 },
> +	{ 0x20072, 0x0 },
> +	{ 0x20073, 0x0 },
> +	{ 0x20074, 0x0 },
> +	{ 0x100aa, 0x0 },
> +	{ 0x110aa, 0x0 },
> +	{ 0x120aa, 0x0 },
> +	{ 0x130aa, 0x0 },
> +	{ 0x20010, 0x0 },
> +	{ 0x120010, 0x0 },
> +	{ 0x220010, 0x0 },
> +	{ 0x20011, 0x0 },
> +	{ 0x120011, 0x0 },
> +	{ 0x220011, 0x0 },
> +	{ 0x100ae, 0x0 },
> +	{ 0x1100ae, 0x0 },
> +	{ 0x2100ae, 0x0 },
> +	{ 0x100af, 0x0 },
> +	{ 0x1100af, 0x0 },
> +	{ 0x2100af, 0x0 },
> +	{ 0x110ae, 0x0 },
> +	{ 0x1110ae, 0x0 },
> +	{ 0x2110ae, 0x0 },
> +	{ 0x110af, 0x0 },
> +	{ 0x1110af, 0x0 },
> +	{ 0x2110af, 0x0 },
> +	{ 0x120ae, 0x0 },
> +	{ 0x1120ae, 0x0 },
> +	{ 0x2120ae, 0x0 },
> +	{ 0x120af, 0x0 },
> +	{ 0x1120af, 0x0 },
> +	{ 0x2120af, 0x0 },
> +	{ 0x130ae, 0x0 },
> +	{ 0x1130ae, 0x0 },
> +	{ 0x2130ae, 0x0 },
> +	{ 0x130af, 0x0 },
> +	{ 0x1130af, 0x0 },
> +	{ 0x2130af, 0x0 },
> +	{ 0x20020, 0x0 },
> +	{ 0x120020, 0x0 },
> +	{ 0x220020, 0x0 },
> +	{ 0x100a0, 0x0 },
> +	{ 0x100a1, 0x0 },
> +	{ 0x100a2, 0x0 },
> +	{ 0x100a3, 0x0 },
> +	{ 0x100a4, 0x0 },
> +	{ 0x100a5, 0x0 },
> +	{ 0x100a6, 0x0 },
> +	{ 0x100a7, 0x0 },
> +	{ 0x110a0, 0x0 },
> +	{ 0x110a1, 0x0 },
> +	{ 0x110a2, 0x0 },
> +	{ 0x110a3, 0x0 },
> +	{ 0x110a4, 0x0 },
> +	{ 0x110a5, 0x0 },
> +	{ 0x110a6, 0x0 },
> +	{ 0x110a7, 0x0 },
> +	{ 0x120a0, 0x0 },
> +	{ 0x120a1, 0x0 },
> +	{ 0x120a2, 0x0 },
> +	{ 0x120a3, 0x0 },
> +	{ 0x120a4, 0x0 },
> +	{ 0x120a5, 0x0 },
> +	{ 0x120a6, 0x0 },
> +	{ 0x120a7, 0x0 },
> +	{ 0x130a0, 0x0 },
> +	{ 0x130a1, 0x0 },
> +	{ 0x130a2, 0x0 },
> +	{ 0x130a3, 0x0 },
> +	{ 0x130a4, 0x0 },
> +	{ 0x130a5, 0x0 },
> +	{ 0x130a6, 0x0 },
> +	{ 0x130a7, 0x0 },
> +	{ 0x2007c, 0x0 },
> +	{ 0x12007c, 0x0 },
> +	{ 0x22007c, 0x0 },
> +	{ 0x2007d, 0x0 },
> +	{ 0x12007d, 0x0 },
> +	{ 0x22007d, 0x0 },
> +	{ 0x400fd, 0x0 },
> +	{ 0x400c0, 0x0 },
> +	{ 0x90201, 0x0 },
> +	{ 0x190201, 0x0 },
> +	{ 0x290201, 0x0 },
> +	{ 0x90202, 0x0 },
> +	{ 0x190202, 0x0 },
> +	{ 0x290202, 0x0 },
> +	{ 0x90203, 0x0 },
> +	{ 0x190203, 0x0 },
> +	{ 0x290203, 0x0 },
> +	{ 0x90204, 0x0 },
> +	{ 0x190204, 0x0 },
> +	{ 0x290204, 0x0 },
> +	{ 0x90205, 0x0 },
> +	{ 0x190205, 0x0 },
> +	{ 0x290205, 0x0 },
> +	{ 0x90206, 0x0 },
> +	{ 0x190206, 0x0 },
> +	{ 0x290206, 0x0 },
> +	{ 0x90207, 0x0 },
> +	{ 0x190207, 0x0 },
> +	{ 0x290207, 0x0 },
> +	{ 0x90208, 0x0 },
> +	{ 0x190208, 0x0 },
> +	{ 0x290208, 0x0 },
> +	{ 0x10062, 0x0 },
> +	{ 0x10162, 0x0 },
> +	{ 0x10262, 0x0 },
> +	{ 0x10362, 0x0 },
> +	{ 0x10462, 0x0 },
> +	{ 0x10562, 0x0 },
> +	{ 0x10662, 0x0 },
> +	{ 0x10762, 0x0 },
> +	{ 0x10862, 0x0 },
> +	{ 0x11062, 0x0 },
> +	{ 0x11162, 0x0 },
> +	{ 0x11262, 0x0 },
> +	{ 0x11362, 0x0 },
> +	{ 0x11462, 0x0 },
> +	{ 0x11562, 0x0 },
> +	{ 0x11662, 0x0 },
> +	{ 0x11762, 0x0 },
> +	{ 0x11862, 0x0 },
> +	{ 0x12062, 0x0 },
> +	{ 0x12162, 0x0 },
> +	{ 0x12262, 0x0 },
> +	{ 0x12362, 0x0 },
> +	{ 0x12462, 0x0 },
> +	{ 0x12562, 0x0 },
> +	{ 0x12662, 0x0 },
> +	{ 0x12762, 0x0 },
> +	{ 0x12862, 0x0 },
> +	{ 0x13062, 0x0 },
> +	{ 0x13162, 0x0 },
> +	{ 0x13262, 0x0 },
> +	{ 0x13362, 0x0 },
> +	{ 0x13462, 0x0 },
> +	{ 0x13562, 0x0 },
> +	{ 0x13662, 0x0 },
> +	{ 0x13762, 0x0 },
> +	{ 0x13862, 0x0 },
> +	{ 0x20077, 0x0 },
> +	{ 0x10001, 0x0 },
> +	{ 0x11001, 0x0 },
> +	{ 0x12001, 0x0 },
> +	{ 0x13001, 0x0 },
> +	{ 0x10040, 0x0 },
> +	{ 0x10140, 0x0 },
> +	{ 0x10240, 0x0 },
> +	{ 0x10340, 0x0 },
> +	{ 0x10440, 0x0 },
> +	{ 0x10540, 0x0 },
> +	{ 0x10640, 0x0 },
> +	{ 0x10740, 0x0 },
> +	{ 0x10840, 0x0 },
> +	{ 0x10030, 0x0 },
> +	{ 0x10130, 0x0 },
> +	{ 0x10230, 0x0 },
> +	{ 0x10330, 0x0 },
> +	{ 0x10430, 0x0 },
> +	{ 0x10530, 0x0 },
> +	{ 0x10630, 0x0 },
> +	{ 0x10730, 0x0 },
> +	{ 0x10830, 0x0 },
> +	{ 0x11040, 0x0 },
> +	{ 0x11140, 0x0 },
> +	{ 0x11240, 0x0 },
> +	{ 0x11340, 0x0 },
> +	{ 0x11440, 0x0 },
> +	{ 0x11540, 0x0 },
> +	{ 0x11640, 0x0 },
> +	{ 0x11740, 0x0 },
> +	{ 0x11840, 0x0 },
> +	{ 0x11030, 0x0 },
> +	{ 0x11130, 0x0 },
> +	{ 0x11230, 0x0 },
> +	{ 0x11330, 0x0 },
> +	{ 0x11430, 0x0 },
> +	{ 0x11530, 0x0 },
> +	{ 0x11630, 0x0 },
> +	{ 0x11730, 0x0 },
> +	{ 0x11830, 0x0 },
> +	{ 0x12040, 0x0 },
> +	{ 0x12140, 0x0 },
> +	{ 0x12240, 0x0 },
> +	{ 0x12340, 0x0 },
> +	{ 0x12440, 0x0 },
> +	{ 0x12540, 0x0 },
> +	{ 0x12640, 0x0 },
> +	{ 0x12740, 0x0 },
> +	{ 0x12840, 0x0 },
> +	{ 0x12030, 0x0 },
> +	{ 0x12130, 0x0 },
> +	{ 0x12230, 0x0 },
> +	{ 0x12330, 0x0 },
> +	{ 0x12430, 0x0 },
> +	{ 0x12530, 0x0 },
> +	{ 0x12630, 0x0 },
> +	{ 0x12730, 0x0 },
> +	{ 0x12830, 0x0 },
> +	{ 0x13040, 0x0 },
> +	{ 0x13140, 0x0 },
> +	{ 0x13240, 0x0 },
> +	{ 0x13340, 0x0 },
> +	{ 0x13440, 0x0 },
> +	{ 0x13540, 0x0 },
> +	{ 0x13640, 0x0 },
> +	{ 0x13740, 0x0 },
> +	{ 0x13840, 0x0 },
> +	{ 0x13030, 0x0 },
> +	{ 0x13130, 0x0 },
> +	{ 0x13230, 0x0 },
> +	{ 0x13330, 0x0 },
> +	{ 0x13430, 0x0 },
> +	{ 0x13530, 0x0 },
> +	{ 0x13630, 0x0 },
> +	{ 0x13730, 0x0 },
> +	{ 0x13830, 0x0 },
> +};
> +
> +/* P0 message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp0_cfg[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x54003, 0xfa0 },
> +	{ 0x54004, 0x2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, 0x14 },
> +	{ 0x54008, 0x131f },
> +	{ 0x54009, 0xc8 },
> +	{ 0x5400b, 0x2 },
> +	{ 0x5400f, 0x100 },
> +	{ 0x54012, 0x310 },
> +	{ 0x54019, 0x3ff4 },
> +	{ 0x5401a, 0x33 },
> +	{ 0x5401b, 0x4866 },
> +	{ 0x5401c, 0x4800 },
> +	{ 0x5401e, 0x16 },
> +	{ 0x5401f, 0x3ff4 },
> +	{ 0x54020, 0x33 },
> +	{ 0x54021, 0x4866 },
> +	{ 0x54022, 0x4800 },
> +	{ 0x54024, 0x16 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, 0x3 },
> +	{ 0x54032, 0xf400 },
> +	{ 0x54033, 0x333f },
> +	{ 0x54034, 0x6600 },
> +	{ 0x54035, 0x48 },
> +	{ 0x54036, 0x48 },
> +	{ 0x54037, 0x1600 },
> +	{ 0x54038, 0xf400 },
> +	{ 0x54039, 0x333f },
> +	{ 0x5403a, 0x6600 },
> +	{ 0x5403b, 0x48 },
> +	{ 0x5403c, 0x48 },
> +	{ 0x5403d, 0x1600 },
> +	{ 0xd0000, 0x1 },
> +};
> +
> +/* P1 message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp1_cfg[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x54002, 0x101 },
> +	{ 0x54003, 0x190 },
> +	{ 0x54004, 0x2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, 0x14 },
> +	{ 0x54008, 0x121f },
> +	{ 0x54009, 0xc8 },
> +	{ 0x5400b, 0x2 },
> +	{ 0x5400f, 0x100 },
> +	{ 0x54012, 0x310 },
> +	{ 0x54019, 0x84 },
> +	{ 0x5401a, 0x33 },
> +	{ 0x5401b, 0x4846 },
> +	{ 0x5401c, 0x4800 },
> +	{ 0x5401e, 0x15 },
> +	{ 0x5401f, 0x84 },
> +	{ 0x54020, 0x33 },
> +	{ 0x54021, 0x4846 },
> +	{ 0x54022, 0x4800 },
> +	{ 0x54024, 0x15 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, 0x3 },
> +	{ 0x54032, 0x8400 },
> +	{ 0x54033, 0x3300 },
> +	{ 0x54034, 0x4600 },
> +	{ 0x54035, 0x48 },
> +	{ 0x54036, 0x48 },
> +	{ 0x54037, 0x1500 },
> +	{ 0x54038, 0x8400 },
> +	{ 0x54039, 0x3300 },
> +	{ 0x5403a, 0x4600 },
> +	{ 0x5403b, 0x48 },
> +	{ 0x5403c, 0x48 },
> +	{ 0x5403d, 0x1500 },
> +	{ 0xd0000, 0x1 },
> +};
> +
> +/* P2 message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp2_cfg[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x54002, 0x102 },
> +	{ 0x54003, 0x64 },
> +	{ 0x54004, 0x2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, 0x14 },
> +	{ 0x54008, 0x121f },
> +	{ 0x54009, 0xc8 },
> +	{ 0x5400b, 0x2 },
> +	{ 0x5400f, 0x100 },
> +	{ 0x54012, 0x310 },
> +	{ 0x54019, 0x84 },
> +	{ 0x5401a, 0x33 },
> +	{ 0x5401b, 0x4846 },
> +	{ 0x5401c, 0x4800 },
> +	{ 0x5401e, 0x15 },
> +	{ 0x5401f, 0x84 },
> +	{ 0x54020, 0x33 },
> +	{ 0x54021, 0x4846 },
> +	{ 0x54022, 0x4800 },
> +	{ 0x54024, 0x15 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, 0x3 },
> +	{ 0x54032, 0x8400 },
> +	{ 0x54033, 0x3300 },
> +	{ 0x54034, 0x4600 },
> +	{ 0x54035, 0x48 },
> +	{ 0x54036, 0x48 },
> +	{ 0x54037, 0x1500 },
> +	{ 0x54038, 0x8400 },
> +	{ 0x54039, 0x3300 },
> +	{ 0x5403a, 0x4600 },
> +	{ 0x5403b, 0x48 },
> +	{ 0x5403c, 0x48 },
> +	{ 0x5403d, 0x1500 },
> +	{ 0xd0000, 0x1 },
> +};
> +
> +/* P0 2D message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x54003, 0xfa0 },
> +	{ 0x54004, 0x2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, 0x14 },
> +	{ 0x54008, 0x61 },
> +	{ 0x54009, 0xc8 },
> +	{ 0x5400b, 0x2 },
> +	{ 0x5400d, 0x100 },
> +	{ 0x5400f, 0x100 },
> +	{ 0x54010, 0x1f7f },
> +	{ 0x54012, 0x310 },
> +	{ 0x54019, 0x3ff4 },
> +	{ 0x5401a, 0x33 },
> +	{ 0x5401b, 0x4866 },
> +	{ 0x5401c, 0x4800 },
> +	{ 0x5401e, 0x16 },
> +	{ 0x5401f, 0x3ff4 },
> +	{ 0x54020, 0x33 },
> +	{ 0x54021, 0x4866 },
> +	{ 0x54022, 0x4800 },
> +	{ 0x54024, 0x16 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, 0x3 },
> +	{ 0x54032, 0xf400 },
> +	{ 0x54033, 0x333f },
> +	{ 0x54034, 0x6600 },
> +	{ 0x54035, 0x48 },
> +	{ 0x54036, 0x48 },
> +	{ 0x54037, 0x1600 },
> +	{ 0x54038, 0xf400 },
> +	{ 0x54039, 0x333f },
> +	{ 0x5403a, 0x6600 },
> +	{ 0x5403b, 0x48 },
> +	{ 0x5403c, 0x48 },
> +	{ 0x5403d, 0x1600 },
> +	{ 0xd0000, 0x1 },
> +};
> +
> +/* DRAM PHY init engine image */
> +struct dram_cfg_param ddr_phy_pie[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x90000, 0x10 },
> +	{ 0x90001, 0x400 },
> +	{ 0x90002, 0x10e },
> +	{ 0x90003, 0x0 },
> +	{ 0x90004, 0x0 },
> +	{ 0x90005, 0x8 },
> +	{ 0x90029, 0xb },
> +	{ 0x9002a, 0x480 },
> +	{ 0x9002b, 0x109 },
> +	{ 0x9002c, 0x8 },
> +	{ 0x9002d, 0x448 },
> +	{ 0x9002e, 0x139 },
> +	{ 0x9002f, 0x8 },
> +	{ 0x90030, 0x478 },
> +	{ 0x90031, 0x109 },
> +	{ 0x90032, 0x0 },
> +	{ 0x90033, 0xe8 },
> +	{ 0x90034, 0x109 },
> +	{ 0x90035, 0x2 },
> +	{ 0x90036, 0x10 },
> +	{ 0x90037, 0x139 },
> +	{ 0x90038, 0xb },
> +	{ 0x90039, 0x7c0 },
> +	{ 0x9003a, 0x139 },
> +	{ 0x9003b, 0x44 },
> +	{ 0x9003c, 0x633 },
> +	{ 0x9003d, 0x159 },
> +	{ 0x9003e, 0x14f },
> +	{ 0x9003f, 0x630 },
> +	{ 0x90040, 0x159 },
> +	{ 0x90041, 0x47 },
> +	{ 0x90042, 0x633 },
> +	{ 0x90043, 0x149 },
> +	{ 0x90044, 0x4f },
> +	{ 0x90045, 0x633 },
> +	{ 0x90046, 0x179 },
> +	{ 0x90047, 0x8 },
> +	{ 0x90048, 0xe0 },
> +	{ 0x90049, 0x109 },
> +	{ 0x9004a, 0x0 },
> +	{ 0x9004b, 0x7c8 },
> +	{ 0x9004c, 0x109 },
> +	{ 0x9004d, 0x0 },
> +	{ 0x9004e, 0x1 },
> +	{ 0x9004f, 0x8 },
> +	{ 0x90050, 0x0 },
> +	{ 0x90051, 0x45a },
> +	{ 0x90052, 0x9 },
> +	{ 0x90053, 0x0 },
> +	{ 0x90054, 0x448 },
> +	{ 0x90055, 0x109 },
> +	{ 0x90056, 0x40 },
> +	{ 0x90057, 0x633 },
> +	{ 0x90058, 0x179 },
> +	{ 0x90059, 0x1 },
> +	{ 0x9005a, 0x618 },
> +	{ 0x9005b, 0x109 },
> +	{ 0x9005c, 0x40c0 },
> +	{ 0x9005d, 0x633 },
> +	{ 0x9005e, 0x149 },
> +	{ 0x9005f, 0x8 },
> +	{ 0x90060, 0x4 },
> +	{ 0x90061, 0x48 },
> +	{ 0x90062, 0x4040 },
> +	{ 0x90063, 0x633 },
> +	{ 0x90064, 0x149 },
> +	{ 0x90065, 0x0 },
> +	{ 0x90066, 0x4 },
> +	{ 0x90067, 0x48 },
> +	{ 0x90068, 0x40 },
> +	{ 0x90069, 0x633 },
> +	{ 0x9006a, 0x149 },
> +	{ 0x9006b, 0x10 },
> +	{ 0x9006c, 0x4 },
> +	{ 0x9006d, 0x18 },
> +	{ 0x9006e, 0x0 },
> +	{ 0x9006f, 0x4 },
> +	{ 0x90070, 0x78 },
> +	{ 0x90071, 0x549 },
> +	{ 0x90072, 0x633 },
> +	{ 0x90073, 0x159 },
> +	{ 0x90074, 0xd49 },
> +	{ 0x90075, 0x633 },
> +	{ 0x90076, 0x159 },
> +	{ 0x90077, 0x94a },
> +	{ 0x90078, 0x633 },
> +	{ 0x90079, 0x159 },
> +	{ 0x9007a, 0x441 },
> +	{ 0x9007b, 0x633 },
> +	{ 0x9007c, 0x149 },
> +	{ 0x9007d, 0x42 },
> +	{ 0x9007e, 0x633 },
> +	{ 0x9007f, 0x149 },
> +	{ 0x90080, 0x1 },
> +	{ 0x90081, 0x633 },
> +	{ 0x90082, 0x149 },
> +	{ 0x90083, 0x0 },
> +	{ 0x90084, 0xe0 },
> +	{ 0x90085, 0x109 },
> +	{ 0x90086, 0xa },
> +	{ 0x90087, 0x10 },
> +	{ 0x90088, 0x109 },
> +	{ 0x90089, 0x9 },
> +	{ 0x9008a, 0x3c0 },
> +	{ 0x9008b, 0x149 },
> +	{ 0x9008c, 0x9 },
> +	{ 0x9008d, 0x3c0 },
> +	{ 0x9008e, 0x159 },
> +	{ 0x9008f, 0x18 },
> +	{ 0x90090, 0x10 },
> +	{ 0x90091, 0x109 },
> +	{ 0x90092, 0x0 },
> +	{ 0x90093, 0x3c0 },
> +	{ 0x90094, 0x109 },
> +	{ 0x90095, 0x18 },
> +	{ 0x90096, 0x4 },
> +	{ 0x90097, 0x48 },
> +	{ 0x90098, 0x18 },
> +	{ 0x90099, 0x4 },
> +	{ 0x9009a, 0x58 },
> +	{ 0x9009b, 0xb },
> +	{ 0x9009c, 0x10 },
> +	{ 0x9009d, 0x109 },
> +	{ 0x9009e, 0x1 },
> +	{ 0x9009f, 0x10 },
> +	{ 0x900a0, 0x109 },
> +	{ 0x900a1, 0x5 },
> +	{ 0x900a2, 0x7c0 },
> +	{ 0x900a3, 0x109 },
> +	{ 0x40000, 0x811 },
> +	{ 0x40020, 0x880 },
> +	{ 0x40040, 0x0 },
> +	{ 0x40060, 0x0 },
> +	{ 0x40001, 0x4008 },
> +	{ 0x40021, 0x83 },
> +	{ 0x40041, 0x4f },
> +	{ 0x40061, 0x0 },
> +	{ 0x40002, 0x4040 },
> +	{ 0x40022, 0x83 },
> +	{ 0x40042, 0x51 },
> +	{ 0x40062, 0x0 },
> +	{ 0x40003, 0x811 },
> +	{ 0x40023, 0x880 },
> +	{ 0x40043, 0x0 },
> +	{ 0x40063, 0x0 },
> +	{ 0x40004, 0x720 },
> +	{ 0x40024, 0xf },
> +	{ 0x40044, 0x1740 },
> +	{ 0x40064, 0x0 },
> +	{ 0x40005, 0x16 },
> +	{ 0x40025, 0x83 },
> +	{ 0x40045, 0x4b },
> +	{ 0x40065, 0x0 },
> +	{ 0x40006, 0x716 },
> +	{ 0x40026, 0xf },
> +	{ 0x40046, 0x2001 },
> +	{ 0x40066, 0x0 },
> +	{ 0x40007, 0x716 },
> +	{ 0x40027, 0xf },
> +	{ 0x40047, 0x2800 },
> +	{ 0x40067, 0x0 },
> +	{ 0x40008, 0x716 },
> +	{ 0x40028, 0xf },
> +	{ 0x40048, 0xf00 },
> +	{ 0x40068, 0x0 },
> +	{ 0x40009, 0x720 },
> +	{ 0x40029, 0xf },
> +	{ 0x40049, 0x1400 },
> +	{ 0x40069, 0x0 },
> +	{ 0x4000a, 0xe08 },
> +	{ 0x4002a, 0xc15 },
> +	{ 0x4004a, 0x0 },
> +	{ 0x4006a, 0x0 },
> +	{ 0x4000b, 0x625 },
> +	{ 0x4002b, 0x15 },
> +	{ 0x4004b, 0x0 },
> +	{ 0x4006b, 0x0 },
> +	{ 0x4000c, 0x4028 },
> +	{ 0x4002c, 0x80 },
> +	{ 0x4004c, 0x0 },
> +	{ 0x4006c, 0x0 },
> +	{ 0x4000d, 0xe08 },
> +	{ 0x4002d, 0xc1a },
> +	{ 0x4004d, 0x0 },
> +	{ 0x4006d, 0x0 },
> +	{ 0x4000e, 0x625 },
> +	{ 0x4002e, 0x1a },
> +	{ 0x4004e, 0x0 },
> +	{ 0x4006e, 0x0 },
> +	{ 0x4000f, 0x4040 },
> +	{ 0x4002f, 0x80 },
> +	{ 0x4004f, 0x0 },
> +	{ 0x4006f, 0x0 },
> +	{ 0x40010, 0x2604 },
> +	{ 0x40030, 0x15 },
> +	{ 0x40050, 0x0 },
> +	{ 0x40070, 0x0 },
> +	{ 0x40011, 0x708 },
> +	{ 0x40031, 0x5 },
> +	{ 0x40051, 0x0 },
> +	{ 0x40071, 0x2002 },
> +	{ 0x40012, 0x8 },
> +	{ 0x40032, 0x80 },
> +	{ 0x40052, 0x0 },
> +	{ 0x40072, 0x0 },
> +	{ 0x40013, 0x2604 },
> +	{ 0x40033, 0x1a },
> +	{ 0x40053, 0x0 },
> +	{ 0x40073, 0x0 },
> +	{ 0x40014, 0x708 },
> +	{ 0x40034, 0xa },
> +	{ 0x40054, 0x0 },
> +	{ 0x40074, 0x2002 },
> +	{ 0x40015, 0x4040 },
> +	{ 0x40035, 0x80 },
> +	{ 0x40055, 0x0 },
> +	{ 0x40075, 0x0 },
> +	{ 0x40016, 0x60a },
> +	{ 0x40036, 0x15 },
> +	{ 0x40056, 0x1200 },
> +	{ 0x40076, 0x0 },
> +	{ 0x40017, 0x61a },
> +	{ 0x40037, 0x15 },
> +	{ 0x40057, 0x1300 },
> +	{ 0x40077, 0x0 },
> +	{ 0x40018, 0x60a },
> +	{ 0x40038, 0x1a },
> +	{ 0x40058, 0x1200 },
> +	{ 0x40078, 0x0 },
> +	{ 0x40019, 0x642 },
> +	{ 0x40039, 0x1a },
> +	{ 0x40059, 0x1300 },
> +	{ 0x40079, 0x0 },
> +	{ 0x4001a, 0x4808 },
> +	{ 0x4003a, 0x880 },
> +	{ 0x4005a, 0x0 },
> +	{ 0x4007a, 0x0 },
> +	{ 0x900a4, 0x0 },
> +	{ 0x900a5, 0x790 },
> +	{ 0x900a6, 0x11a },
> +	{ 0x900a7, 0x8 },
> +	{ 0x900a8, 0x7aa },
> +	{ 0x900a9, 0x2a },
> +	{ 0x900aa, 0x10 },
> +	{ 0x900ab, 0x7b2 },
> +	{ 0x900ac, 0x2a },
> +	{ 0x900ad, 0x0 },
> +	{ 0x900ae, 0x7c8 },
> +	{ 0x900af, 0x109 },
> +	{ 0x900b0, 0x10 },
> +	{ 0x900b1, 0x10 },
> +	{ 0x900b2, 0x109 },
> +	{ 0x900b3, 0x10 },
> +	{ 0x900b4, 0x2a8 },
> +	{ 0x900b5, 0x129 },
> +	{ 0x900b6, 0x8 },
> +	{ 0x900b7, 0x370 },
> +	{ 0x900b8, 0x129 },
> +	{ 0x900b9, 0xa },
> +	{ 0x900ba, 0x3c8 },
> +	{ 0x900bb, 0x1a9 },
> +	{ 0x900bc, 0xc },
> +	{ 0x900bd, 0x408 },
> +	{ 0x900be, 0x199 },
> +	{ 0x900bf, 0x14 },
> +	{ 0x900c0, 0x790 },
> +	{ 0x900c1, 0x11a },
> +	{ 0x900c2, 0x8 },
> +	{ 0x900c3, 0x4 },
> +	{ 0x900c4, 0x18 },
> +	{ 0x900c5, 0xe },
> +	{ 0x900c6, 0x408 },
> +	{ 0x900c7, 0x199 },
> +	{ 0x900c8, 0x8 },
> +	{ 0x900c9, 0x8568 },
> +	{ 0x900ca, 0x108 },
> +	{ 0x900cb, 0x18 },
> +	{ 0x900cc, 0x790 },
> +	{ 0x900cd, 0x16a },
> +	{ 0x900ce, 0x8 },
> +	{ 0x900cf, 0x1d8 },
> +	{ 0x900d0, 0x169 },
> +	{ 0x900d1, 0x10 },
> +	{ 0x900d2, 0x8558 },
> +	{ 0x900d3, 0x168 },
> +	{ 0x900d4, 0x70 },
> +	{ 0x900d5, 0x788 },
> +	{ 0x900d6, 0x16a },
> +	{ 0x900d7, 0x1ff8 },
> +	{ 0x900d8, 0x85a8 },
> +	{ 0x900d9, 0x1e8 },
> +	{ 0x900da, 0x50 },
> +	{ 0x900db, 0x798 },
> +	{ 0x900dc, 0x16a },
> +	{ 0x900dd, 0x60 },
> +	{ 0x900de, 0x7a0 },
> +	{ 0x900df, 0x16a },
> +	{ 0x900e0, 0x8 },
> +	{ 0x900e1, 0x8310 },
> +	{ 0x900e2, 0x168 },
> +	{ 0x900e3, 0x8 },
> +	{ 0x900e4, 0xa310 },
> +	{ 0x900e5, 0x168 },
> +	{ 0x900e6, 0xa },
> +	{ 0x900e7, 0x408 },
> +	{ 0x900e8, 0x169 },
> +	{ 0x900e9, 0x6e },
> +	{ 0x900ea, 0x0 },
> +	{ 0x900eb, 0x68 },
> +	{ 0x900ec, 0x0 },
> +	{ 0x900ed, 0x408 },
> +	{ 0x900ee, 0x169 },
> +	{ 0x900ef, 0x0 },
> +	{ 0x900f0, 0x8310 },
> +	{ 0x900f1, 0x168 },
> +	{ 0x900f2, 0x0 },
> +	{ 0x900f3, 0xa310 },
> +	{ 0x900f4, 0x168 },
> +	{ 0x900f5, 0x1ff8 },
> +	{ 0x900f6, 0x85a8 },
> +	{ 0x900f7, 0x1e8 },
> +	{ 0x900f8, 0x68 },
> +	{ 0x900f9, 0x798 },
> +	{ 0x900fa, 0x16a },
> +	{ 0x900fb, 0x78 },
> +	{ 0x900fc, 0x7a0 },
> +	{ 0x900fd, 0x16a },
> +	{ 0x900fe, 0x68 },
> +	{ 0x900ff, 0x790 },
> +	{ 0x90100, 0x16a },
> +	{ 0x90101, 0x8 },
> +	{ 0x90102, 0x8b10 },
> +	{ 0x90103, 0x168 },
> +	{ 0x90104, 0x8 },
> +	{ 0x90105, 0xab10 },
> +	{ 0x90106, 0x168 },
> +	{ 0x90107, 0xa },
> +	{ 0x90108, 0x408 },
> +	{ 0x90109, 0x169 },
> +	{ 0x9010a, 0x58 },
> +	{ 0x9010b, 0x0 },
> +	{ 0x9010c, 0x68 },
> +	{ 0x9010d, 0x0 },
> +	{ 0x9010e, 0x408 },
> +	{ 0x9010f, 0x169 },
> +	{ 0x90110, 0x0 },
> +	{ 0x90111, 0x8b10 },
> +	{ 0x90112, 0x168 },
> +	{ 0x90113, 0x1 },
> +	{ 0x90114, 0xab10 },
> +	{ 0x90115, 0x168 },
> +	{ 0x90116, 0x0 },
> +	{ 0x90117, 0x1d8 },
> +	{ 0x90118, 0x169 },
> +	{ 0x90119, 0x80 },
> +	{ 0x9011a, 0x790 },
> +	{ 0x9011b, 0x16a },
> +	{ 0x9011c, 0x18 },
> +	{ 0x9011d, 0x7aa },
> +	{ 0x9011e, 0x6a },
> +	{ 0x9011f, 0xa },
> +	{ 0x90120, 0x0 },
> +	{ 0x90121, 0x1e9 },
> +	{ 0x90122, 0x8 },
> +	{ 0x90123, 0x8080 },
> +	{ 0x90124, 0x108 },
> +	{ 0x90125, 0xf },
> +	{ 0x90126, 0x408 },
> +	{ 0x90127, 0x169 },
> +	{ 0x90128, 0xc },
> +	{ 0x90129, 0x0 },
> +	{ 0x9012a, 0x68 },
> +	{ 0x9012b, 0x9 },
> +	{ 0x9012c, 0x0 },
> +	{ 0x9012d, 0x1a9 },
> +	{ 0x9012e, 0x0 },
> +	{ 0x9012f, 0x408 },
> +	{ 0x90130, 0x169 },
> +	{ 0x90131, 0x0 },
> +	{ 0x90132, 0x8080 },
> +	{ 0x90133, 0x108 },
> +	{ 0x90134, 0x8 },
> +	{ 0x90135, 0x7aa },
> +	{ 0x90136, 0x6a },
> +	{ 0x90137, 0x0 },
> +	{ 0x90138, 0x8568 },
> +	{ 0x90139, 0x108 },
> +	{ 0x9013a, 0xb7 },
> +	{ 0x9013b, 0x790 },
> +	{ 0x9013c, 0x16a },
> +	{ 0x9013d, 0x1f },
> +	{ 0x9013e, 0x0 },
> +	{ 0x9013f, 0x68 },
> +	{ 0x90140, 0x8 },
> +	{ 0x90141, 0x8558 },
> +	{ 0x90142, 0x168 },
> +	{ 0x90143, 0xf },
> +	{ 0x90144, 0x408 },
> +	{ 0x90145, 0x169 },
> +	{ 0x90146, 0xd },
> +	{ 0x90147, 0x0 },
> +	{ 0x90148, 0x68 },
> +	{ 0x90149, 0x0 },
> +	{ 0x9014a, 0x408 },
> +	{ 0x9014b, 0x169 },
> +	{ 0x9014c, 0x0 },
> +	{ 0x9014d, 0x8558 },
> +	{ 0x9014e, 0x168 },
> +	{ 0x9014f, 0x8 },
> +	{ 0x90150, 0x3c8 },
> +	{ 0x90151, 0x1a9 },
> +	{ 0x90152, 0x3 },
> +	{ 0x90153, 0x370 },
> +	{ 0x90154, 0x129 },
> +	{ 0x90155, 0x20 },
> +	{ 0x90156, 0x2aa },
> +	{ 0x90157, 0x9 },
> +	{ 0x90158, 0x0 },
> +	{ 0x90159, 0x400 },
> +	{ 0x9015a, 0x10e },
> +	{ 0x9015b, 0x8 },
> +	{ 0x9015c, 0xe8 },
> +	{ 0x9015d, 0x109 },
> +	{ 0x9015e, 0x0 },
> +	{ 0x9015f, 0x8140 },
> +	{ 0x90160, 0x10c },
> +	{ 0x90161, 0x10 },
> +	{ 0x90162, 0x8138 },
> +	{ 0x90163, 0x10c },
> +	{ 0x90164, 0x8 },
> +	{ 0x90165, 0x7c8 },
> +	{ 0x90166, 0x101 },
> +	{ 0x90167, 0x8 },
> +	{ 0x90168, 0x448 },
> +	{ 0x90169, 0x109 },
> +	{ 0x9016a, 0xf },
> +	{ 0x9016b, 0x7c0 },
> +	{ 0x9016c, 0x109 },
> +	{ 0x9016d, 0x0 },
> +	{ 0x9016e, 0xe8 },
> +	{ 0x9016f, 0x109 },
> +	{ 0x90170, 0x47 },
> +	{ 0x90171, 0x630 },
> +	{ 0x90172, 0x109 },
> +	{ 0x90173, 0x8 },
> +	{ 0x90174, 0x618 },
> +	{ 0x90175, 0x109 },
> +	{ 0x90176, 0x8 },
> +	{ 0x90177, 0xe0 },
> +	{ 0x90178, 0x109 },
> +	{ 0x90179, 0x0 },
> +	{ 0x9017a, 0x7c8 },
> +	{ 0x9017b, 0x109 },
> +	{ 0x9017c, 0x8 },
> +	{ 0x9017d, 0x8140 },
> +	{ 0x9017e, 0x10c },
> +	{ 0x9017f, 0x0 },
> +	{ 0x90180, 0x478 },
> +	{ 0x90181, 0x109 },
> +	{ 0x90182, 0x0 },
> +	{ 0x90183, 0x1 },
> +	{ 0x90184, 0x8 },
> +	{ 0x90185, 0x8 },
> +	{ 0x90186, 0x4 },
> +	{ 0x90187, 0x8 },
> +	{ 0x90188, 0x8 },
> +	{ 0x90189, 0x7c8 },
> +	{ 0x9018a, 0x101 },
> +	{ 0x90006, 0x0 },
> +	{ 0x90007, 0x0 },
> +	{ 0x90008, 0x8 },
> +	{ 0x90009, 0x0 },
> +	{ 0x9000a, 0x0 },
> +	{ 0x9000b, 0x0 },
> +	{ 0xd00e7, 0x400 },
> +	{ 0x90017, 0x0 },
> +	{ 0x9001f, 0x29 },
> +	{ 0x90026, 0x6a },
> +	{ 0x400d0, 0x0 },
> +	{ 0x400d1, 0x101 },
> +	{ 0x400d2, 0x105 },
> +	{ 0x400d3, 0x107 },
> +	{ 0x400d4, 0x10f },
> +	{ 0x400d5, 0x202 },
> +	{ 0x400d6, 0x20a },
> +	{ 0x400d7, 0x20b },
> +	{ 0x2003a, 0x2 },
> +	{ 0x2000b, 0x7d },
> +	{ 0x2000c, 0xfa },
> +	{ 0x2000d, 0x9c4 },
> +	{ 0x2000e, 0x2c },
> +	{ 0x12000b, 0xc },
> +	{ 0x12000c, 0x19 },
> +	{ 0x12000d, 0xfa },
> +	{ 0x12000e, 0x10 },
> +	{ 0x22000b, 0x3 },
> +	{ 0x22000c, 0x6 },
> +	{ 0x22000d, 0x3e },
> +	{ 0x22000e, 0x10 },
> +	{ 0x9000c, 0x0 },
> +	{ 0x9000d, 0x173 },
> +	{ 0x9000e, 0x60 },
> +	{ 0x9000f, 0x6110 },
> +	{ 0x90010, 0x2152 },
> +	{ 0x90011, 0xdfbd },
> +	{ 0x90012, 0x2060 },
> +	{ 0x90013, 0x6152 },
> +	{ 0x20010, 0x5a },
> +	{ 0x20011, 0x3 },
> +	{ 0x40080, 0xe0 },
> +	{ 0x40081, 0x12 },
> +	{ 0x40082, 0xe0 },
> +	{ 0x40083, 0x12 },
> +	{ 0x40084, 0xe0 },
> +	{ 0x40085, 0x12 },
> +	{ 0x140080, 0xe0 },
> +	{ 0x140081, 0x12 },
> +	{ 0x140082, 0xe0 },
> +	{ 0x140083, 0x12 },
> +	{ 0x140084, 0xe0 },
> +	{ 0x140085, 0x12 },
> +	{ 0x240080, 0xe0 },
> +	{ 0x240081, 0x12 },
> +	{ 0x240082, 0xe0 },
> +	{ 0x240083, 0x12 },
> +	{ 0x240084, 0xe0 },
> +	{ 0x240085, 0x12 },
> +	{ 0x400fd, 0xf },
> +	{ 0x10011, 0x1 },
> +	{ 0x10012, 0x1 },
> +	{ 0x10013, 0x180 },
> +	{ 0x10018, 0x1 },
> +	{ 0x10002, 0x6209 },
> +	{ 0x100b2, 0x1 },
> +	{ 0x101b4, 0x1 },
> +	{ 0x102b4, 0x1 },
> +	{ 0x103b4, 0x1 },
> +	{ 0x104b4, 0x1 },
> +	{ 0x105b4, 0x1 },
> +	{ 0x106b4, 0x1 },
> +	{ 0x107b4, 0x1 },
> +	{ 0x108b4, 0x1 },
> +	{ 0x11011, 0x1 },
> +	{ 0x11012, 0x1 },
> +	{ 0x11013, 0x180 },
> +	{ 0x11018, 0x1 },
> +	{ 0x11002, 0x6209 },
> +	{ 0x110b2, 0x1 },
> +	{ 0x111b4, 0x1 },
> +	{ 0x112b4, 0x1 },
> +	{ 0x113b4, 0x1 },
> +	{ 0x114b4, 0x1 },
> +	{ 0x115b4, 0x1 },
> +	{ 0x116b4, 0x1 },
> +	{ 0x117b4, 0x1 },
> +	{ 0x118b4, 0x1 },
> +	{ 0x12011, 0x1 },
> +	{ 0x12012, 0x1 },
> +	{ 0x12013, 0x180 },
> +	{ 0x12018, 0x1 },
> +	{ 0x12002, 0x6209 },
> +	{ 0x120b2, 0x1 },
> +	{ 0x121b4, 0x1 },
> +	{ 0x122b4, 0x1 },
> +	{ 0x123b4, 0x1 },
> +	{ 0x124b4, 0x1 },
> +	{ 0x125b4, 0x1 },
> +	{ 0x126b4, 0x1 },
> +	{ 0x127b4, 0x1 },
> +	{ 0x128b4, 0x1 },
> +	{ 0x13011, 0x1 },
> +	{ 0x13012, 0x1 },
> +	{ 0x13013, 0x180 },
> +	{ 0x13018, 0x1 },
> +	{ 0x13002, 0x6209 },
> +	{ 0x130b2, 0x1 },
> +	{ 0x131b4, 0x1 },
> +	{ 0x132b4, 0x1 },
> +	{ 0x133b4, 0x1 },
> +	{ 0x134b4, 0x1 },
> +	{ 0x135b4, 0x1 },
> +	{ 0x136b4, 0x1 },
> +	{ 0x137b4, 0x1 },
> +	{ 0x138b4, 0x1 },
> +	{ 0x20089, 0x1 },
> +	{ 0x20088, 0x19 },
> +	{ 0xc0080, 0x2 },
> +	{ 0xd0000, 0x1 }
> +};
> +
> +struct dram_fsp_msg ddr_dram_fsp_msg[] = {
> +	{
> +		/* P0 4000mts 1D */
> +		.drate = 4000,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp0_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
> +	},
> +	{
> +		/* P1 400mts 1D */
> +		.drate = 400,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp1_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
> +	},
> +	{
> +		/* P2 100mts 1D */
> +		.drate = 100,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp2_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
> +	},
> +	{
> +		/* P0 4000mts 2D */
> +		.drate = 4000,
> +		.fw_type = FW_2D_IMAGE,
> +		.fsp_cfg = ddr_fsp0_2d_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
> +	},
> +};
> +
> +/* ddr timing config params */
> +struct dram_timing_info dram_timing = {
> +	.ddrc_cfg = ddr_ddrc_cfg,
> +	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
> +	.ddrphy_cfg = ddr_ddrphy_cfg,
> +	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
> +	.fsp_msg = ddr_dram_fsp_msg,
> +	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
> +	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
> +	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
> +	.ddrphy_pie = ddr_phy_pie,
> +	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
> +	.fsp_table = { 4000, 400, 100, },
> +};
> +
> +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
> +void board_dram_ecc_scrub(void)
> +{
> +	/* add inline scrb function MPlus spcific */
> +	/* scrub 0-1.75G */
> +	ddrc_inline_ecc_scrub(0x0, 0x1bffffff);
> +	/* scrub 2-3.75G */
> +	ddrc_inline_ecc_scrub(0x20000000, 0x3bffffff);
> +	/* scrub 4-5.75G */
> +	ddrc_inline_ecc_scrub(0x40000000, 0x5bffffff);
> +	/* set scruber read range 0-6G */
> +	ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff);
> +}
> +#endif
> diff --git a/board/freescale/imx8mp_rsb3720a1/spl.c b/board/freescale/imx8mp_rsb3720a1/spl.c
> new file mode 100644
> index 0000000000..513adf870f
> --- /dev/null
> +++ b/board/freescale/imx8mp_rsb3720a1/spl.c
> @@ -0,0 +1,270 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018-2019 NXP
> + * Copyright 2021 Linaro
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <cpu_func.h>
> +#include <hang.h>
> +#include <image.h>
> +#include <init.h>
> +#include <log.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm/arch/imx8mp_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-imx/boot_mode.h>
> +#include <power/pmic.h>
> +
> +#include <power/pca9450.h>
> +#include <asm/arch/clock.h>
> +#include <asm/mach-imx/gpio.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <fsl_esdhc_imx.h>
> +#include <mmc.h>
> +#include <asm/arch/ddr.h>
> +#include <linux/delay.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int spl_board_boot_device(enum boot_device boot_dev_spl)
> +{
> +#ifdef CONFIG_SPL_BOOTROM_SUPPORT
> +	return BOOT_DEVICE_BOOTROM;
> +#else
> +	switch (boot_dev_spl) {
> +	case SD1_BOOT:
> +	case MMC1_BOOT:
> +	case SD2_BOOT:
> +	case MMC2_BOOT:
> +		return BOOT_DEVICE_MMC1;
> +	case SD3_BOOT:
> +	case MMC3_BOOT:
> +		return BOOT_DEVICE_MMC2;
> +	case QSPI_BOOT:
> +		return BOOT_DEVICE_NOR;
> +	case NAND_BOOT:
> +		return BOOT_DEVICE_NAND;
> +	case USB_BOOT:
> +		return BOOT_DEVICE_BOARD;
> +	default:
> +		return BOOT_DEVICE_NONE;
> +	}
> +#endif
> +}
> +
> +void spl_dram_init(void)
> +{
> +	ddr_init(&dram_timing);
> +}
> +
> +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> +struct i2c_pads_info i2c_pad_info1 = {
> +	.scl = {
> +		.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
> +		.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
> +		.gp = IMX_GPIO_NR(5, 14),
> +	},
> +	.sda = {
> +		.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
> +		.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
> +		.gp = IMX_GPIO_NR(5, 15),
> +	},
> +};
> +
> +#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
> +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
> +
> +#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
> +			 PAD_CTL_PE |				    \
> +			 PAD_CTL_FSEL2)
> +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
> +#define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS | \
> +			   PAD_CTL_DSE4)
> +
> +static iomux_v3_cfg_t const usdhc3_pads[] = {
> +	MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const usdhc2_pads[] = {
> +	MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
> +	MX8MP_PAD_SD2_CD_B__GPIO2_IO12    | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
> +};
> +
> +#ifndef USDHC3_BASE_ADDR
> +#define USDHC3_BASE_ADDR	0x30B60000
> +#endif
> +
> +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> +	{USDHC2_BASE_ADDR, 0, 4},
> +	{USDHC3_BASE_ADDR, 0, 8},
> +};
> +
> +int board_mmc_init(struct bd_info *bis)
> +{
> +	int i, ret;
> +	/*
> +	 * According to the board_mmc_init() the following map is done:
> +	 * (U-Boot device node)    (Physical Port)
> +	 * mmc0                    USDHC1
> +	 * mmc1                    USDHC2
> +	 */
> +	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> +		switch (i) {
> +		case 0:
> +			init_clk_usdhc(1);
> +			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> +			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
> +							 ARRAY_SIZE(usdhc2_pads));
> +			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
> +			gpio_direction_output(USDHC2_PWR_GPIO, 0);
> +			udelay(500);
> +			gpio_direction_output(USDHC2_PWR_GPIO, 1);
> +			gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
> +			gpio_direction_input(USDHC2_CD_GPIO);
> +			break;
> +		case 1:
> +			init_clk_usdhc(2);
> +			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> +			imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
> +							 ARRAY_SIZE(usdhc3_pads));
> +			break;
> +		default:
> +			printf("Warning: you configured more USDHC controllers");
> +			printf("(%d) than supported by the board\n", i + 1);
> +			return -EINVAL;
> +		}
> +
> +		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> +	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> +	int ret = 0;
> +
> +	switch (cfg->esdhc_base) {
> +	default:
> +		break;
> +	case USDHC2_BASE_ADDR:
> +		ret = !gpio_get_value(USDHC2_CD_GPIO);
> +		return ret;
> +	}
> +
> +	return 1;
> +}
> +
> +#ifdef CONFIG_POWER
> +#define I2C_PMIC	0
> +int power_init_board(void)
> +{
> +	struct pmic *p;
> +	int ret;
> +
> +	ret = power_pca9450_init(I2C_PMIC, 0x25);
> +	if (ret)
> +		printf("power init failed");
> +	p = pmic_get("PCA9450");
> +	pmic_probe(p);
> +
> +	/* BUCKxOUT_DVS0/1 control BUCK123 output */
> +	pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
> +
> +	/*
> +	 * increase VDD_SOC to typical value 0.95V before first
> +	 * DRAM access, set DVS1 to 0.85v for suspend.
> +	 * Enable DVS control through PMIC_STBY_REQ and
> +	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
> +	 */
> +	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
> +	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
> +	pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
> +
> +	/* Kernel uses OD/OD freq for SOC */
> +	/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
> +	pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
> +
> +	/* set WDOG_B_CFG to cold reset */
> +	pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
> +
> +	/* Forced enable the I2C level translator*/
> +	pmic_reg_write(p, PCA9450_CONFIG2, 0x03);
> +
> +	return 0;
> +}
> +#endif
> +
> +void spl_board_init(void)
> +{
> +	puts("Normal Boot\n");
> +}
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> +	/* Just empty function now - can't decide what to choose */
> +	debug("%s: %s\n", __func__, name);
> +
> +	return 0;
> +}
> +#endif
> +
> +void board_init_f(ulong dummy)
> +{
> +	int ret;
> +
> +	/* Clear the BSS. */
> +	memset(__bss_start, 0, __bss_end - __bss_start);
> +
> +	arch_cpu_init();
> +
> +	board_early_init_f();
> +
> +	timer_init();
> +
> +	preloader_console_init();
> +
> +	ret = spl_init();
> +	if (ret) {
> +		debug("spl_init() failed: %d\n", ret);
> +		hang();
> +	}
> +
> +	enable_tzc380();
> +
> +	/* Adjust pmic voltage to 1.0V for 800M */
> +	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
> +
> +	power_init_board();
> +
> +	/* DDR initialization */
> +	spl_dram_init();
> +
> +	board_init_r(NULL, 0);
> +}
> diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig
> new file mode 100644
> index 0000000000..7b3c42faf1
> --- /dev/null
> +++ b/configs/imx8mp_rsb3720a1_4G_defconfig
> @@ -0,0 +1,158 @@
> +CONFIG_ARM=y
> +CONFIG_SPL_SYS_ICACHE_OFF=y
> +CONFIG_SPL_SYS_DCACHE_OFF=y
> +CONFIG_ARCH_IMX8M=y
> +CONFIG_SYS_TEXT_BASE=0x40200000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_NR_DRAM_BANKS=3
> +CONFIG_ENV_SIZE=0x2000
> +CONFIG_ENV_OFFSET=0x400000
> +CONFIG_ENV_SECT_SIZE=0x10000
> +CONFIG_SYS_I2C_MXC_I2C1=y
> +CONFIG_SYS_I2C_MXC_I2C2=y
> +CONFIG_SYS_I2C_MXC_I2C3=y
> +CONFIG_SYS_I2C_MXC_I2C4=y
> +CONFIG_DM_GPIO=y
> +CONFIG_SPL_TEXT_BASE=0x920000
> +CONFIG_TARGET_IMX8MP_RSB3720A1_4G=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> +CONFIG_SPL=y
> +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
> +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-rsb3720-a1"
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_FIT=y
> +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> +CONFIG_FIT_SIGNATURE=y
> +CONFIG_SPL_LOAD_FIT=y
> +# CONFIG_USE_SPL_FIT_GENERATOR is not set
> +CONFIG_OF_BOARD_SETUP=y
> +CONFIG_OF_SYSTEM_SETUP=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg"
> +CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb"
> +CONFIG_ARCH_MISC_INIT=y
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_BOARD_LATE_INIT=y
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_SPL_BOOTROM_SUPPORT=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SPL_I2C_SUPPORT=y
> +CONFIG_SPL_POWER_SUPPORT=y
> +CONFIG_SYS_PROMPT="u-boot=> "
> +# CONFIG_BOOTM_NETBSD is not set
> +CONFIG_CMD_BOOTEFI_SELFTEST=y
> +CONFIG_CMD_ERASEENV=y
> +CONFIG_CMD_NVEDIT_EFI=y
> +CONFIG_CMD_EEPROM=y
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_CMD_SHA1SUM=y
> +CONFIG_CMD_BIND=y
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_DFU=y
> +CONFIG_CMD_FUSE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_READ=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_CMD_SNTP=y
> +CONFIG_CMD_BMP=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_EFIDEBUG=y
> +CONFIG_CMD_RTC=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_GETTIME=y
> +CONFIG_CMD_TIMER=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_ENV_OVERWRITE=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_SYS_MMC_ENV_DEV=2
> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_SPL_DM=y
> +CONFIG_REGMAP=y
> +CONFIG_SYSCON=y
> +CONFIG_CLK_COMPOSITE_CCF=y
> +CONFIG_CLK_IMX8MP=y
> +CONFIG_DFU_TFTP=y
> +CONFIG_DFU_MMC=y
> +CONFIG_DFU_RAM=y
> +CONFIG_DFU_SF=y
> +CONFIG_USB_FUNCTION_FASTBOOT=y
> +CONFIG_FASTBOOT_BUF_ADDR=0x42800000
> +CONFIG_FASTBOOT_BUF_SIZE=0x5000000
> +CONFIG_FASTBOOT_FLASH=y
> +CONFIG_FASTBOOT_UUU_SUPPORT=y
> +CONFIG_FASTBOOT_FLASH_MMC_DEV=2
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_PCA953X=y
> +CONFIG_DM_I2C=y
> +# CONFIG_SPL_DM_I2C is not set
> +CONFIG_SYS_I2C_MXC=y
> +CONFIG_LED=y
> +CONFIG_LED_GPIO=y
> +CONFIG_SUPPORT_EMMC_RPMB=y
> +CONFIG_SUPPORT_EMMC_BOOT=y
> +CONFIG_MMC_IO_VOLTAGE=y
> +CONFIG_MMC_UHS_SUPPORT=y
> +CONFIG_MMC_HS400_ES_SUPPORT=y
> +CONFIG_MMC_HS400_SUPPORT=y
> +CONFIG_FSL_ESDHC_IMX=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SF_DEFAULT_MODE=0
> +CONFIG_SF_DEFAULT_SPEED=40000000
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_PHY_REALTEK=y
> +CONFIG_DM_ETH=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_DWC_ETH_QOS=y
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_IMX8M=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_RTC=y
> +CONFIG_RTC_S35392A=y
> +CONFIG_MXC_UART=y
> +CONFIG_SPI=y
> +CONFIG_DM_SPI=y
> +CONFIG_SYSRESET=y
> +CONFIG_SYSRESET_PSCI=y
> +CONFIG_DM_THERMAL=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_DWC3=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_MANUFACTURER="FSL"
> +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> +CONFIG_SDP_LOADADDR=0x40480000
> +CONFIG_USB_HOST_ETHER=y
> +CONFIG_DM_VIDEO=y
> +CONFIG_SYS_WHITE_ON_BLACK=y
> +CONFIG_SHA512_ALGO=y
> +CONFIG_SHA512=y
> +CONFIG_SHA384=y
> +CONFIG_LZO=y
> +CONFIG_BZIP2=y
> +CONFIG_OF_LIBFDT_OVERLAY=y
> +CONFIG_EFI_SET_TIME=y
> +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
> +CONFIG_EFI_CAPSULE_ON_DISK=y
> +CONFIG_EFI_CAPSULE_AUTHENTICATE=y
> +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
> +CONFIG_EFI_SECURE_BOOT=y
> diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig
> new file mode 100644
> index 0000000000..45036b2510
> --- /dev/null
> +++ b/configs/imx8mp_rsb3720a1_6G_defconfig
> @@ -0,0 +1,159 @@
> +CONFIG_ARM=y
> +CONFIG_SPL_SYS_ICACHE_OFF=y
> +CONFIG_SPL_SYS_DCACHE_OFF=y
> +CONFIG_ARCH_IMX8M=y
> +CONFIG_SYS_TEXT_BASE=0x40200000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_NR_DRAM_BANKS=3
> +CONFIG_ENV_SIZE=0x2000
> +CONFIG_ENV_OFFSET=0x400000
> +CONFIG_ENV_SECT_SIZE=0x10000
> +CONFIG_SYS_I2C_MXC_I2C1=y
> +CONFIG_SYS_I2C_MXC_I2C2=y
> +CONFIG_SYS_I2C_MXC_I2C3=y
> +CONFIG_SYS_I2C_MXC_I2C4=y
> +CONFIG_DM_GPIO=y
> +CONFIG_SPL_TEXT_BASE=0x920000
> +CONFIG_TARGET_IMX8MP_RSB3720A1_6G=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> +CONFIG_SPL=y
> +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
> +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-rsb3720-a1"
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_FIT=y
> +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> +CONFIG_FIT_SIGNATURE=y
> +CONFIG_SPL_LOAD_FIT=y
> +# CONFIG_USE_SPL_FIT_GENERATOR is not set
> +CONFIG_OF_BOARD_SETUP=y
> +CONFIG_OF_SYSTEM_SETUP=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg"
> +CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb"
> +CONFIG_ARCH_MISC_INIT=y
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_BOARD_LATE_INIT=y
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_SPL_BOOTROM_SUPPORT=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SPL_I2C_SUPPORT=y
> +CONFIG_SPL_POWER_SUPPORT=y
> +CONFIG_SYS_PROMPT="u-boot=> "
> +# CONFIG_BOOTM_NETBSD is not set
> +CONFIG_CMD_BOOTEFI_SELFTEST=y
> +CONFIG_CMD_ERASEENV=y
> +CONFIG_CMD_NVEDIT_EFI=y
> +CONFIG_CMD_EEPROM=y
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_CMD_SHA1SUM=y
> +CONFIG_CMD_BIND=y
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_DFU=y
> +CONFIG_CMD_FUSE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_READ=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_CMD_SNTP=y
> +CONFIG_CMD_BMP=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_EFIDEBUG=y
> +CONFIG_CMD_RTC=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_GETTIME=y
> +CONFIG_CMD_TIMER=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_ENV_OVERWRITE=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_SYS_MMC_ENV_DEV=2
> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_SPL_DM=y
> +CONFIG_REGMAP=y
> +CONFIG_SYSCON=y
> +CONFIG_CLK_COMPOSITE_CCF=y
> +CONFIG_CLK_IMX8MP=y
> +CONFIG_DFU_TFTP=y
> +CONFIG_DFU_MMC=y
> +CONFIG_DFU_RAM=y
> +CONFIG_DFU_SF=y
> +CONFIG_USB_FUNCTION_FASTBOOT=y
> +CONFIG_FASTBOOT_BUF_ADDR=0x42800000
> +CONFIG_FASTBOOT_BUF_SIZE=0x5000000
> +CONFIG_FASTBOOT_FLASH=y
> +CONFIG_FASTBOOT_UUU_SUPPORT=y
> +CONFIG_FASTBOOT_FLASH_MMC_DEV=2
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_PCA953X=y
> +CONFIG_DM_I2C=y
> +# CONFIG_SPL_DM_I2C is not set
> +CONFIG_SYS_I2C_MXC=y
> +CONFIG_LED=y
> +CONFIG_LED_GPIO=y
> +CONFIG_SUPPORT_EMMC_RPMB=y
> +CONFIG_SUPPORT_EMMC_BOOT=y
> +CONFIG_MMC_IO_VOLTAGE=y
> +CONFIG_MMC_UHS_SUPPORT=y
> +CONFIG_MMC_HS400_ES_SUPPORT=y
> +CONFIG_MMC_HS400_SUPPORT=y
> +CONFIG_FSL_ESDHC_IMX=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SF_DEFAULT_MODE=0
> +CONFIG_SF_DEFAULT_SPEED=40000000
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +CONFIG_PHY_REALTEK=y
> +CONFIG_DM_ETH=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_DWC_ETH_QOS=y
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_IMX8M=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_RTC=y
> +CONFIG_RTC_S35392A=y
> +CONFIG_MXC_UART=y
> +CONFIG_SPI=y
> +CONFIG_DM_SPI=y
> +CONFIG_SYSRESET=y
> +CONFIG_SYSRESET_PSCI=y
> +CONFIG_DM_THERMAL=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_DWC3=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_MANUFACTURER="FSL"
> +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> +CONFIG_SDP_LOADADDR=0x40480000
> +CONFIG_USB_HOST_ETHER=y
> +CONFIG_DM_VIDEO=y
> +CONFIG_SYS_WHITE_ON_BLACK=y
> +CONFIG_SHA512_ALGO=y
> +CONFIG_SHA512=y
> +CONFIG_SHA384=y
> +CONFIG_LZO=y
> +CONFIG_BZIP2=y
> +CONFIG_OF_LIBFDT_OVERLAY=y
> +CONFIG_EFI_SET_TIME=y
> +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
> +CONFIG_EFI_CAPSULE_ON_DISK=y
> +CONFIG_EFI_CAPSULE_AUTHENTICATE=y
> +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
> +CONFIG_EFI_SECURE_BOOT=y
> diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h
> new file mode 100644
> index 0000000000..f505b54e93
> --- /dev/null
> +++ b/include/configs/imx8mp_rsb3720.h
> @@ -0,0 +1,273 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019 NXP
> + * Copyright 2021 Linaro
> + */
> +
> +#ifndef __IMX8MP_RSB3720_H
> +#define __IMX8MP_RSB3720_H
> +
> +#include <linux/sizes.h>
> +#include <linux/stringify.h>
> +#include <asm/arch/imx-regs.h>
> +#include <config_distro_bootcmd.h>
> +
> +#define CONFIG_HAS_ETH1
> +
> +#define CONFIG_SPL_MAX_SIZE		(152 * 1024)
> +#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
> +#define CONFIG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
> +
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SPL_STACK		0x187FF0
> +#define CONFIG_SPL_BSS_START_ADDR	0x0095e000
> +#define CONFIG_SPL_BSS_MAX_SIZE		0x2000	/* 8 KB */
> +#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K	/* 512 KB */
> +
> +#define CONFIG_MALLOC_F_ADDR		0x184000 /* malloc f used before \
> +						  * GD_FLG_FULL_MALLOC_INIT \
> +						  * set \
> +						  */
> +
> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
> +
> +#define CONFIG_POWER
> +#define CONFIG_POWER_I2C
> +#define CONFIG_POWER_PCA9450
> +
> +#define CONFIG_SYS_I2C
> +
> +#if defined(CONFIG_NAND_BOOT)
> +#define CONFIG_SPL_NAND_SUPPORT
> +#define CONFIG_SPL_DMA
> +#define CONFIG_SPL_NAND_MXS
> +#define CONFIG_SPL_NAND_BASE
> +#define CONFIG_SPL_NAND_IDENT
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x4000000 /* Put the FIT out of \
> +						   * first 64MB boot area \
> +						   */
> +
> +/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full
> + * boot image (not only FIT part) to the mtdpart, so we check both two offsets
> + */
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
> +	(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
> +
> +#endif
> +
> +#endif
> +
> +#define CONFIG_FASTBOOT_USB_DEV 0
> +
> +#define CONFIG_REMAKE_ELF
> +/* ENET Config */
> +/* ENET1 */
> +#if defined(CONFIG_CMD_NET)
> +#define CONFIG_ETHPRIME                 "eth1" /* Set eqos to primary since we use its MDIO */
> +
> +#define CONFIG_FEC_XCV_TYPE             RGMII
> +#define CONFIG_FEC_MXC_PHYADDR          4
> +#define FEC_QUIRK_ENET_MAC
> +
> +#define DWC_NET_PHYADDR			4
> +#ifdef CONFIG_DWC_ETH_QOS
> +#define CONFIG_SYS_NONCACHED_MEMORY     (1 * SZ_1M)     /* 1M */
> +#endif
> +
> +#define PHY_ANEG_TIMEOUT 20000
> +
> +#endif
> +
> +#if CONFIG_IS_ENABLED(CMD_MMC)
> +# define BOOT_TARGET_MMC(func) \
> +	func(MMC, mmc, 2)      \
> +	func(MMC, mmc, 1)
> +#else
> +# define BOOT_TARGET_MMC(func)
> +#endif
> +
> +#if CONFIG_IS_ENABLED(CMD_USB)
> +# define BOOT_TARGET_USB(func) func(USB, usb, 0)
> +#else
> +# define BOOT_TARGET_USB(func)
> +#endif
> +
> +#if CONFIG_IS_ENABLED(CMD_PXE)
> +# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
> +#else
> +# define BOOT_TARGET_PXE(func)
> +#endif
> +
> +#if CONFIG_IS_ENABLED(CMD_DHCP)
> +# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
> +#else
> +# define BOOT_TARGET_DHCP(func)
> +#endif
> +
> +#define BOOT_TARGET_DEVICES(func) \
> +	BOOT_TARGET_USB(func) \
> +	BOOT_TARGET_MMC(func) \
> +	BOOT_TARGET_PXE(func) \
> +	BOOT_TARGET_DHCP(func)
> +
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS		\
> +	BOOTENV \
> +	"script=boot.scr\0" \
> +	"image=Image\0" \
> +	"splashimage=0x50000000\0" \
> +	"console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200\0" \
> +	"fdt_addr=0x43000000\0"			\
> +	"fdt_addr_r=0x43000000\0"			\
> +	"boot_fit=no\0" \
> +	"dfu_alt_info=mmc 2=flash-bin raw 0x40 0x250 mmcpart 0;" \
> +		"u-boot-itb raw 0x300 0x1B00 mmcpart 0\0"	 \
> +	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> +	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
> +	"initrd_addr=0x43800000\0"		\
> +	"bootm_size=0x10000000\0" \
> +	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
> +	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> +	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> +	"mmcautodetect=yes\0" \
> +	"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
> +	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
> +	"bootscript=echo Running bootscript from mmc ...; " \
> +		"source\0" \
> +	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> +	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> +	"kernel_addr_r=0x40480000\0" \
> +	"pxefile_addr_r=0x40480000\0" \
> +	"ramdisk_addr_r=0x43800000\0" \
> +	"mmcboot=echo Booting from mmc ...; " \
> +		"run mmcargs; " \
> +		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
> +			"bootm ${loadaddr}; " \
> +		"else " \
> +			"if run loadfdt; then " \
> +				"booti ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"echo WARN: Cannot load the DT; " \
> +			"fi; " \
> +		"fi;\0" \
> +	"netargs=setenv bootargs ${jh_clk} console=${console} " \
> +		"root=/dev/nfs " \
> +		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> +	"netboot=echo Booting from net ...; " \
> +		"run netargs;  " \
> +		"if test ${ip_dyn} = yes; then " \
> +			"setenv get_cmd dhcp; " \
> +		"else " \
> +			"setenv get_cmd tftp; " \
> +		"fi; " \
> +		"${get_cmd} ${loadaddr} ${image}; " \
> +		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
> +			"bootm ${loadaddr}; " \
> +		"else " \
> +			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> +				"booti ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"echo WARN: Cannot load the DT; " \
> +			"fi; " \
> +		"fi;\0"
> +
> +/* Link Definitions */
> +#define CONFIG_LOADADDR			0x40480000
> +
> +#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
> +#define CONFIG_SYS_INIT_RAM_SIZE	0x80000
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> +	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> +	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
> +#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
> +#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
> +#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
> +
> +#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN		SZ_32M
> +
> +/* Totally 6GB or 4G DDR */
> +#define CONFIG_SYS_SDRAM_BASE		0x40000000
> +#define PHYS_SDRAM			0x40000000
> +#if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
> +#define PHYS_SDRAM_SIZE			0xC0000000	/* 3 GB */
> +#define PHYS_SDRAM_2			0x100000000
> +#define PHYS_SDRAM_2_SIZE		0xC0000000	/* 3 GB */
> +#elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)
> +#define PHYS_SDRAM_SIZE			0x80000000	/* 2 GB */
> +#define PHYS_SDRAM_2			0xC0000000
> +#define PHYS_SDRAM_2_SIZE		0x80000000	/* 2 GB */
> +#endif
> +
> +#define CONFIG_MXC_UART_BASE		UART3_BASE_ADDR
> +
> +/* Monitor Command Prompt */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
> +#define CONFIG_SYS_CBSIZE		2048
> +#define CONFIG_SYS_MAXARGS		64
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> +					sizeof(CONFIG_SYS_PROMPT) + 16)
> +
> +#define CONFIG_IMX_BOOTAUX
> +#define CONFIG_FSL_USDHC
> +
> +#define CONFIG_SYS_FSL_USDHC_NUM	2
> +#define CONFIG_SYS_FSL_ESDHC_ADDR	0
> +
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
> +
> +#ifdef CONFIG_FSL_FSPI
> +#define FSL_FSPI_FLASH_SIZE		SZ_32M
> +#define FSL_FSPI_FLASH_NUM		1
> +#define FSPI0_BASE_ADDR			0x30bb0000
> +#define FSPI0_AMBA_BASE			0x0
> +#define CONFIG_FSPI_QUAD_SUPPORT
> +
> +#define CONFIG_SYS_FSL_FSPI_AHB
> +#endif
> +
> +#ifdef CONFIG_NAND_MXS
> +
> +/* NAND stuff */
> +#define CONFIG_SYS_MAX_NAND_DEVICE     1
> +#define CONFIG_SYS_NAND_BASE           0x20000000
> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +#define CONFIG_SYS_NAND_USE_FLASH_BBT
> +#endif /* CONFIG_NAND_MXS */
> +
> +#define CONFIG_SYS_I2C_SPEED		100000
> +
> +/* USB configs */
> +#ifndef CONFIG_SPL_BUILD
> +#define CONFIG_USB_GADGET_MASS_STORAGE
> +#endif
> +
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
> +#define CONFIG_USBD_HS
> +#define CONFIG_USB_GADGET_VBUS_DRAW 2
> +
> +#ifdef CONFIG_DM_VIDEO
> +#define CONFIG_VIDEO_LOGO
> +#define CONFIG_SPLASH_SCREEN
> +#define CONFIG_SPLASH_SCREEN_ALIGN
> +#define CONFIG_BMP_16BPP
> +#define CONFIG_BMP_24BPP
> +#define CONFIG_BMP_32BPP
> +#define CONFIG_VIDEO_BMP_RLE8
> +#define CONFIG_VIDEO_BMP_LOGO
> +#endif

VIDEO and USB on i.MX8MP, I think they are not ready in upstream.

If you not have that run, please drop.

Thanks,
Peng.

> +
> +#endif /* __IMX8MP_RSB3720_H */
>