[PATCH v3 00/16] misc: Some more misc patches

[Bin Meng]

Hi Simon,

On Wed, Jul 14, 2021 at 11:47 PM Simon Glass <sjg at chromium.org> wrote:
>
> Hi Bin,
>
> On Sun, 27 Jun 2021 at 17:51, Simon Glass <sjg at chromium.org> wrote:
> >
> > Various issues were discovered in getting Chromium OS verified boot
> > running on top of coreboot, booting into U-Boot.
> >
> > Improvements include:
> > - enable serial console if even coreboot doesn't
> > - enable cache always
> > - show the BIOS date since Chromium OS's coreboot doesn't have a version
> > - update docs
> > - allow SPI driver to work without a PCH
> > - fix mtrr command when multi-processing (CONFIG_MP) is disabled
> > - add documentation about the memory map
> >
> > Changes in v3:
> > - Fix comment to menion u-boot,dm-tpl
> > - Fix 'u-boot,dm-pre-tpl' (it should be u-boot,dm-tpl)
> >
> > Changes in v2:
> > - Add a comment about the cases
> > - Reorder declaration and use bios_date for the variable name
> > - Add missing newline in the error path
> > - Use (ret) instead of (ret != 0) to fit with U-Boot style
> > - Convert table to reST format
> > - Add 'cros' tag since this not a generic x86 change
> > - Drop unnecessary patch 'Enable the cbsysinfo command'
> >
> > Simon Glass (16):
> >   pci: Use const for pci_find_device_id() etc.
> >   x86: pci: Allow binding of some devices before relocation
> >   x86: Allow coreboot serial driver to guess the UART
> >   spi: ich: Don't require the PCH
> >   tpm: cr50: Drop unnecessary coral headers
> >   x86: Don't set up MTRRs if previously done
> >   x86: Update the MP constants to avoid conflicts
> >   x86: Do cache set-up by default when booting from coreboot
> >   x86: coreboot: Show the BIOS date
> >   x86: coral: Allow booting from coreboot
> >   x86: Add function comments to cb_sysinfo.h
> >   x86: coreboot: Use vendor in the Kconfig
> >   x86: coreboot: Document the memory map
> >   x86: cros: Check ROM exists before building vboot
> >   dtoc: Check that a parent is not missing
> >   doc: Update documentation for cros-2021.04 release
> >
> >  arch/x86/cpu/coreboot/Kconfig            |  2 +-
> >  arch/x86/cpu/i386/cpu.c                  |  2 +-
> >  arch/x86/dts/chromebook_coral.dts        |  2 +-
> >  arch/x86/dts/chromebook_samus.dts        |  2 +-
> >  arch/x86/include/asm/cb_sysinfo.h        | 16 ++++++
> >  arch/x86/include/asm/mp.h                | 12 +++--
> >  arch/x86/lib/init_helpers.c              | 18 +++++--
> >  board/coreboot/coreboot/Kconfig          | 12 +++--
> >  board/coreboot/coreboot/coreboot.c       |  3 ++
> >  board/google/chromebook_coral/coral.c    | 28 ++++++++++
> >  doc/board/coreboot/coreboot.rst          | 21 ++++++++
> >  doc/chromium/run_vboot.rst               | 15 +++---
> >  doc/device-tree-bindings/pci/x86-pci.txt |  7 ++-
> >  drivers/pci/pci-uclass.c                 | 39 ++++++++++++--
> >  drivers/serial/serial_coreboot.c         | 68 +++++++++++++++++++++---
> >  drivers/spi/ich.c                        |  4 +-
> >  drivers/tpm/cr50_i2c.c                   |  2 -
> >  include/dt-bindings/pci/pci.h            | 12 +++++
> >  include/pci.h                            |  5 +-
> >  include/pci_ids.h                        |  1 +
> >  tools/dtoc/dtb_platdata.py               |  9 ++++
> >  tools/dtoc/test/dtoc_test_noparent.dts   | 32 +++++++++++
> >  tools/dtoc/test_dtoc.py                  | 10 ++++
> >  23 files changed, 278 insertions(+), 44 deletions(-)
> >  create mode 100644 include/dt-bindings/pci/pci.h
> >  create mode 100644 tools/dtoc/test/dtoc_test_noparent.dts
> >
> > --
> > 2.32.0.93.g670b81a890-goog
> >
>
> Do you have any update on this series, please?
>

Sorry, I just applied this series.

There are many commits that have a blank line between your SoB tag and
the RB tag which I believe is caused by the patman patchwork
functionality.

I have manually removed the blank lines when applying. Would you
please fix the patman?

Regards,
Bin