[Patch V3 19/44] arm: imx8ulp: Enable full L2 cache in SPL

[sbabic at denx.de]

> From: Ye Li <ye.li at nxp.com>
> SRAM2 is half L2 cache and default to SRAM after system boot.
> To enable the full l2 cache (512KB), it needs to reset A35 to make
> the change happen.
> So re-implement the jump entry function in SPL:
> 1. configure the core0 reset vector to entry (ATF)
> 2. enable the L2 full cache
> 3. reset A35
> So when core0 up, it runs into ATF. And we have 512KB L2 cache working.
> Signed-off-by: Ye Li <ye.li at nxp.com>
> Signed-off-by: Peng Fan <peng.fan at nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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