[v4 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X device
Lim, Elly Siew Chin
elly.siew.chin.lim at intel.com
Thu Jul 22 19:58:58 CEST 2021
> -----Original Message-----
> From: Ley Foon Tan <lftan.linux at gmail.com>
> Sent: Friday, July 23, 2021 1:35 AM
> To: Lim, Elly Siew Chin <elly.siew.chin.lim at intel.com>
> Cc: ZY - u-boot <u-boot at lists.denx.de>; Marek Vasut <marex at denx.de>;
> Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong
> <tien.fong.chee at intel.com>; Westergreen, Dalon
> <dalon.westergreen at intel.com>; Simon Glass <sjg at chromium.org>; Gan,
> Yau Wai <yau.wai.gan at intel.com>
> Subject: Re: [v4 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X
> device
>
> On Mon, Jul 12, 2021 at 5:50 PM Siew Chin Lim <elly.siew.chin.lim at intel.com>
> wrote:
> >
> > Add device tree for N5X.
> >
> > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim at intel.com>
> > Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
> >
> > ---
> > v4:
> > - Reuse socfpga_n5x_socdk.dts from Linux and add U-boot specifc dts
> > to u-boot.dtsi. Linux socfpga_n5x_socdk.dts:
> >
> > https://github.com/altera-opensource/linux-socfpga/blob/socfpga-5.4.11
> > 4-lts/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
> >
> > v3:
> > - Update comment for memory example code
> > - Move all common dts settings for N5X from
> > socfpga_n5x_socdk.dts to socfpga_n5x-u-boot.dtsi
> > - Remove unused parameter "u-boot,boot0"
> >
> > v2:
> > - Remove socfpga_n5x.dtsi
> > - Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update
> > n5x data accordingly.
> > ---
> > arch/arm/dts/Makefile | 1 +
> > arch/arm/dts/socfpga_n5x-u-boot.dtsi | 192
> +++++++++++++++++++++++++++++
> > arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 100 +++++++++++++++
> > arch/arm/dts/socfpga_n5x_socdk.dts | 88 +++++++++++++
> > 4 files changed, 381 insertions(+)
> > create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi
> > create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> > create mode 100644 arch/arm/dts/socfpga_n5x_socdk.dts
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> > 7ce3ae6caa..9bf64e207c 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -397,6 +397,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
> \
> > socfpga_cyclone5_socrates.dtb \
> > socfpga_cyclone5_sr1500.dtb \
> > socfpga_cyclone5_vining_fpga.dtb \
> > + socfpga_n5x_socdk.dtb \
> > socfpga_stratix10_socdk.dtb
> >
> > dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
> diff
> > --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi
> > b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
> > new file mode 100644
> > index 0000000000..3e3859c0bf
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
> > @@ -0,0 +1,192 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * U-Boot additions
> > + *
> > + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> */
> > +
> > +#include "socfpga_soc64_fit-u-boot.dtsi"
> > +#include <dt-bindings/clock/n5x-clock.h>
> > +
> > +/{
> > + memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + u-boot,dm-pre-reloc;
> > + };
> > +
> > + soc {
> > + u-boot,dm-pre-reloc;
> > +
> > + ccu: cache-controller at f7000000 {
> > + compatible = "arteris,ncore-ccu";
> > + reg = <0xf7000000 0x100900>;
> > + u-boot,dm-pre-reloc;
> > + };
> > +
> > + clocks {
> > + dram_eosc_clk: dram-eosc-clk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + };
> > + };
> > +
> > + memclkmgr: mem-clock-controller at f8040000 {
> > + compatible = "intel,n5x-mem-clkmgr";
> > + reg = <0xf8040000 0x1000>;
> > + #clock-cells = <0>;
> > + clocks = <&dram_eosc_clk>, <&f2s_free_clk>;
> > + };
> > + };
> > +};
> > +
> > +&clkmgr {
> > + compatible = "intel,n5x-clkmgr";
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&gmac0 {
> > + clocks = <&clkmgr N5X_EMAC0_CLK>; };
> > +
> > +&gmac1 {
> > + altr,sysmgr-syscon = <&sysmgr 0x48 0>;
> > + clocks = <&clkmgr N5X_EMAC1_CLK>; };
> > +
> > +&gmac2 {
> > + altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
> > + clocks = <&clkmgr N5X_EMAC2_CLK>; };
> > +
> > +&i2c0 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>;
> > + reset-names = "i2c";
> > +};
> > +
> > +&i2c1 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>;
> > + reset-names = "i2c";
> > +};
> > +
> > +&i2c2 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>;
> > + reset-names = "i2c";
> > +};
> > +
> > +&i2c3 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>;
> > + reset-names = "i2c";
> > +};
> > +
> > +&i2c4 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>;
> > + reset-names = "i2c";
> > +};
> > +
> > +&memclkmgr {
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&mmc {
> > + clocks = <&clkmgr N5X_L4_MP_CLK>,
> > + <&clkmgr N5X_SDMMC_CLK>;
> > + resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; };
> > +
> > +&pdma {
> > + clocks = <&clkmgr N5X_L4_MAIN_CLK>; };
> > +
> > +&spi0 {
> > + clocks = <&clkmgr N5X_L4_MAIN_CLK>; };
> > +
> > +&spi1 {
> > + clocks = <&clkmgr N5X_L4_MAIN_CLK>; };
> > +
> > +&timer0 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>; };
> > +
> > +&timer1 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>; };
> > +
> > +&timer2 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>; };
> > +
> > +&timer3 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>; };
> > +
> > +&porta {
> Sort the node name in alphanumeric order.
>
> > + bank-name = "porta";
> > +};
> > +
> > +&portb {
> > + bank-name = "portb";
> > +};
> > +
> > +&qspi {
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&rst {
> > + compatible = "altr,rst-mgr";
> > + altr,modrst-offset = <0x20>;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&sdr {
> > + compatible = "intel,sdr-ctl-n5x";
> > + resets = <&rst DDRSCH_RESET>;
> > + clocks = <&memclkmgr>;
> > + clock-names = "mem_clk";
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&sysmgr {
> > + compatible = "altr,sys-mgr", "syscon";
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&uart0 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&uart1 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>; };
> > +
> > +&usb0 {
> > + clocks = <&clkmgr N5X_USB_CLK>;
> > + disable-over-current;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&usb1 {
> > + clocks = <&clkmgr N5X_USB_CLK>;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&watchdog0 {
> > + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&watchdog1 {
> > + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; };
> > +
> > +&watchdog2 {
> > + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; };
> > +
> > +&watchdog3 {
> > + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; };
> > +
> > diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> > b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> > new file mode 100644
> > index 0000000000..ccc0c61d89
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> > @@ -0,0 +1,100 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * U-Boot additions
> > + *
> > + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> */
> > +
> > +#include "socfpga_n5x-u-boot.dtsi"
> > +
> > +/{
> > + aliases {
> > + spi0 = &qspi;
> > + i2c0 = &i2c1;
> > + };
> > +
> > + memory {
> > + /*
> > + * Memory type: DDR4 (non-interleaving mode)
> > + * 16GB
> > + * <0 0x00000000 0 0x80000000>,
> > + * <4 0x80000000 3 0x80000000>;
> > + *
> > + * 8GB
> > + * <0 0x00000000 0 0x80000000>,
> > + * <2 0x80000000 1 0x80000000>;
> > + *
> > + * 4GB
> > + * <0 0x00000000 0 0x80000000>,
> > + * <1 0x80000000 0 0x80000000>;
> > + *
> > + * Memory type: LPDDR4 (non-interleaving mode)
> > + * Total memory size 3GB, usable = 2.5GB, 0.5GB trade off for
> secure
> > + * region.
> > + */
> > + reg = <0 0x00000000 0 0x60000000>,
> > + <0x10 0x00100000 0 0x40000000>;
> > + };
> > +};
> > +
> > +&i2c1 {
> > + status = "okay";
> > +};
> > +
> > +&nand {
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&mmc {
> > + drvsel = <3>;
> > + smplsel = <0>;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&qspi {
> > + status = "okay";
> > +
> > + flash0: flash at 0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "mt25qu02g";
> > + reg = <0>;
> > + spi-max-frequency = <100000000>;
> > +
> > + m25p,fast-read;
> > + cdns,page-size = <256>;
> > + cdns,block-size = <16>;
> > + cdns,read-delay = <3>;
> > + cdns,tshsl-ns = <50>;
> > + cdns,tsd2d-ns = <50>;
> > + cdns,tchsh-ns = <4>;
> > + cdns,tslch-ns = <4>;
> > +
> > + partitions {
> > + compatible = "fixed-partitions";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + qspi_boot: partition at 0 {
> > + label = "Boot and fpga data";
> > + reg = <0x0 0x034B0000>;
> > + };
> > +
> > + qspi_rootfs: partition at 34B0000 {
> > + label = "Root Filesystem - JFFS2";
> > + reg = <0x034B0000 0x0EB50000>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&flash0 {
> > + compatible = "jedec,spi-nor";
> > + spi-tx-bus-width = <4>;
> > + spi-rx-bus-width = <4>;
> > + u-boot,dm-pre-reloc;
> These should merge into "flash0: flash at 0" node.
>
>
> Regards
> Ley Foon
Noted, I will update and resend.
Thanks,
Siew Chin
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