[PATCH 07/27] sunxi: add SPI0 node for suniv

[Yifan Gu]

From: Icenowy Zheng <icenowy at aosc.io>

The suniv SoC has two SPI controllers, in which SPI0 is bootable.

Add device tree node of the controller and its bootable pinmux node.

Signed-off-by: Icenowy Zheng <icenowy at aosc.io>
Signed-off-by: Yifan Gu <me at yifangu.com>
---
 arch/arm/dts/suniv.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/dts/suniv.dtsi b/arch/arm/dts/suniv.dtsi
index a5673f5006..b11d9eb57a 100644
--- a/arch/arm/dts/suniv.dtsi
+++ b/arch/arm/dts/suniv.dtsi
@@ -76,6 +76,19 @@
 			};
 		};
 
+		spi0: spi at 1c05000 {
+			compatible = "allwinner,suniv-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c05000 0x1000>;
+			interrupts = <10>;
+			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI0>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		ccu: clock at 1c20000 {
 			compatible = "allwinner,suniv-f1c100s-ccu";
 			reg = <0x01c20000 0x400>;
@@ -103,6 +116,11 @@
 			#interrupt-cells = <3>;
 			#gpio-cells = <3>;
 
+			spi0_pins_a: spi0-pins-pc {
+				pins = "PC0", "PC1", "PC2", "PC3";
+				function = "spi0";
+			};
+
 			uart0_pe_pins: uart-pins-pe {
 				pins = "PE0", "PE1";
 				function = "uart0";
-- 
2.25.1