[PATCH v1 4/5] rockchip: Add rk3568 architecture core
Joseph Chen
chenjh at rock-chips.com
Wed Jun 2 09:58:25 CEST 2021
RK3568 is a high-performance and low power quad-core application
processor designed for personal mobile internet device and AIoT
equipments.
Signed-off-by: Joseph Chen <chenjh at rock-chips.com>
---
arch/arm/include/asm/arch-rk3568/boot0.h | 11 +
arch/arm/include/asm/arch-rk3568/gpio.h | 11 +
.../include/asm/arch-rockchip/grf_rk3568.h | 369 ++++++++++++++++++
arch/arm/mach-rockchip/Kconfig | 17 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3568/Kconfig | 20 +
arch/arm/mach-rockchip/rk3568/Makefile | 9 +
arch/arm/mach-rockchip/rk3568/clk_rk3568.c | 53 +++
arch/arm/mach-rockchip/rk3568/rk3568.c | 85 ++++
arch/arm/mach-rockchip/rk3568/syscon_rk3568.c | 24 ++
include/configs/rk3568_common.h | 43 ++
11 files changed, 643 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rk3568/boot0.h
create mode 100644 arch/arm/include/asm/arch-rk3568/gpio.h
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3568.h
create mode 100644 arch/arm/mach-rockchip/rk3568/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3568/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3568/clk_rk3568.c
create mode 100644 arch/arm/mach-rockchip/rk3568/rk3568.c
create mode 100644 arch/arm/mach-rockchip/rk3568/syscon_rk3568.c
create mode 100644 include/configs/rk3568_common.h
diff --git a/arch/arm/include/asm/arch-rk3568/boot0.h b/arch/arm/include/asm/arch-rk3568/boot0.h
new file mode 100644
index 0000000000..dea2b20252
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3568/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3568/gpio.h b/arch/arm/include/asm/arch-rk3568/gpio.h
new file mode 100644
index 0000000000..b48c0a5cf8
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3568/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3568.h b/arch/arm/include/asm/arch-rockchip/grf_rk3568.h
new file mode 100644
index 0000000000..d4e9b56292
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3568.h
@@ -0,0 +1,369 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3568_GRF_H__
+#define __SOC_ROCKCHIP_RK3568_GRF_H__
+
+struct rk3568_grf {
+ unsigned int gpio1a_iomux_l;
+ unsigned int gpio1a_iomux_h;
+ unsigned int gpio1b_iomux_l;
+ unsigned int gpio1b_iomux_h;
+ unsigned int gpio1c_iomux_l;
+ unsigned int gpio1c_iomux_h;
+ unsigned int gpio1d_iomux_l;
+ unsigned int gpio1d_iomux_h;
+ unsigned int gpio2a_iomux_l;
+ unsigned int gpio2a_iomux_h;
+ unsigned int gpio2b_iomux_l;
+ unsigned int gpio2b_iomux_h;
+ unsigned int gpio2c_iomux_l;
+ unsigned int gpio2c_iomux_h;
+ unsigned int gpio2d_iomux_l;
+ unsigned int gpio2d_iomux_h;
+ unsigned int gpio3a_iomux_l;
+ unsigned int gpio3a_iomux_h;
+ unsigned int gpio3b_iomux_l;
+ unsigned int gpio3b_iomux_h;
+ unsigned int gpio3c_iomux_l;
+ unsigned int gpio3c_iomux_h;
+ unsigned int gpio3d_iomux_l;
+ unsigned int gpio3d_iomux_h;
+ unsigned int gpio4a_iomux_l;
+ unsigned int gpio4a_iomux_h;
+ unsigned int gpio4b_iomux_l;
+ unsigned int gpio4b_iomux_h;
+ unsigned int gpio4c_iomux_l;
+ unsigned int gpio4c_iomux_h;
+ unsigned int gpio4d_iomux_l;
+ unsigned int reserved0[(0x0080 - 0x0078) / 4 - 1];
+ unsigned int gpio1a_p;
+ unsigned int gpio1b_p;
+ unsigned int gpio1c_p;
+ unsigned int gpio1d_p;
+ unsigned int gpio2a_p;
+ unsigned int gpio2b_p;
+ unsigned int gpio2c_p;
+ unsigned int gpio2d_p;
+ unsigned int gpio3a_p;
+ unsigned int gpio3b_p;
+ unsigned int gpio3c_p;
+ unsigned int gpio3d_p;
+ unsigned int gpio4a_p;
+ unsigned int gpio4b_p;
+ unsigned int gpio4c_p;
+ unsigned int gpio4d_p;
+ unsigned int gpio1a_ie;
+ unsigned int gpio1b_ie;
+ unsigned int gpio1c_ie;
+ unsigned int gpio1d_ie;
+ unsigned int gpio2a_ie;
+ unsigned int gpio2b_ie;
+ unsigned int gpio2c_ie;
+ unsigned int gpio2d_ie;
+ unsigned int gpio3a_ie;
+ unsigned int gpio3b_ie;
+ unsigned int gpio3c_ie;
+ unsigned int gpio3d_ie;
+ unsigned int gpio4a_ie;
+ unsigned int gpio4b_ie;
+ unsigned int gpio4c_ie;
+ unsigned int gpio4d_ie;
+ unsigned int gpio1a_opd;
+ unsigned int gpio1b_opd;
+ unsigned int gpio1c_opd;
+ unsigned int gpio1d_opd;
+ unsigned int gpio2a_opd;
+ unsigned int gpio2b_opd;
+ unsigned int gpio2c_opd;
+ unsigned int gpio2d_opd;
+ unsigned int gpio3a_opd;
+ unsigned int gpio3b_opd;
+ unsigned int gpio3c_opd;
+ unsigned int gpio3d_opd;
+ unsigned int gpio4a_opd;
+ unsigned int gpio4b_opd;
+ unsigned int gpio4c_opd;
+ unsigned int gpio4d_opd;
+ unsigned int gpio1a_sus;
+ unsigned int gpio1b_sus;
+ unsigned int gpio1c_sus;
+ unsigned int gpio1d_sus;
+ unsigned int gpio2a_sus;
+ unsigned int gpio2b_sus;
+ unsigned int gpio2c_sus;
+ unsigned int gpio2d_sus;
+ unsigned int gpio3a_sus;
+ unsigned int gpio3b_sus;
+ unsigned int gpio3c_sus;
+ unsigned int gpio3d_sus;
+ unsigned int gpio4a_sus;
+ unsigned int gpio4b_sus;
+ unsigned int gpio4c_sus;
+ unsigned int gpio4d_sus;
+ unsigned int gpio1a_sl;
+ unsigned int gpio1b_sl;
+ unsigned int gpio1c_sl;
+ unsigned int gpio1d_sl;
+ unsigned int gpio2a_sl;
+ unsigned int gpio2b_sl;
+ unsigned int gpio2c_sl;
+ unsigned int gpio2d_sl;
+ unsigned int gpio3a_sl;
+ unsigned int gpio3b_sl;
+ unsigned int gpio3c_sl;
+ unsigned int gpio3d_sl;
+ unsigned int gpio4a_sl;
+ unsigned int gpio4b_sl;
+ unsigned int gpio4c_sl;
+ unsigned int gpio4d_sl;
+ unsigned int reserved1[(0x0200 - 0x01bc) / 4 - 1];
+ unsigned int gpio1a_ds_0;
+ unsigned int gpio1a_ds_1;
+ unsigned int gpio1a_ds_2;
+ unsigned int gpio1a_ds_3;
+ unsigned int gpio1b_ds_0;
+ unsigned int gpio1b_ds_1;
+ unsigned int gpio1b_ds_2;
+ unsigned int gpio1b_ds_3;
+ unsigned int gpio1c_ds_0;
+ unsigned int gpio1c_ds_1;
+ unsigned int gpio1c_ds_2;
+ unsigned int gpio1c_ds_3;
+ unsigned int gpio1d_ds_0;
+ unsigned int gpio1d_ds_1;
+ unsigned int gpio1d_ds_2;
+ unsigned int gpio1d_ds_3;
+ unsigned int gpio2a_ds_0;
+ unsigned int gpio2a_ds_1;
+ unsigned int gpio2a_ds_2;
+ unsigned int gpio2a_ds_3;
+ unsigned int gpio2b_ds_0;
+ unsigned int gpio2b_ds_1;
+ unsigned int gpio2b_ds_2;
+ unsigned int gpio2b_ds_3;
+ unsigned int gpio2c_ds_0;
+ unsigned int gpio2c_ds_1;
+ unsigned int gpio2c_ds_2;
+ unsigned int gpio2c_ds_3;
+ unsigned int gpio2d_ds_0;
+ unsigned int gpio2d_ds_1;
+ unsigned int gpio2d_ds_2;
+ unsigned int gpio2d_ds_3;
+ unsigned int gpio3a_ds_0;
+ unsigned int gpio3a_ds_1;
+ unsigned int gpio3a_ds_2;
+ unsigned int gpio3a_ds_3;
+ unsigned int gpio3b_ds_0;
+ unsigned int gpio3b_ds_1;
+ unsigned int gpio3b_ds_2;
+ unsigned int gpio3b_ds_3;
+ unsigned int gpio3c_ds_0;
+ unsigned int gpio3c_ds_1;
+ unsigned int gpio3c_ds_2;
+ unsigned int gpio3c_ds_3;
+ unsigned int gpio3d_ds_0;
+ unsigned int gpio3d_ds_1;
+ unsigned int gpio3d_ds_2;
+ unsigned int gpio3d_ds_3;
+ unsigned int gpio4a_ds_0;
+ unsigned int gpio4a_ds_1;
+ unsigned int gpio4a_ds_2;
+ unsigned int gpio4a_ds_3;
+ unsigned int gpio4b_ds_0;
+ unsigned int gpio4b_ds_1;
+ unsigned int gpio4b_ds_2;
+ unsigned int gpio4b_ds_3;
+ unsigned int gpio4c_ds_0;
+ unsigned int gpio4c_ds_1;
+ unsigned int gpio4c_ds_2;
+ unsigned int gpio4c_ds_3;
+ unsigned int gpio4d_ds_0;
+ unsigned int gpio4d_ds_1;
+ unsigned int gpio4d_ds_2;
+ unsigned int gpio4d_ds_3;
+ unsigned int iofunc_sel0;
+ unsigned int iofunc_sel1;
+ unsigned int iofunc_sel2;
+ unsigned int iofunc_sel3;
+ unsigned int iofunc_sel4;
+ unsigned int iofunc_sel5;
+ unsigned int reserved2[(0x0340 - 0x0314) / 4 - 1];
+ unsigned int vi_con0;
+ unsigned int vi_con1;
+ unsigned int vi_status0;
+ unsigned int reserved3[(0x0360 - 0x0348) / 4 - 1];
+ unsigned int vo_con0;
+ unsigned int vo_con1;
+ unsigned int vo_con2;
+ unsigned int vo_con3;
+ unsigned int reserved4[(0x0380 - 0x036c) / 4 - 1];
+ unsigned int mac0_con0;
+ unsigned int mac0_con1;
+ unsigned int mac1_con0;
+ unsigned int mac1_con1;
+ unsigned int reserved5[(0x03a0 - 0x038c) / 4 - 1];
+ unsigned int biu_con0;
+ unsigned int biu_con1;
+ unsigned int biu_con2;
+ unsigned int reserved6[(0x03c0 - 0x03a8) / 4 - 1];
+ unsigned int gic_con0;
+ unsigned int gic_con1;
+ unsigned int gic_con2;
+ unsigned int reserved7[(0x03f0 - 0x03c8) / 4 - 1];
+ unsigned int gpu_con0;
+ unsigned int gpu_con1;
+ unsigned int reserved8[(0x0400 - 0x03f4) / 4 - 1];
+ unsigned int cpu_con0;
+ unsigned int reserved9[(0x0420 - 0x0400) / 4 - 1];
+ unsigned int cpu_status0;
+ unsigned int reserved10[(0x0500 - 0x0420) / 4 - 1];
+ unsigned int soc_con0;
+ unsigned int soc_con1;
+ unsigned int soc_con2;
+ unsigned int soc_con3;
+ unsigned int reserved11[(0x0514 - 0x050c) / 4 - 1];
+ unsigned int soc_con5;
+ unsigned int soc_con6;
+ unsigned int reserved12[(0x0580 - 0x0518) / 4 - 1];
+ unsigned int soc_status0;
+ unsigned int reserved13[(0x05c0 - 0x0580) / 4 - 1];
+ unsigned int ram_con;
+ unsigned int core_ram_con;
+ unsigned int reserved14[(0x0600 - 0x05c4) / 4 - 1];
+ unsigned int tsadc_con;
+ unsigned int reserved15[(0x0610 - 0x0600) / 4 - 1];
+ unsigned int saradc_con;
+ unsigned int reserved16[(0x0700 - 0x0610) / 4 - 1];
+ unsigned int gpupvtpll_con0;
+ unsigned int gpupvtpll_con1;
+ unsigned int gpupvtpll_con2;
+ unsigned int gpupvtpll_con3;
+ unsigned int reserved17[(0x0740 - 0x070c) / 4 - 1];
+ unsigned int npupvtpll_con0;
+ unsigned int npupvtpll_con1;
+ unsigned int npupvtpll_con2;
+ unsigned int npupvtpll_con3;
+ unsigned int reserved18[(0x0800 - 0x074c) / 4 - 1];
+ unsigned int chip_id;
+ unsigned int reserved19[(0x0840 - 0x0800) / 4 - 1];
+ unsigned int gpio1c5_ds;
+ unsigned int gpio2a2_ds;
+ unsigned int gpio2b0_ds;
+ unsigned int gpio3a0_ds;
+ unsigned int gpio3a6_ds;
+ unsigned int gpio4a0_ds;
+ unsigned int reserved20[(0x0900 - 0x0854) / 4 - 1];
+ unsigned int dmac0_con0;
+ unsigned int dmac0_con1;
+ unsigned int dmac0_con2;
+ unsigned int dmac0_con3;
+ unsigned int dmac0_con4;
+ unsigned int dmac0_con5;
+ unsigned int dmac0_con6;
+ unsigned int dmac0_con7;
+ unsigned int dmac0_con8;
+ unsigned int dmac0_con9;
+ unsigned int reserved21[(0x0940 - 0x0924) / 4 - 1];
+ unsigned int dmac1_con0;
+ unsigned int dmac1_con1;
+ unsigned int dmac1_con2;
+ unsigned int dmac1_con3;
+ unsigned int dmac1_con4;
+ unsigned int dmac1_con5;
+ unsigned int dmac1_con6;
+ unsigned int dmac1_con7;
+ unsigned int dmac1_con8;
+ unsigned int dmac1_con9;
+};
+
+check_member(rk3568_grf, dmac1_con9, 0x0964);
+
+struct rk3568_pmugrf {
+ unsigned int pmu_gpio0a_iomux_l;
+ unsigned int pmu_gpio0a_iomux_h;
+ unsigned int pmu_gpio0b_iomux_l;
+ unsigned int pmu_gpio0b_iomux_h;
+ unsigned int pmu_gpio0c_iomux_l;
+ unsigned int pmu_gpio0c_iomux_h;
+ unsigned int pmu_gpio0d_iomux_l;
+ unsigned int reserved0[(0x0020 - 0x0018) / 4 - 1];
+ unsigned int pmu_gpio0a_p;
+ unsigned int pmu_gpio0b_p;
+ unsigned int pmu_gpio0c_p;
+ unsigned int pmu_gpio0d_p;
+ unsigned int pmu_gpio0a_ie;
+ unsigned int pmu_gpio0b_ie;
+ unsigned int pmu_gpio0c_ie;
+ unsigned int pmu_gpio0d_ie;
+ unsigned int pmu_gpio0a_opd;
+ unsigned int pmu_gpio0b_opd;
+ unsigned int pmu_gpio0c_opd;
+ unsigned int pmu_gpio0d_opd;
+ unsigned int pmu_gpio0a_sus;
+ unsigned int pmu_gpio0b_sus;
+ unsigned int pmu_gpio0c_sus;
+ unsigned int pmu_gpio0d_sus;
+ unsigned int pmu_gpio0a_sl;
+ unsigned int pmu_gpio0b_sl;
+ unsigned int pmu_gpio0c_sl;
+ unsigned int pmu_gpio0d_sl;
+ unsigned int pmu_gpio0a_ds_0;
+ unsigned int pmu_gpio0a_ds_1;
+ unsigned int pmu_gpio0a_ds_2;
+ unsigned int pmu_gpio0a_ds_3;
+ unsigned int pmu_gpio0b_ds_0;
+ unsigned int pmu_gpio0b_ds_1;
+ unsigned int pmu_gpio0b_ds_2;
+ unsigned int pmu_gpio0b_ds_3;
+ unsigned int pmu_gpio0c_ds_0;
+ unsigned int pmu_gpio0c_ds_1;
+ unsigned int pmu_gpio0c_ds_2;
+ unsigned int pmu_gpio0c_ds_3;
+ unsigned int pmu_gpio0d_ds_0;
+ unsigned int pmu_gpio0d_ds_1;
+ unsigned int pmu_gpio0d_ds_2;
+ unsigned int pmu_gpio0d_ds_3;
+ unsigned int reserved1[(0x0100 - 0x00ac) / 4 - 1];
+ unsigned int pmu_soc_con0;
+ unsigned int pmu_soc_con1;
+ unsigned int pmu_soc_con2;
+ unsigned int pmu_soc_con3;
+ unsigned int pmu_soc_con4;
+ unsigned int pmu_soc_con5;
+ unsigned int reserved2[(0x0124 - 0x0114) / 4 - 1];
+ unsigned int pmu_io_vsel0;
+ unsigned int pmu_io_vsel1;
+ unsigned int pmu_io_vsel2;
+ unsigned int reserved3[(0x0180 - 0x012c) / 4 - 1];
+ unsigned int pmu_dll_con0;
+ unsigned int reserved4[(0x0200 - 0x0180) / 4 - 1];
+ unsigned int pmu_os_reg0;
+ unsigned int pmu_os_reg1;
+ unsigned int pmu_os_reg2;
+ unsigned int pmu_os_reg3;
+ unsigned int pmu_os_reg4;
+ unsigned int pmu_os_reg5;
+ unsigned int pmu_os_reg6;
+ unsigned int pmu_os_reg7;
+ unsigned int pmu_os_reg8;
+ unsigned int pmu_os_reg9;
+ unsigned int pmu_os_reg10;
+ unsigned int pmu_os_reg11;
+ unsigned int pmu_reset_function_status;
+ unsigned int pmu_reset_function_clr;
+ unsigned int reserved5[(0x0380 - 0x0234) / 4 - 1];
+ unsigned int pmu_sig_detect_con;
+ unsigned int reserved6[(0x0390 - 0x0380) / 4 - 1];
+ unsigned int pmu_sig_detect_status;
+ unsigned int reserved7[(0x03a0 - 0x0390) / 4 - 1];
+ unsigned int pmu_sig_detect_status_clear;
+ unsigned int reserved8[(0x03b0 - 0x03a0) / 4 - 1];
+ unsigned int pmu_sdmmc_det_counter;
+};
+
+check_member(rk3568_pmugrf, pmu_sdmmc_det_counter, 0x03b0);
+
+#endif
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 407bf3fbea..4a2d35aee2 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -257,6 +257,23 @@ config ROCKCHIP_RK3399
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+config ROCKCHIP_RK3568
+ bool "Support Rockchip RK3568"
+ select ARM64
+ select CLK
+ select PINCTRL
+ select RAM
+ select REGMAP
+ select SYSCON
+ select BOARD_LATE_INIT
+ imply ROCKCHIP_COMMON_BOARD
+ help
+ The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
+ including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
+ two video interfaces supporting HDMI and eDP, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+
config ROCKCHIP_RV1108
bool "Support Rockchip RV1108"
select CPU_V7A
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 121f23a563..00aef0ecee 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
+obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
# Clear out SPL objects, in case this is a TPL build
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig
new file mode 100644
index 0000000000..201c63c2a9
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -0,0 +1,20 @@
+if ROCKCHIP_RK3568
+
+config TARGET_EVB_RK3568
+ bool "RK3568 evaluation board"
+ select BOARD_LATE_INIT
+ help
+ RK3568 EVB is a evaluation board for Rockchp RK3568.
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0xfdc20200
+
+config SYS_SOC
+ default "rk3568"
+
+config SYS_MALLOC_F_LEN
+ default 0x2000
+
+source "board/rockchip/evb_rk3568/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rockchip/rk3568/Makefile b/arch/arm/mach-rockchip/rk3568/Makefile
new file mode 100644
index 0000000000..28c1f4ee5c
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3568/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2021 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clk_rk3568.o
+obj-y += rk3568.o
+obj-y += syscon_rk3568.o
diff --git a/arch/arm/mach-rockchip/rk3568/clk_rk3568.c b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c
new file mode 100644
index 0000000000..8917edcbd3
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3568.h>
+#include <linux/err.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(rockchip_rk3568_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3568_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
+
+static int rockchip_get_pmucruclk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(rockchip_rk3568_pmucru), devp);
+}
+
+void *rockchip_get_pmucru(void)
+{
+ struct rk3568_pmuclk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_pmucruclk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->pmucru;
+}
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
new file mode 100644
index 0000000000..973b4f9dcb
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/grf_rk3568.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <dt-bindings/clock/rk3568-cru.h>
+
+#define PMUGRF_BASE 0xfdc20000
+#define GRF_BASE 0xfdc60000
+
+/* PMU_GRF_GPIO0D_IOMUX_L */
+enum {
+ GPIO0D1_SHIFT = 4,
+ GPIO0D1_MASK = GENMASK(6, 4),
+ GPIO0D1_GPIO = 0,
+ GPIO0D1_UART2_TXM0,
+
+ GPIO0D0_SHIFT = 0,
+ GPIO0D0_MASK = GENMASK(2, 0),
+ GPIO0D0_GPIO = 0,
+ GPIO0D0_UART2_RXM0,
+};
+
+/* GRF_IOFUNC_SEL3 */
+enum {
+ UART2_IO_SEL_SHIFT = 10,
+ UART2_IO_SEL_MASK = GENMASK(11, 10),
+ UART2_IO_SEL_M0 = 0,
+};
+
+static struct mm_region rk3568_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xf0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf0000000UL,
+ .phys = 0xf0000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x300000000,
+ .phys = 0x300000000,
+ .size = 0x0c0c00000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rk3568_mem_map;
+
+void board_debug_uart_init(void)
+{
+ static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
+ static struct rk3568_grf * const grf = (void *)GRF_BASE;
+
+ /* UART2 M0 */
+ rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK,
+ UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
+
+ /* Switch iomux */
+ rk_clrsetreg(&pmugrf->pmu_gpio0d_iomux_l,
+ GPIO0D1_MASK | GPIO0D0_MASK,
+ GPIO0D1_UART2_TXM0 << GPIO0D1_SHIFT |
+ GPIO0D0_UART2_RXM0 << GPIO0D0_SHIFT);
+}
+
+int arch_cpu_init(void)
+{
+ return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c
new file mode 100644
index 0000000000..20adfd1169
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3568_syscon_ids[] = {
+ { .compatible = "rockchip,rk3568-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rk3568-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3568) = {
+ .name = "rk3568_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3568_syscon_ids,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
+};
diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h
new file mode 100644
index 0000000000..b6568917ea
--- /dev/null
+++ b/include/configs/rk3568_common.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_RK3568_COMMON_H
+#define __CONFIG_RK3568_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define COUNTER_FREQUENCY 24000000
+#define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020
+
+#define CONFIG_IRAM_BASE 0xfdcc0000
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
+#define CONFIG_SYS_LOAD_ADDR 0x00c00800
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
+
+#define CONFIG_SYS_SDRAM_BASE 0
+#define SDRAM_MAX_SIZE 0xf0000000
+
+#ifndef CONFIG_SPL_BUILD
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x00c00000\0" \
+ "pxefile_addr_r=0x00e00000\0" \
+ "fdt_addr_r=0x0a100000\0" \
+ "kernel_addr_r=0x02080000\0" \
+ "ramdisk_addr_r=0x0a200000\0"
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "partitions=" PARTS_DEFAULT \
+ ROCKCHIP_DEVICE_SETTINGS \
+ BOOTENV
+#endif
+
+#endif
--
2.17.1
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