[PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config

[Rick Chen]

Hi Bin,

> From: Bin Meng <bmeng.cn at gmail.com>
> Sent: Friday, June 04, 2021 1:51 PM
> To: Rick Jian-Zhi Chen(陳建志) <rick at andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang at andestech.com>; U-Boot Mailing List <u-boot at lists.denx.de>
> Subject: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config
>
> At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The intention was to use gdb to load device tree before running U-Boot SPL/proper from RAM. When we switch to OF_SEPARATE we will have to use our own DT but without "u-boot,dm-spl" in several essential nodes, SPL does not boot.

Can you describe how do you verify and provide the steps about that
SPL boot fail that I can duplicate it. :)

Thanks,
Rick.

>
> Let's add all the required "u-boot,dm-spl" for SPL config.
>
> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
> ---
>
>  arch/riscv/dts/ae350-u-boot.dtsi | 52 ++++++++++++++++++++++++++++++++
>  arch/riscv/dts/ae350_32.dts      |  1 +
>  arch/riscv/dts/ae350_64.dts      |  1 +
>  3 files changed, 54 insertions(+)
>  create mode 100644 arch/riscv/dts/ae350-u-boot.dtsi
>
> diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
> new file mode 100644
> index 0000000000..0d4201cfae
> --- /dev/null
> +++ b/arch/riscv/dts/ae350-u-boot.dtsi
> @@ -0,0 +1,52 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +/ {
> +       cpus {
> +               u-boot,dm-spl;
> +               CPU0: cpu at 0 {
> +                       u-boot,dm-spl;
> +                       CPU0_intc: interrupt-controller {
> +                               u-boot,dm-spl;
> +                       };
> +               };
> +               CPU1: cpu at 1 {
> +                       u-boot,dm-spl;
> +                       CPU1_intc: interrupt-controller {
> +                               u-boot,dm-spl;
> +                       };
> +               };
> +               CPU2: cpu at 2 {
> +                       u-boot,dm-spl;
> +                       CPU2_intc: interrupt-controller {
> +                               u-boot,dm-spl;
> +                       };
> +               };
> +               CPU3: cpu at 3 {
> +                       u-boot,dm-spl;
> +                       CPU3_intc: interrupt-controller {
> +                               u-boot,dm-spl;
> +                       };
> +               };
> +       };
> +
> +       memory at 0 {
> +               u-boot,dm-spl;
> +       };
> +
> +       soc {
> +               u-boot,dm-spl;
> +
> +               plic1: interrupt-controller at e6400000 {
> +                       u-boot,dm-spl;
> +               };
> +
> +               plmt0 at e6000000 {
> +                       u-boot,dm-spl;
> +               };
> +       };
> +
> +       serial0: serial at f0300000 {
> +               u-boot,dm-spl;
> +       };
> +
> +};
> diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 70576846f2..083f676333 100644
> --- a/arch/riscv/dts/ae350_32.dts
> +++ b/arch/riscv/dts/ae350_32.dts
> @@ -3,6 +3,7 @@
>  /dts-v1/;
>
>  #include "binman.dtsi"
> +#include "ae350-u-boot.dtsi"
>
>  / {
>         #address-cells = <1>;
> diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 564e94a1db..74cff9122d 100644
> --- a/arch/riscv/dts/ae350_64.dts
> +++ b/arch/riscv/dts/ae350_64.dts
> @@ -3,6 +3,7 @@
>  /dts-v1/;
>
>  #include "binman.dtsi"
> +#include "ae350-u-boot.dtsi"
>
>  / {
>         #address-cells = <2>;
> --
> 2.25.1
>
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