[RFT PATCH] riscv: andes_plic: Fix riscv_get_ipi() mask

[Bin Meng]

Current logic in riscv_get_ipi() for Andes PLICSW does not look good
to me. The mask to test IPI pending bits for a hart should be left
shifted by (8 * gd->arch.boot_hart), just the same as what is done in
riscv_send_ipi().

Signed-off-by: Bin Meng <bmeng.cn at gmail.com>

---
It looks there is no datasheet released from Andes that describes how
PLICSW works, and its register fields. I can only get an understanding
from current U-Boot and OpenSBI PLICSW driver.

This requires testing on Andes hardware, which I don't have access to.

 arch/riscv/lib/andes_plic.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 221a5fe324..5e113ee8c9 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -105,9 +105,11 @@ int riscv_clear_ipi(int hart)
 
 int riscv_get_ipi(int hart, int *pending)
 {
+	unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+
 	*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
 						     gd->arch.boot_hart));
-	*pending = !!(*pending & SEND_IPI_TO_HART(hart));
+	*pending = !!(*pending & ipi);
 
 	return 0;
 }
-- 
2.25.1