[PATCH v3 05/11] clk: k210: Re-add support for setting rate

[Leo Liang]

On Fri, Jun 11, 2021 at 12:16:11PM +0800, Sean Anderson wrote:
> This adds support for setting clock rates, which was left out of the
> initial CCF expunging. There are several tricky bits here, mostly related
> to the PLLS:
> 
> * The PLL's bypass is broken. If the PLL is reconfigured, any child clocks
>   will be stopped.
> * PLL0 is the parent of ACLK which is the CPU and SRAM's clock. To prevent
>   stopping the CPU while we configure PLL0's rate, ACLK is reparented
>   to IN0 while PLL0 is disabled.
> * PLL1 is the parent of the AISRAM clock. This clock cannot be reparented,
>   so we instead just disallow changing PLL1's rate after relocation (when
>   we are using the AISRAM).
> 
> Signed-off-by: Sean Anderson <seanga2 at gmail.com>
> ---
> 
> Changes in v3:
> - Fix inverted condition for setting defaults
> - Fix val not being set for K210_DIV_POWER
> 
> Changes in v2:
> - Only force probe clocks pre-reloc
> 
>  drivers/clk/kendryte/clk.c | 89 +++++++++++++++++++++++++++++++++++---
>  1 file changed, 84 insertions(+), 5 deletions(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>