[PULL] u-boot-riscv/next

[Tom Rini]

On Wed, Jun 16, 2021 at 04:28:21PM +0800, Leo Liang wrote:
> On Wed, Jun 16, 2021 at 04:07:26PM +0800, Bin Meng wrote:
> > Hi Leo,
> > 
> > On Wed, Jun 16, 2021 at 3:44 PM Leo Liang <ycliang at andestech.com> wrote:
> > >
> > > Hi Tom,
> > >
> > > Please pull u-boot-riscv/next into -next.
> > >
> > > The following changes on the "next" branch since commit c4737cd594b5c4c47aff789fc53f7dd36ed03c94:
> > >
> > >   Merge tag 'xilinx-for-v2021.07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-microblaze (2021-06-11 08:29:34 -0400)
> > >
> > > are available in the Git repository at:
> > >
> > >   git at source.denx.de:u-boot/custodians/u-boot-riscv.git
> > >
> > > for you to fetch changes up to efbcd66af3c83b14efb72eb38f73cd4af8128208:
> > >
> > >   test: Add K210 PLL tests to sandbox defconfigs (2021-06-16 10:04:23 +0800)
> > >
> > > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7856
> > >
> > > ----------------------------------------------------------------
> > > Bin Meng (6):
> > >       riscv: ae350: dts: Add SPDX license header
> > >       riscv: ae350: dts: Remove the unnecessary space in bootargs
> > >       riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
> > >       riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
> > >       riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config
> > >       riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT
> > 
> > It seems this patch is missing?
> > 
> > riscv: andes_plic: Fix riscv_get_ipi() mask
> > http://patchwork.ozlabs.org/project/uboot/patch/20210615054557.376750-1-bmeng.cn@gmail.com/
> > 
> > Regards,
> > Bin
> 
> Hi Bin,
> 
> Sorry, I must have omitted it by accident.
> 
> Hi Tom,
> 
> Could you drop this PR ?
> I will send another one including the patch Bin mentioned.
> Thanks!

Will do.

-- 
Tom
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