[PULL] u-boot-riscv/master

Leo Liang ycliang at andestech.com
Thu Jun 17 05:31:12 CEST 2021

Hi Tom,

The following changes since commit 9301a5cc99dd0c298e2f7fe2fa98a7287fcda772:

  Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2021-06-15 08:23:04 -0400)

are available in the Git repository at:

  git at source.denx.de:u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 62ce0a02f9e5bda51a05c5f735e5a75f6c4bbb54:

  riscv: andes_plic: Fix riscv_get_ipi() mask (2021-06-17 09:39:46 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7864

Bin Meng (7):
      riscv: ae350: dts: Add SPDX license header
      riscv: ae350: dts: Remove the unnecessary space in bootargs
      riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
      riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
      riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config
      riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT
      riscv: andes_plic: Fix riscv_get_ipi() mask

 arch/riscv/dts/ae350-u-boot.dtsi   | 52 ++++++++++++++++++++++++++++++++++++++
 arch/riscv/dts/ae350_32.dts        |  9 ++++---
 arch/riscv/dts/ae350_64.dts        |  7 ++---
 arch/riscv/lib/andes_plic.c        |  4 ++-
 doc/board/AndesTech/ax25-ae350.rst | 19 +++-----------
 5 files changed, 68 insertions(+), 23 deletions(-)
 create mode 100644 arch/riscv/dts/ae350-u-boot.dtsi

 Best regards,

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