[PATCH v2] Revert "mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output"
festevam at gmail.com
Thu Jun 17 21:19:30 CEST 2021
On Mon, Jun 14, 2021 at 9:23 PM Peng Fan (OSS) <peng.fan at oss.nxp.com> wrote:
> Do you have a chance to see where it consumes so much time?
Here is the place it consumes too much time. Here is an example on a
U-Boot 2021.07-rc3 (Jun 17 2021 - 18:30:37 +0000)
CPU: Freescale i.MX7S rev1.2 800 MHz (running at 792 MHz)
CPU: Extended Commercial temperature grade (-20C to 105C) at 42C
Reset cause: POR
Model: Warp i.MX7 Board
Board: WARP7 in secure mode OPTEE DRAM 0x9d000000-0xa0000000
DRAM: 464 MiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC: FSL_SDHC: 3, FSL_SDHC: 0
Loading Environment from MMC... (takes 10 seconds to continue) OK
Can we go with the revert to avoid such regression?
More information about the U-Boot