[PATCH] board: stm32mp1: correct the property name for eth

[Patrice CHOTARD]

Hi Patrick

It seems that my previous reviewed-by of this patch encountered an issue, so do it again.

On 6/4/21 6:30 PM, Patrick Delaunay wrote:
> Use the correct name for STMicroelectronics phys config properties,
> replace '_' by '-':
>   "st,eth_clk_sel" => "st,eth-clk-sel"
>   "st,eth-ref-clk-sel" => st,eth-clk-sel"
> 
> These property name are aligned with the upstreamed Linux kernel binding:
>  linux/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
> 
> See Linux kernel commit "dt-bindings: net: stmmac: add phys config
> properties" merged in v5.1-rc1.
> 
> This patch allow to reuse the kernel device tree directly in U-Boot.
> 
> Signed-off-by: Patrick Delaunay <patrick.delaunay at foss.st.com>
> ---
> 
>  board/dhelectronics/dh_stm32mp1/board.c | 4 ++--
>  board/st/stm32mp1/stm32mp1.c            | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
> index ac1af718d4..d7c1857c16 100644
> --- a/board/dhelectronics/dh_stm32mp1/board.c
> +++ b/board/dhelectronics/dh_stm32mp1/board.c
> @@ -660,11 +660,11 @@ int board_interface_eth_init(struct udevice *dev,
>  	bool eth_ref_clk_sel_reg = false;
>  
>  	/* Gigabit Ethernet 125MHz clock selection. */
> -	eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
> +	eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
>  
>  	/* Ethernet 50Mhz RMII clock selection */
>  	eth_ref_clk_sel_reg =
> -		dev_read_bool(dev, "st,eth_ref_clk_sel");
> +		dev_read_bool(dev, "st,eth-ref-clk-sel");
>  
>  	syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
>  
> diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
> index 261ec15e1b..18b8870269 100644
> --- a/board/st/stm32mp1/stm32mp1.c
> +++ b/board/st/stm32mp1/stm32mp1.c
> @@ -733,11 +733,11 @@ int board_interface_eth_init(struct udevice *dev,
>  	bool eth_ref_clk_sel_reg = false;
>  
>  	/* Gigabit Ethernet 125MHz clock selection. */
> -	eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
> +	eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
>  
>  	/* Ethernet 50Mhz RMII clock selection */
>  	eth_ref_clk_sel_reg =
> -		dev_read_bool(dev, "st,eth_ref_clk_sel");
> +		dev_read_bool(dev, "st,eth-ref-clk-sel");
>  
>  	syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
>  
> 

Reviewed-by: Patrice Chotard <patrice.chotard at foss.st.com>

Thanks
Patrice