[PATCH v9 00/28] mtd: spi-nor-core: add xSPI Octal DTR support

Jagan Teki jagan at amarulasolutions.com
Wed Jun 23 14:02:28 CEST 2021

On Wed, May 5, 2021 at 3:11 PM Pratyush Yadav <p.yadav at ti.com> wrote:
> Hi,
> This series adds support for octal DTR flashes in the SPI NOR framework,
> and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA
> flashes.
> The Cadence QSPI controller driver is also updated to run in Octal DTR
> mode.
> Tested on TI J721E for MT35XU512ABA and J7200 for S28HS512T. Also tested
> on MT25QU512A for regressions.
> Changes in v9:
> - Fix a typo in patch 26 commit message.
> - Add Sean's Reviewed-by in patch 3.
> - Drop the 2-byte check from spi_mem_dtr_supports_op(). Instead, perform
>   a even-byte length check on all 4 phases. Only do this when the
>   buswidth of the phase is 8.
> - Make template ops in spi_nor_check_readop() and spi_nor_check_pp()
>   have 2-byte data phase so they don't get rejected when 8D-8D-8D
>   protocol is being used.
> Changes in v8:
> - Rebase on latest master, fixing merge conflicts.
> - Fix a regression related to address width that was discovered on
>   Linux.
> - Port spi_mem_dtr_supports_op() from Linux and use it in Cadence qspi
>   driver.
> - Do not set non-volatile Uniform Sector mode bit on S28HS512T. Instead
>   use Takahiro's non-uniform erase patch to enable non-uniform erases.
> - Make sure spi_nor_write_reg() does not set data direction to out when
>   there is no data to write, like in write enable.
> - Set buswidths to 0 before calling spi_nor_setup_op(), like how it is
>   done in Linux.
> Changes in v7:
> - Port back changes requested on the Linux series.
> - Introduce the flag SPI_NOR_OCTAL_DTR_PP to indicate 8D page program
>   support since it can't be detected from SFDP.
> - Re-order Profile 1.0 related defines by DWORD order.
> - Drop local variables addr_width and dummy in spi_nor_read_sr()
>   spi_nor_read_fsr().
> - Do not make having command opcode extension as a reserved field fatal.
> - Update doc comment for spi_nor_parse_profile1() and
>   spi_nor_cypress_octal_dtr_enable() to add missing fields.
> - Move rdsr parameter parsing to where opcode is parsed because it is
>   from the same DWORD.
> - Convert a comment in Profile 1.0 parsing from multi-line to one line.
> - Rename 'table' to 'dwords' in xSPI Profile 1.0 parsing.
> - Update spi_nor_check_readop() and spi_nor_check_pp() to use
>   spi_nor_setup_op() so the buswidths are properly set up for DTR ops.
> - Do not set Uniform Sector bit on the Cypress S28HS512T flash if it is
>   already set. It will avoid wearing out the non-volatile bit.
> - Enable DQS for Micron MT35XU512ABA. No reason not to.
> - Avoid enabling 4-byte addressing mode for all DTR ops instead of just
>   Octal DTR ops. This is based on the assumption that DTR ops can only
>   use 4-byte addressing.
> - Make spi_nor_set_fixups() static.
> - Add flag SPI_NOR_OCTAL_DTR_PP to both Cypress S28HS512T and Micron
>   MT35XU512ABA.
> - Use values set up by spi-{rx,tx}-bus-width via device tree to
>   determine if the controller supports the op or not. Gives more
>   flexibility to choose protocol per-board.
> - Use tiny SPI NOR on x530 because of size constraints.
> Changes in v6:
> - Use "# CONFIG_SPI_FLASH_SMART_HWCAPS is not set" instead of
>   "CONFIG_SPI_FLASH_SMART_HWCAPS=n" in x530_defconfig.
> Changes in v5:
> - Fix build breaking when CONFIG_SPL_SPI_FLASH_TINY is enabled because
>   spi-nor-tiny did not have spi_nor_remove().
> - The build was breaking in x530 because of SPL size too big. Fix it by
>   the below changes.
> - Re-introduce old hwcaps selection logic and put the new one behind a
>   config. This lets boards with size restrictions use the old logic
>   which takes up less space. The code was getting hard to manage with
>   the old code behind ifdefs. So, re-structure the old hwcaps selection
>   logic and move it into one function: spi_nor_adjust_hwcaps(). This
>   way, the common code just calls spi_nor_adjust_hwcaps(), but the old
>   or new hwcaps selection is used based on the config option selected.
> - Put spi_nor_soft_reset() behind the config option SPI_NOR_SOFT_RESET.
> - Rename the config option used for soft resetting on boot to
>   SPI_NOR_SOFT_RESET_ON_BOOT to make its intention clearer.
> - Put the fixup hooks of MT35XU512ABA and S28HS512T flashes behind
>   config options to reduce code size on platforms that don't need them.
> - Introduce spi_nor_set_fixups(). Earlier, the fixup members of each
>   flash was specified in spi-nor-ids.c. This meant they had to be
>   declared as extern in sf_internal.h. But since spi-nor-tiny.c also
>   uses it, and it doesn't have those fixups, they had to be put behind
>   in an ifdef. The ".fixups = " assignment in spi-nor-ids.c also had to
>   be put in an ifdef to account for spi-nor-tiny.c not having the fixup
>   hooks. On top of this, the fixup of each flash is behind the flash's
>   config.
>   All this lead to a soup of ifdefs that wasn't easy to digest. So don't
>   set the fixups in the common code. Instead, add a function in
>   spi-nor-core.c that sets the fixups of each flash. This isn't ideal,
>   but its the best compromise I could figure out.
> - Build were breaking with boards that use spi-mem-nodm.c because it
>   doesn't have spi_mem_supports_op() which is needed for smart hwcaps
>   selection. Add an equivalent to spi_mem_default_supports_op() there.
> - Replace uses of sizeof(op->cmd.opcode) with op->cmd.nbytes.
> - Do not set quad_enable to NULL if the value is set to reserved.
>   Instead just print a warning and go on. quad_enable should be set to
>   NULL in fixup hooks instead. Suggested on the Linux list.
> - Set dummy cycles for DTR mode in spi_nor_micron_octal_dtr_enable()
>   instead of in the post sfdp hook. This keeps the flash functional in
>   case Octal DTR mode is not selected.
> - Only use nor->rdsr_addr_nbytes and nor->rdsr_dummy when in Octal DTR
>   mode. This makes sure the flash is functional in case Octal DTR is not
>   selected.
> - Rebase on latest master and fix a small merge conflict.
> Changes in v4:
> - Fix BFPT parsing stopping too early for JESD216 rev B flashes.
> - Instead of just checking for spi_nor_get_protocol_width() in
>   spi_nor_octal_dtr_enable(), make sure the protocol is
>   SNOR_PROTO_8_8_8_DTR since get_protocol_width() only cares about data
>   width.
> - Do not enable stateful X-X-X modes if the reset line is broken.
> - Instead of setting SNOR_READ_HWCAPS_8_8_8_DTR from Profile 1.0 table
>   parsing, do it in spi_nor_info_init_params() instead based on the
>   SPI_NOR_OCTAL_DTR_READ flag instead.
> - Set SNOR_HWCAPS_PP_8_8_8_DTR in s28hs post_sfdp hook since this
>   capability is no longer set in Profile 1.0 parsing.
> - Rename spi_nor_cypress_octal_enable() to
>   spi_nor_cypress_octal_dtr_enable().
> - Instead of hard-coding 8D-8D-8D Fast Read dummy cycles to 20, find
>   them out from the Profile 1.0 table.
> - Call post-bfpt fixup when exiting early because of JESD rev A.
> - Do not make an invalid Quad Enable BFPT field a fatal error. Silently
>   ignore it by assuming no quad enable bit is present.
> - Set cmd.nbytes to 1 when using SPI_MEM_OP_CMD().
> - Reject ops with more than 1 command byte in
>   spi_mem_default_supports_op().
> - Drop flag SPI_NOR_SOFT_RESET. Instead, discover soft reset capability
>   via BFPT.
> - Add missing headers that were removed from common header.
> Changes in v3:
> - Read 2 bytes in Octal DTR mode when reading SR and FSR to avoid
>   tripping up controllers.
> - Use op->data.nbytes as a measure of whether the data phase exists or
>   not. This fixes data buswidth not being updadted for SR and FSR reads
>   because they keep data buffer as NULL when calling spi_nor_setup_op().
> - Add support for Micron mt35xu512aba to run in Octal DTR mode.
> Pratyush Yadav (27):
>   spi: spi-mem: allow specifying whether an op is DTR or not
>   spi: spi-mem: allow specifying a command's extension
>   spi: spi-mem: export spi_mem_default_supports_op()
>   spi: spi-mem: add spi_mem_dtr_supports_op()
>   spi: cadence-qspi: Do not calibrate when device tree sets read delay
>   spi: cadence-qspi: Add a small delay before indirect writes
>   spi: cadence-qspi: Add support for octal DTR flashes
>   arm: mvebu: x530: Use tiny SPI NOR
>   mtd: spi-nor-core: Fix address width on flash chips > 16MB
>   mtd: spi-nor-core: Add a ->setup() hook
>   mtd: spi-nor-core: Move SFDP related declarations to top
>   mtd: spi-nor-core: Introduce flash-specific fixup hooks
>   mtd: spi-nor-core: Rework hwcaps selection
>   mtd: spi-nor-core: Do not set data direction when there is no data
>   mtd: spi-nor-core: Add support for DTR protocol
>   mtd: spi-nor-core: prepare BFPT parsing for JESD216 rev D
>   mtd: spi-nor-core: Get command opcode extension type from BFPT
>   mtd: spi-nor-core: Parse xSPI Profile 1.0 table
>   mtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode
>   mtd: spi-nor-core: Enable octal DTR mode when possible
>   mtd: spi-nor-core: Do not make invalid quad enable fatal
>   mtd: spi-nor-core: Detect Soft Reset sequence support from BFPT
>   mtd: spi-nor-core: Perform a Soft Reset on shutdown
>   mtd: spi-nor-core: Perform a Soft Reset on boot
>   mtd: spi-nor-core: allow truncated erases
>   mtd: spi-nor-core: Add support for Cypress Semper flash
>   mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode
> Takahiro Kuwano (1):
>   mtd: spi-nor-core: Add non-uniform erase for Spansion/Cypress

I found some merge conflicts, can you resend on top of u-boot-spi/master?


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