[v10,14/27] mtd: spi-nor-core: Add support for DTR protocol
jaimeliao at mxic.com.tw
jaimeliao at mxic.com.tw
Tue Jun 29 03:32:05 CEST 2021
Hi Pratyush
In the [v10,14/27]
@@ -2767,7 +2858,10 @@ int spi_nor_scan(struct spi_nor *nor)
if (ret)
return ret;
- if (nor->addr_width) {
+ if (spi_nor_protocol_is_dtr(nor->read_proto)) {
+ /* Always use 4-byte addresses in DTR
mode. */
+ nor->addr_width = 4;
+ } else if (nor->addr_width) {
/* already configured from SFDP */
} else if (info->addr_width) {
nor->addr_width = info->addr_width;
In the [v10,8/27]
@@ -2603,7 +2603,11 @@ int spi_nor_scan(struct spi_nor *nor)
/* already configured from SFDP */
} else if (info->addr_width) {
nor->addr_width = info->addr_width;
- } else if (mtd->size > SZ_16M) {
+ } else {
+ nor->addr_width = 3;
+ }
+
+ if (nor->addr_width == 3 && mtd->size > SZ_16M) {
#ifndef CONFIG_SPI_FLASH_BAR
/* enable 4-byte addressing if the device
exceeds 16MiB */
nor->addr_width = 4;
For this part, nor->addr_width will be set to 4 if spi-nor protocol is DTR
mode.
Judgement "if (nor->addr_width == 3 && mtd->size > SZ_16M)" will not be
triggered
and spi_nor_set_4byte_opcodes will not execute. So that driver still using
3-bytes
opcode in DTR mode. I think it is not convenient for every flash vendors
to add
xxx_post_sfdp_fixup() for setting pp and erase opcode in different
protocol.
Would you consider to follow the linux method?
Thanks
Jaime
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