[PATCH 3/6] clk: sunxi: v3s: fix tabs / spaces

[Andreas Rehn]

Both didn't align with the rest of the list on my side.

this patch is not important for the functionality so
we can drop this if this only apppears on my machine.

greetings
Andreas

Am Mi., 19. Mai 2021 um 23:43 Uhr schrieb Andre Przywara <
andre.przywara at arm.com>:

> On Wed, 19 May 2021 21:42:05 +0200
> Andreas Rehn <rehn.andreas86 at gmail.com> wrote:
>
> Hi,
>
> > align CLK_SPI0 and CLK_USB_PHY0 with tabs
> >
> > Signed-off-by: Andreas Rehn <rehn.andreas86 at gmail.com>
> > ---
> >  drivers/clk/sunxi/clk_v3s.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
> > index 55fc597043..9c2717bfab 100644
> > --- a/drivers/clk/sunxi/clk_v3s.c
> > +++ b/drivers/clk/sunxi/clk_v3s.c
> > @@ -27,9 +27,9 @@ static struct ccu_clk_gate v3s_gates[] = {
> >
> >       [CLK_BUS_EPHY]          = GATE(0x070, BIT(0)),
> >
> > -     [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
> > +     [CLK_SPI0]                      = GATE(0x0a0, BIT(31)),
>
> What is the problem with this line? This is already using tabs and is
> correctly aligned already? Are you using a tab length other than 8, by
> any chance?
>
> >
> > -     [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
> > +     [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
>
> This change looks fine.
>
> Cheers,
> Andre.
>
> >  };
> >
> >  static struct ccu_reset v3s_resets[] = {
>
>

-- 
Mit freundlichen Grüßen / kind regards
Andreas Rehn | Master of Engineering (M.Eng)