[PATCH 0/8] pci: pci_mvebu: Fix access to config space and PCIe Root Port

[Stefan Roese]

On 22.10.21 16:22, Pali Rohár wrote:
> This patch series fixes access to config space and fixes issues with the
> mysterious "Memory controller" PCI device (which is PCIe Root Port).
> 
> Tested on Armada 385 Turris Omnia device which has 3 mPCIe slots.
> PCIe Root Port device is available for each slot on separate bus and has
> PCI Bridge class code as required by PCIe base specifications.
> 
> => pci 0
> Scanning PCI devices on bus 0
> BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
> _____________________________________________________________
> 00.00.00   0x11ab     0x6820     Bridge device           0x04
> => pci 1
> Scanning PCI devices on bus 1
> BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
> _____________________________________________________________
> 01.00.00   0x168c     0x003c     Network controller      0x80
> => pci 2
> Scanning PCI devices on bus 2
> BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
> _____________________________________________________________
> 02.00.00   0x11ab     0x6820     Bridge device           0x04
> => pci 3
> Scanning PCI devices on bus 3
> BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
> _____________________________________________________________
> 03.00.00   0x168c     0x003c     Network controller      0x80
> => pci 4
> Scanning PCI devices on bus 4
> BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
> _____________________________________________________________
> 04.00.00   0x11ab     0x6820     Bridge device           0x04
> => pci 5
> Scanning PCI devices on bus 5
> BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
> _____________________________________________________________
> 05.00.00   0x168c     0x002e     Network controller      0x80
> => pci 6
> No such bus
> =>
> 
> U-Boot command "pci display.b 0.0.0 0 200" will display config space of
> the first PCIe Root Port device with the Type 1 PCI header as required by
> PCIe base specification.
> 
> => pci display.b 0.0.0 0 200
> 00000000: ab 11 20 68 07 00 10 00 04 00 04 06 00 00 01 00
> 00000010: 00 00 00 00 00 00 00 00 00 01 01 00 01 f1 00 00
> 00000020: 00 c0 20 c0 01 10 01 00 00 00 00 00 00 00 00 00
> 00000030: 10 f1 0f f1 40 00 00 00 00 00 00 00 00 01 00 00
> 00000040: 01 50 03 06 00 00 00 00 00 00 00 00 00 00 00 00
> 00000050: 05 60 80 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00000060: 10 00 42 00 80 80 00 00 00 20 00 00 12 ac 07 00
> 00000070: 00 00 11 10 00 00 00 00 00 00 40 00 00 00 00 00
> 00000080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00000090: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000000b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000000c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000000d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000000e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00000100: 01 00 01 00 00 00 00 00 00 00 00 00 10 00 06 00
> 00000110: 00 00 00 00 00 20 00 00 00 00 00 00 01 00 00 4a
> 00000120: 04 00 00 01 00 01 08 01 02 80 00 00 00 00 00 00
> 00000130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00000140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00000150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00000160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00000170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00000180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00000190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000001a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000001b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000001c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000001d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000001e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000001f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> Pali Rohár (8):
>    pci: pci_mvebu: Fix write_config() with PCI_SIZE_8 or PCI_SIZE_16
>    pci: pci_mvebu: Fix read_config() with PCI_SIZE_8 or PCI_SIZE_16
>    pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port)
>    pci: pci_mvebu: Remove unused functions
>    pci: pci_mvebu: Fix place of link up detection
>    pci: pci_mvebu: Do not automatically enable bus mastering on PCI
>      Bridge
>    pci: pci_mvebu: Setup PCI controller to Root Complex mode
>    pci: pci_mvebu: Fix comment about driver class name
> 
>   drivers/pci/pci_mvebu.c | 275 +++++++++++++++++++++++++++++-----------
>   1 file changed, 202 insertions(+), 73 deletions(-)
> 

Applied to u-boot-marvell/master

Thanks,
Stefan