[PATCH u-boot-marvell 1/9] arm: mvebu: a38x: serdes: Add comments and use macros in PCIe code

[Stefan Roese]

On 24.09.21 22:59, Marek Behún wrote:
> From: Pali Rohár <pali at kernel.org>
> 
> Replace magic register offsets by macros to make code more readable.
> Add comments about what this code is doing.
> 
> Signed-off-by: Pali Rohár <pali at kernel.org>
> Reviewed-by: Marek Behún <marek.behun at nic.cz>

Reviewed-by: Stefan Roese <sr at denx.de>

Thanks,
Stefan

> ---
>   .../serdes/a38x/high_speed_env_spec.c         | 37 +++++++++++++------
>   1 file changed, 25 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
> index 3b41c7d49b..09192acef2 100644
> --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
> +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
> @@ -1723,31 +1723,44 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
>   					reg_data &= ~0x4000;
>   				reg_write(SOC_CONTROL_REG1, reg_data);
>   
> -				reg_data =
> -				    reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
> -					      0x6c));
> +				/* Set Maximum Link Width to X1 or X4 */
> +				reg_data = reg_read(PEX_CFG_DIRECT_ACCESS(
> +						     pex_idx,
> +						     PEX_LINK_CAPABILITY_REG));
>   				reg_data &= ~0x3f0;
>   				if (is_pex_by1 == 1)
>   					reg_data |= 0x10;
>   				else
>   					reg_data |= 0x40;
> -				reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
> +				reg_write(PEX_CFG_DIRECT_ACCESS(
> +					   pex_idx,
> +					   PEX_LINK_CAPABILITY_REG),
>   					  reg_data);
>   
> -				reg_data =
> -				    reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
> -					      0x6c));
> +				/* Set Maximum Link Speed to 5 GT/s */
> +				reg_data = reg_read(PEX_CFG_DIRECT_ACCESS(
> +						     pex_idx,
> +						     PEX_LINK_CAPABILITY_REG));
>   				reg_data &= ~0xf;
>   				reg_data |= 0x2;
> -				reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
> +				reg_write(PEX_CFG_DIRECT_ACCESS(
> +					   pex_idx,
> +					   PEX_LINK_CAPABILITY_REG),
>   					  reg_data);
>   
> -				reg_data =
> -				    reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
> -					      0x70));
> +				/*
> +				 * Set Common Clock Configuration to indicates
> +				 * that both devices on the link use a
> +				 * distributed common reference clock.
> +				 */
> +				reg_data = reg_read(PEX_CFG_DIRECT_ACCESS(
> +						     pex_idx,
> +						     PEX_LINK_CTRL_STAT_REG));
>   				reg_data &= ~0x40;
>   				reg_data |= 0x40;
> -				reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70),
> +				reg_write(PEX_CFG_DIRECT_ACCESS(
> +					   pex_idx,
> +					   PEX_LINK_CTRL_STAT_REG),
>   					  reg_data);
>   			}
>   
> 


Viele Grüße,
Stefan

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