Subject: [PATCH 5/6] SoC: qcom: add support for SDM845
Ramon Fried
rfried.dev at gmail.com
Sun Sep 5 15:37:40 CEST 2021
On Tue, Aug 31, 2021 at 11:45 AM Дмитрий Санковский
<dsankouski at gmail.com> wrote:
>
> From 1deb063fe8d0e527b0fd412505b7614462c7fd19 Mon Sep 17 00:00:00 2001
> From: Dzmitry Sankouski <dsankouski at gmail.com>
> Date: Sun, 29 Aug 2021 21:55:31 +0300
> Subject: [PATCH 5/6] SoC: qcom: add support for SDM845
>
> Hi-end qualcomm chip, introduced in late 2017.
> Mostly used in flagship phones and tablets of 2018.
> Features:
> - arm64 arch
> - total of 8 Kryo 385 Gold / Silver cores
> - Hexagon 685 DSP
> - Adreno 630 GPU
>
> Tested only as second-stage bootloader.
>
> Signed-off-by: Dzmitry Sankouski <dsankouski at gmail.com>
> Cc: Ramon Fried <rfried.dev at gmail.com>
> ---
> arch/arm/dts/sdm845.dtsi | 118 ++++++++++++++++++
> arch/arm/mach-snapdragon/Kconfig | 4 +
> arch/arm/mach-snapdragon/Makefile | 4 +
> .../include/mach/sysmap-sdm845.h | 42 +++++++
> arch/arm/mach-snapdragon/init_sdm845.c | 82 ++++++++++++
> arch/arm/mach-snapdragon/sysmap-sdm845.c | 31 +++++
> include/configs/sdm845.h | 32 +++++
> 7 files changed, 313 insertions(+)
> create mode 100644 arch/arm/dts/sdm845.dtsi
> create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h
> create mode 100644 arch/arm/mach-snapdragon/init_sdm845.c
> create mode 100644 arch/arm/mach-snapdragon/sysmap-sdm845.c
> create mode 100644 include/configs/sdm845.h
>
> diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
> new file mode 100644
> index 0000000000..bf32c6995d
> --- /dev/null
> +++ b/arch/arm/dts/sdm845.dtsi
> @@ -0,0 +1,118 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Qualcomm SDM845 chip device tree source
> + *
> + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski at gmail.com>
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "skeleton64.dtsi"
> +
> +/ {
> + soc: soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
> + compatible = "simple-bus";
> +
> + gcc: clock-controller at 100000 {
> + u-boot,dm-pre-reloc;
> + compatible = "qcom,gcc-sdm845";
> + reg = <0x00100000 0x1f0000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + gpio_north: gpio_north at 3900000 {
> + u-boot,dm-pre-reloc;
> + #gpio-cells = <2>;
> + compatible = "qcom,sdm845-pinctrl";
> + reg = <0x3900000 0x400000>;
> + gpio-count = <150>;
> + gpio-controller;
> + gpio-ranges = <&gpio_north 0 0 150>;
> + gpio-bank-name = "soc_north.";
> + };
> +
> + tlmm_north: pinctrl_north at 3900000 {
> + u-boot,dm-pre-reloc;
> + compatible = "qcom,tlmm-sdm845";
> + reg = <0x03900000 0x400000>;
> + gpio-count = <150>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&tlmm_north 0 0 150>;
> +
> + /* DEBUG UART */
> + qup_uart9: qup-uart9-default {
> + pinmux {
> + pins = "GPIO_4", "GPIO_5";
> + function = "qup9";
> + };
> + };
> + };
> +
> + debug_uart: serial at 0xa84000 {
> + compatible = "qcom,msm-geni-uart";
> + reg = <0xa84000 0x4000>;
> + reg-names = "se_phys";
> + clock-names = "se-clk";
> + clocks = <&gcc 0x58>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart9>;
> + qcom,wrapper-core = <0x8a>;
> + status = "disabled";
> + };
> +
> + spmi at c440000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0xc440000 0x1100>,
> + <0xc600000 0x2000000>,
> + <0xe600000 0x100000>;
> + reg-names = "cnfg", "core", "obsrvr";
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> +
> + qcom,revid at 100 {
> + compatible = "qcom,qpnp-revid";
> + reg = <0x100 0x100>;
> + linux,phandle = <0x3ac>;
> + phandle = <0x3ac>;
> + };
> +
> + pmic0: pm8998 at 0 {
> + compatible = "qcom,spmi-pmic";
> + reg = <0x0 0x1>;
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> +
> + pm8998_pon: pm8998_pon at 800 {
> + compatible = "qcom,pm8998-pwrkey";
> + reg = <0x800 0x100>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + gpio-bank-name="pm8998_key.";
> + };
> +
> + pm8998_gpios: pm8998_gpios at c000 {
> + compatible = "qcom,pm8998-gpio";
> + reg = <0xc000 0x1a00>;
> + gpio-controller;
> + gpio-count = <21>;
> + #gpio-cells = <2>;
> + gpio-bank-name="pm8998.";
> + };
> + };
> +
> + pmic1: pm8998 at 1 {
> + compatible = "qcom,spmi-pmic";
> + reg = <0x1 0x0>;
> + #address-cells = <0x2>;
> + #size-cells = <0x0>;
> + };
> + };
> + };
> +};
> diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
> index 0ec74fa5d3..1a6a608967 100644
> --- a/arch/arm/mach-snapdragon/Kconfig
> +++ b/arch/arm/mach-snapdragon/Kconfig
> @@ -9,6 +9,10 @@ config SYS_MALLOC_F_LEN
> config SPL_SYS_MALLOC_F_LEN
> default 0x2000
>
> +config SDM845
> + bool "Qualcomm Snapdragon 845 SoC"
> + default n
> +
> choice
> prompt "Snapdragon board select"
>
> diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
> index 709919fce4..962855eb8c 100644
> --- a/arch/arm/mach-snapdragon/Makefile
> +++ b/arch/arm/mach-snapdragon/Makefile
> @@ -2,6 +2,9 @@
> #
> # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski at gmail.com>
>
> +obj-$(CONFIG_SDM845) += clock-sdm845.o
> +obj-$(CONFIG_SDM845) += sysmap-sdm845.o
> +obj-$(CONFIG_SDM845) += init_sdm845.o
> obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
> obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
> obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
> @@ -12,3 +15,4 @@ obj-y += dram.o
> obj-y += pinctrl-snapdragon.o
> obj-y += pinctrl-apq8016.o
> obj-y += pinctrl-apq8096.o
> +obj-$(CONFIG_SDM845) += pinctrl-sdm845.o
> diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h b/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h
> new file mode 100644
> index 0000000000..7165985bcd
> --- /dev/null
> +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Qualcomm SDM845 sysmap
> + *
> + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski at gmail.com>
> + */
> +#ifndef _MACH_SYSMAP_SDM845_H
> +#define _MACH_SYSMAP_SDM845_H
> +
> +#define TLMM_BASE_ADDR (0x1010000)
> +
> +/* Strength (sdc1) */
> +#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000)
> +
> +/* Clocks: (from CLK_CTL_BASE) */
> +#define GPLL0_STATUS (0x0000)
> +#define APCS_GPLL_ENA_VOTE (0x52000)
> +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004)
> +
> +#define SDCC2_BCR (0x14000) /* block reset */
> +#define SDCC2_APPS_CBCR (0x14004) /* branch control */
> +#define SDCC2_AHB_CBCR (0x14008)
> +#define SDCC2_CMD_RCGR (0x1400c)
> +#define SDCC2_CFG_RCGR (0x14010)
> +#define SDCC2_M (0x14014)
> +#define SDCC2_N (0x14018)
> +#define SDCC2_D (0x1401C)
> +
> +#define RCG2_CFG_REG 0x4
> +#define M_REG 0x8
> +#define N_REG 0xc
> +#define D_REG 0x10
> +
> +#define SE9_AHB_CBCR (0x25004)
> +#define SE9_UART_APPS_CBCR (0x29004)
> +#define SE9_UART_APPS_CMD_RCGR (0x18148)
> +#define SE9_UART_APPS_CFG_RCGR (0x1814C)
> +#define SE9_UART_APPS_M (0x18150)
> +#define SE9_UART_APPS_N (0x18154)
> +#define SE9_UART_APPS_D (0x18158)
> +
> +#endif
> diff --git a/arch/arm/mach-snapdragon/init_sdm845.c b/arch/arm/mach-snapdragon/init_sdm845.c
> new file mode 100644
> index 0000000000..5f53c21947
> --- /dev/null
> +++ b/arch/arm/mach-snapdragon/init_sdm845.c
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Common init part for boards based on SDM845
> + *
> + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski at gmail.com>
> + */
> +
> +#include <init.h>
> +#include <env.h>
> +#include <common.h>
> +#include <asm/system.h>
> +#include <asm/gpio.h>
> +#include <dm.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + return fdtdec_setup_mem_size_base();
> +}
> +
> +void reset_cpu(void)
> +{
> + psci_system_reset();
> +}
> +
> +__weak int board_init(void)
> +{
> + return 0;
> +}
> +
> +/* Check for vol- and power buttons */
> +__weak int misc_init_r(void)
> +{
> + struct udevice *pon;
> + struct gpio_desc resin;
> + int node, ret;
> +
> + ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8998_pon at 800", &pon);
> + if (ret < 0) {
> + printf("Failed to find PMIC pon node. Check device tree\n");
> + return 0;
> + }
> +
> + node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
> + "key_vol_down");
> + if (node < 0) {
> + printf("Failed to find key_vol_down node. Check device tree\n");
> + return 0;
> + }
> + if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
> + &resin, 0)) {
> + printf("Failed to request key_vol_down button.\n");
> + return 0;
> + }
> + if (dm_gpio_get_value(&resin)) {
> + env_set("key_vol_down", "1");
> + printf("Volume down button pressed\n");
> + } else {
> + env_set("key_vol_down", "0");
> + }
> +
> + node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
> + "key_power");
> + if (node < 0) {
> + printf("Failed to find key_power node. Check device tree\n");
> + return 0;
> + }
> + if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
> + &resin, 0)) {
> + printf("Failed to request key_power button.\n");
> + return 0;
> + }
> + if (dm_gpio_get_value(&resin)) {
> + env_set("key_power", "1");
> + printf("Power button pressed\n");
> + } else {
> + env_set("key_power", "0");
> + }
> +
> + return 0;
> +}
> diff --git a/arch/arm/mach-snapdragon/sysmap-sdm845.c b/arch/arm/mach-snapdragon/sysmap-sdm845.c
> new file mode 100644
> index 0000000000..721ac41166
> --- /dev/null
> +++ b/arch/arm/mach-snapdragon/sysmap-sdm845.c
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Qualcomm SDM845 memory map
> + *
> + * (C) Copyright 2021 Dzmitry Sankouski <dsankousk at gmail.com>
> + */
> +
> +#include <common.h>
> +#include <asm/armv8/mmu.h>
> +
> +static struct mm_region sdm845_mem_map[] = {
> + {
> + .virt = 0x0UL, /* Peripheral block */
> + .phys = 0x0UL, /* Peripheral block */
> + .size = 0x10000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + .virt = 0x80000000UL, /* DDR */
> + .phys = 0x80000000UL, /* DDR */
> + .size = 0x200000000UL, /* 8GiB - maximum allowed memory */
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE
> + }, {
> + /* List terminator */
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = sdm845_mem_map;
> diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h
> new file mode 100644
> index 0000000000..f53adb773a
> --- /dev/null
> +++ b/include/configs/sdm845.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Configuration file for boards, based on Qualcomm SDM845 chip
> + *
> + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski at gmail.com>
> + */
> +
> +#ifndef __CONFIGS_SDM845_H
> +#define __CONFIGS_SDM845_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/sysmap-sdm845.h>
> +
> +#define CONFIG_SYS_LOAD_ADDR 0x80000000
> +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
> +
> +/* Generic Timer Definitions */
> +#define COUNTER_FREQUENCY 19000000
> +
> +#define EXTRA_ENV_SETTINGS \
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "loadaddr=0x80000000\0"
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
> +
> +/* Monitor Command Prompt */
> +#define CONFIG_SYS_CBSIZE 512
> +#define CONFIG_SYS_MAXARGS 64
> +
> +#endif
> --
> 2.20.1
>
Reviewed-by: Ramon Fried <rfried.dev at gmail.com>
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