[u-boot PATCH] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge

[Nishanth Menon]

On 16:27-20210907, Tom Rini wrote:
> On Tue, Sep 07, 2021 at 09:41:23PM +0200, Jan Kiszka wrote:
> > On 02.09.21 08:36, Jan Kiszka wrote:
> > > On 28.07.21 11:10, Jan Kiszka wrote:
> > >> On 30.01.20 09:05, Roger Quadros wrote:

[...]

> > >>>  #endif /* __ASM_ARCH_AM6_HARDWARE_H */
> > >>>
> > >>
> > >> This was never merged, not even commented on (only apparently rejected
> > >> in patchwork) - but it is crucial as we now found out:
> > >>
> > >> prueth will quickly stall when these priorities are not applied, at
> > >> least with SR1.0-based AM65x designs. And you probably know what else
> > >> could go wrong. Please clarify and merge, possibly reducing the scope to
> > >> SR1.0 if you can confirm that SR2.0 cannot be affected by design (I can
> > >> only say this based on few practical experiments here).
> > >>
> > >> If it was good for several TI SDK releases by now, at least something
> > >> similar should be good for upstream as well, I believe.
> > >>
> > > 
> > > Ping. We need at least some confirmation on what is actually needed.
> > > Then, if you do not like to add it to the generic path, it would be easy
> > > for us to carry it in the IOT2050 board init only - with the appropriate
> > > condition check.
> > 
> > Did some more experiments on SR2 silicon, and while I'm not seeing
> > stalls without this patch there, iperf tests with prueth show high retry
> > rates and, thus, about 10% worse throughput. So it seems to be required
> > for newer silicon as well.
> 
> At this point, I'd really appreciate it if someone from within TI can
> chime in here as I expect someone must suspect something here, thanks!

Here are some internal discussion highlights:


This is critical to provide deterministic access latency to MSMC from
ICSSG, it applies to all AM65 silicon revisions.

- is this errata or use-case specific settings?
Incorrect reset values, should've been static and setup as in the patch.

- what SoCs are affected (am64, J721e)?
AM65x only

- if this configuration applied will/might it affect on other use-cases (mostly
 multi-media related)?
No. This will only effect traffic taking advantage of the 2 ports to
MSMC and mapping to independent threads inside MSMC, one for SRAM and
one for DDR bound traffic.

In short, the patch is valid, we should be able to apply this
consistently on AM65x SoCs independent of the platform.


Hope this helps?

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D