[PATCH 08/17] ti: keystone: Clean up or migrate some NAND related options.

[Tom Rini]

The COFNIG_KEYSTONE_RBL_NAND option is always enabled for the driver on
keystone platforms, but not older davinci platforms.  Use def_bool for
the symbol. For CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE, it's only used within
the driver and derived from another symbol, so remove CONFIG from the
name.  Finally, CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE is a bit more fixed.
For now, use the value directly.  Long term, as part of DM'ifying NAND,
this should come from the device tree.

Signed-off-by: Tom Rini <trini at konsulko.com>
---
 drivers/mtd/nand/raw/Kconfig         |  4 ++++
 drivers/mtd/nand/raw/davinci_nand.c  | 12 ++++++------
 include/configs/ti_armv7_keystone2.h |  2 --
 3 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index f7b1334ddb47..bb8cffcabcef 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -105,6 +105,10 @@ config NAND_DAVINCI
 	  Enable this driver for NAND flash controllers available in TI Davinci
 	  and Keystone2 platforms
 
+config KEYSTONE_RBL_NAND
+	depends on ARCH_KEYSTONE
+	def_bool y
+
 config NAND_DENALI
 	bool
 	select SYS_NAND_SELF_INIT
diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
index 9ad3a57690e5..ef8e85a00212 100644
--- a/drivers/mtd/nand/raw/davinci_nand.c
+++ b/drivers/mtd/nand/raw/davinci_nand.c
@@ -347,9 +347,9 @@ static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
 };
 
 #ifdef CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE	CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
+#define KEYSTONE_NAND_MAX_RBL_PAGE	(0x100000 >> 11)
 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
-#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE	CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
+#define KEYSTONE_NAND_MAX_RBL_PAGE	(0x100000 >> 12)
 #endif
 
 /**
@@ -371,7 +371,7 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 	struct nand_ecclayout *saved_ecc_layout;
 
 	/* save current ECC layout and assign Keystone RBL ECC layout */
-	if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+	if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
 		saved_ecc_layout = chip->ecc.layout;
 		chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
 		mtd->oobavail = chip->ecc.layout->oobavail;
@@ -402,7 +402,7 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 
 err:
 	/* restore ECC layout */
-	if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+	if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
 		chip->ecc.layout = saved_ecc_layout;
 		mtd->oobavail = saved_ecc_layout->oobavail;
 	}
@@ -433,7 +433,7 @@ static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *
 	struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
 
 	/* save current ECC layout and assign Keystone RBL ECC layout */
-	if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+	if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
 		chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
 		mtd->oobavail = chip->ecc.layout->oobavail;
 	}
@@ -463,7 +463,7 @@ static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *
 	}
 
 	/* restore ECC layout */
-	if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+	if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
 		chip->ecc.layout = saved_ecc_layout;
 		mtd->oobavail = saved_ecc_layout->oobavail;
 	}
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index aa7b6ca9b809..512be7d328ea 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -119,8 +119,6 @@
 /* EEPROM definitions */
 
 /* NAND Configuration */
-#define CONFIG_KEYSTONE_RBL_NAND
-#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE	CONFIG_ENV_OFFSET
 #define CONFIG_SYS_NAND_MASK_CLE		0x4000
 #define CONFIG_SYS_NAND_MASK_ALE		0x2000
 #define CONFIG_SYS_NAND_CS			2
-- 
2.17.1