[PATCH v2 4/5] clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write

[Tom Rini]

On Tue, Sep 07, 2021 at 05:16:57PM -0500, Dave Gerlach wrote:

> There are three different divider values in the DIV_CTRL register
> controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate
> function writes the entire register when programming plld, even though
> plld only resides in the lower 6 bits.
> 
> Change the plld programming to read-modify-write to only affect the
> relevant bits for plld and to preserve the other two divider values
> present in the upper 16 bits, otherwise they will always get set to zero
> when programming plld.
> 
> Fixes: 0aa2930ca192 ("clk: add support for TI K3 SoC PLL")
> Signed-off-by: Dave Gerlach <d-gerlach at ti.com>

Applied to u-boot/master, thanks!

-- 
Tom
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