[PATCH v2 5/5] clk: ti: k3: Update driver to account for divider flags

[Tom Rini]

On Tue, Sep 07, 2021 at 05:16:58PM -0500, Dave Gerlach wrote:

> From: Suman Anna <s-anna at ti.com>
> 
> The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in
> turn serve as inputs to other HSDIV output clocks. These clocks use
> the actual value to compute the divider clock rate, and need to be
> registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk
> driver and data lacks the infrastructure to pass in divider flags.
> Update the driver and data to account for these divider flags.
> 
> Signed-off-by: Suman Anna <s-anna at ti.com>
> Signed-off-by: Dave Gerlach <d-gerlach at ti.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20210917/c1326899/attachment.sig>