[PATCH 3/3] phy: marvell: a3700: Return correct error code when power up fails

[Pali Rohár]

Subroutines in comphy_usb2_power_up() and comphy_sgmii_power_up() functions
may fail. In this case, do not continue execution of current function and
instead jump to the end. Return value in 'ret' variable is already set.

Signed-off-by: Pali Rohár <pali at kernel.org>
---
 drivers/phy/marvell/comphy_a3700.c | 26 ++++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 47a1ebd50238..b775db441890 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -594,24 +594,30 @@ static int comphy_usb2_power_up(u8 usb32)
 			      rb_usb2phy_pllcal_done,	/* value */
 			      rb_usb2phy_pllcal_done,	/* mask */
 			      POLL_32B_REG);		/* 32bit */
-	if (!ret)
+	if (!ret) {
 		printf("Failed to end USB2 PLL calibration\n");
+		goto out;
+	}
 
 	/* Assert impedance calibration done */
 	ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
 			      rb_usb2phy_impcal_done,	/* value */
 			      rb_usb2phy_impcal_done,	/* mask */
 			      POLL_32B_REG);		/* 32bit */
-	if (!ret)
+	if (!ret) {
 		printf("Failed to end USB2 impedance calibration\n");
+		goto out;
+	}
 
 	/* Assert squetch calibration done */
 	ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32),
 			      rb_usb2phy_sqcal_done,	/* value */
 			      rb_usb2phy_sqcal_done,	/* mask */
 			      POLL_32B_REG);		/* 32bit */
-	if (!ret)
+	if (!ret) {
 		printf("Failed to end USB2 unknown calibration\n");
+		goto out;
+	}
 
 	/* Assert PLL is ready */
 	ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32),
@@ -619,9 +625,12 @@ static int comphy_usb2_power_up(u8 usb32)
 			      rb_usb2phy_pll_ready,		/* mask */
 			      POLL_32B_REG);		/* 32bit */
 
-	if (!ret)
+	if (!ret) {
 		printf("Failed to lock USB2 PLL\n");
+		goto out;
+	}
 
+out:
 	debug_exit();
 
 	return ret;
@@ -873,8 +882,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
 			      rb_pll_ready_tx | rb_pll_ready_rx, /* value */
 			      rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
 			      POLL_32B_REG);			/* 32bit */
-	if (!ret)
+	if (!ret) {
 		printf("Failed to lock PLL for SGMII PHY %d\n", lane);
+		goto out;
+	}
 
 	/*
 	 * 21. Set COMPHY input port PIN_TX_IDLE=0
@@ -895,14 +906,17 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
 			      rb_rx_init_done,			/* value */
 			      rb_rx_init_done,			/* mask */
 			      POLL_32B_REG);			/* 32bit */
-	if (!ret)
+	if (!ret) {
 		printf("Failed to init RX of SGMII PHY %d\n", lane);
+		goto out;
+	}
 
 	/*
 	 * Restore saved selector.
 	 */
 	reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF);
 
+out:
 	debug_exit();
 
 	return ret;
-- 
2.20.1