[PATCH u-boot-marvell 6/6] arm: a37xx: pci: Update private structure documentation

[Pali Rohár]

On Saturday 25 September 2021 22:37:06 Marek Behún wrote:
> From: Marek Behún <marek.behun at nic.cz>
> 
> There were several changes for this structure but the documentation was
> not changed at the time. Fix this.
> 
> Signed-off-by: Marek Behún <marek.behun at nic.cz>
> ---
>  drivers/pci/pci-aardvark.c | 17 +++++++++--------
>  1 file changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
> index b4f350ca2c..76cb2098e8 100644
> --- a/drivers/pci/pci-aardvark.c
> +++ b/drivers/pci/pci-aardvark.c
> @@ -186,14 +186,15 @@
>  /**
>   * struct pcie_advk - Advk PCIe controller state
>   *
> - * @reg_base:    The base address of the register space.
> - * @first_busno: This driver supports multiple PCIe controllers.
> - *               first_busno stores the bus number of the PCIe root-port
> - *               number which may vary depending on the PCIe setup
> - *               (PEX switches etc).
> - * @sec_busno:   sec_busno stores the bus number for the device behind
> - *               the PCIe root-port
> - * @device:      The pointer to PCI uclass device.
> + * @base:        The base address of the register space.
> + * @first_busno: Bus number for the device behind the PCIe root-port.
> + *               This may vary depending on the PCIe setup.
> + * @sec_busno:   Bus number for the device behind the PCIe root-port.

Seems like there is copy+paste error here. First (primary) bus is
for PCIe root port and secondary bus for device behind the root port.
And both bus numbers are set by u-boot pnp code.

> + * @dev:         The pointer to PCI uclass device.
> + * @reset_gpio:  GPIO descriptor for PERST.
> + * @cfgcache:    Buffer for emulation of PCIe Root Port's PCI Bridge registers
> + *               that are not available on Aardvark.
> + * @cfgcrssve:   For CRSSVE emulation.
>   */
>  struct pcie_advk {
>  	void			*base;
> -- 
> 2.32.0
>