[PATCH 1/4] net: replace the "xfi" phy-mode with "10gbase-r"
Ramon Fried
rfried.dev at gmail.com
Tue Sep 28 15:28:59 CEST 2021
On Sat, Sep 18, 2021 at 3:34 PM Vladimir Oltean <vladimir.oltean at nxp.com> wrote:
>
> As part of the effort of making U-Boot work with the same device tree as
> Linux, there is an issue with the "xfi" phy-mode. To be precise, in
> Linux there was a discussion (for those who have time to read:
> https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/)
>
> which led to a patch:
> https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881
>
> TL;DR: "xfi" was standardized in Linux as "10gbase-r".
>
> This patch changes the relevant occurrences in U-Boot to use "10gbase-r"
> instead of "xfi" wherever applicable.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean at nxp.com>
> ---
> arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +-
> .../cpu/armv8/fsl-layerscape/doc/README.soc | 8 +++----
> .../cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 2 +-
> arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi | 4 ++--
> arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi | 4 ++--
> arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi | 16 +++++++-------
> arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 16 +++++++-------
> arch/arm/dts/fsl-sch-30841.dtsi | 2 +-
> arch/arm/dts/fsl-sch-30842.dtsi | 2 +-
> board/Marvell/octeon_ebb7304/board.c | 6 ++---
> board/freescale/ls1043aqds/README | 2 +-
> board/freescale/ls1043aqds/eth.c | 4 ++--
> board/freescale/ls1043ardb/README | 2 +-
> board/freescale/ls1043ardb/eth.c | 2 +-
> board/freescale/ls1046aqds/README | 2 +-
> board/freescale/ls1046aqds/eth.c | 4 ++--
> board/freescale/ls1046ardb/README | 4 ++--
> board/freescale/ls1046ardb/eth.c | 2 +-
> board/freescale/ls1088a/README | 4 ++--
> board/freescale/ls1088a/eth_ls1088ardb.c | 6 ++---
> board/freescale/ls2080aqds/README | 2 +-
> board/freescale/ls2080aqds/eth.c | 13 +++++------
> board/freescale/ls2080ardb/README | 2 +-
> board/freescale/t102xrdb/README | 2 +-
> board/freescale/t102xrdb/eth_t102xrdb.c | 2 +-
> board/freescale/t208xqds/README | 18 +++++++--------
> board/freescale/t208xqds/eth_t208xqds.c | 22 +++++++++----------
> board/freescale/t208xqds/t208xqds.c | 8 +++----
> board/freescale/t208xrdb/README | 4 ++--
> board/freescale/t4rdb/eth.c | 2 +-
> doc/device-tree-bindings/net/ethernet.txt | 12 +++++++++-
> drivers/net/fm/b4860.c | 2 +-
> drivers/net/fm/memac.c | 4 ++--
> drivers/net/fsl_enetc.c | 4 ++--
> drivers/net/mscc_eswitch/felix_switch.c | 2 +-
> drivers/net/phy/aquantia.c | 14 ++++++------
> include/phy.h | 2 +-
> include/phy_interface.h | 4 ++--
> 38 files changed, 111 insertions(+), 102 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index d0103fc8811e..1a359d060e82 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -1147,7 +1147,7 @@ int arch_early_init_r(void)
> #endif
> #ifdef CONFIG_SYS_FSL_HAS_RGMII
> /* some dpmacs in armv8a based freescale layerscape SOCs can be
> - * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
> + * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
> * EC*_PMUX(rgmii) bits in RCW.
> * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
> * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
> index f33d05d0539f..f2efd4cc1d70 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
> @@ -31,7 +31,7 @@ The LS1043A SoC includes the following function and features:
> - Hardware buffer management for buffer allocation and de-allocation (BMan)
> - Cryptography acceleration (SEC)
> - Ethernet interfaces by FMan
> - - Up to 1 x XFI supporting 10G interface
> + - Up to 1 x 10GBase-R supporting 10G interface
> - Up to 1 x QSGMII
> - Up to 4 x SGMII supporting 1000Mbps
> - Up to 2 x SGMII supporting 2500Mbps
> @@ -190,7 +190,7 @@ The LS1046A SoC includes the following function and features:
> - Two PLLs per four-lane SerDes
> - Support for 10G operation
> - Ethernet interfaces by FMan
> - - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
> + - Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10)
> - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
> - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
> - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
> @@ -295,7 +295,7 @@ The LX2160A SoC includes the following function and features:
> Single WRIOP tile supporting 130Gbps using 18 MACs
> Support for 10G-SXGMII (aka USXGMII).
> Support for SGMII (and 1000Base-KX)
> - Support for XFI (and 10GBase-KR)
> + Support for 10GBase-R (and 10GBase-KR)
> Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G).
> Support for XLAUI (and 40GBase-KR4) for 40G.
> Support for two RGMII parallel interfaces.
> @@ -400,7 +400,7 @@ The LX2162A SoC includes the following function and features:
> Ethernet interfaces
> Support for 10G-SXGMII (aka USXGMII).
> Support for SGMII (and 1000Base-KX)
> - Support for XFI (and 10GBase-KR)
> + Support for 10GBase-R (and 10GBase-KR)
> Support for CAUI2 (50G) and 25G-AUI(25G).
> Support for XLAUI (and 40GBase-KR4) for 40G.
> Support for two RGMII parallel interfaces.
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
> index 280afbbf98f7..26f8a4982692 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
> @@ -100,7 +100,7 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
> if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
> return 0;
> /*
> - * LS1044A/1048A support only one XFI port
> + * LS1044A/1048A support only one 10GBase-R port
> * Disable MAC1 for LS1044A/1048A
> */
> if (serdes == FSL_SRDS_1 && lane == 2) {
> diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
> index e0a6c04835bf..df39cca6961c 100644
> --- a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
> +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
> @@ -9,12 +9,12 @@
>
> &dpmac1 {
> status = "okay";
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac2 {
> status = "okay";
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac4 {
> diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
> index 65e95300ab56..99f74c2fc4d3 100644
> --- a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
> +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
> @@ -9,10 +9,10 @@
>
> &dpmac1 {
> status = "okay";
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac2 {
> status = "okay";
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
> diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
> index ccbb5de1eaef..72297f48ca65 100644
> --- a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
> +++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
> @@ -9,40 +9,40 @@
>
> &dpmac1 {
> status = "okay";
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac2 {
> status = "okay";
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac3 {
> status = "okay";
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac4 {
> status = "okay";
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac5 {
> status = "okay";
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac6 {
> status = "okay";
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac7 {
> status = "okay";
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac8 {
> status = "okay";
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
> diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
> index 179ed19bf2c1..9e68c147e607 100644
> --- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
> +++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
> @@ -24,49 +24,49 @@
> &dpmac1 {
> status = "okay";
> phy-handle = <&mdio1_phy1>;
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac2 {
> status = "okay";
> phy-handle = <&mdio1_phy2>;
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac3 {
> status = "okay";
> phy-handle = <&mdio1_phy3>;
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac4 {
> status = "okay";
> phy-handle = <&mdio1_phy4>;
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac5 {
> status = "okay";
> phy-handle = <&mdio2_phy1>;
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac6 {
> status = "okay";
> phy-handle = <&mdio2_phy2>;
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac7 {
> status = "okay";
> phy-handle = <&mdio2_phy3>;
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &dpmac8 {
> status = "okay";
> phy-handle = <&mdio2_phy4>;
> - phy-connection-type = "xfi";
> + phy-connection-type = "10gbase-r";
> };
>
> &emdio1 {
> diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi
> index ca437d178281..0a723c21b8f8 100644
> --- a/arch/arm/dts/fsl-sch-30841.dtsi
> +++ b/arch/arm/dts/fsl-sch-30841.dtsi
> @@ -9,7 +9,7 @@
> * SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
> * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
> * together on a single lane or mapped 1:1 to serdes lanes.
> - * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
> + * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, 10GBase-R.
> * PHY addresses are 0x00 - 0x03.
> * On the card the first port is the bottom port (closest to PEX connector).
> */
> diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi
> index fa0f2cdb1096..b64aeb3fcce6 100644
> --- a/arch/arm/dts/fsl-sch-30842.dtsi
> +++ b/arch/arm/dts/fsl-sch-30842.dtsi
> @@ -8,7 +8,7 @@
> /*
> * SCH-30842 is a single port add-on card used with various FSL QDS boards.
> * It integrates a AQR112 PHY, which supports several protocols - SGMII,
> - * SGMII-2500, USXGMII, XFI.
> + * SGMII-2500, USXGMII, 10GBase-R.
> * PHY address is 0x02.
> */
> phy at 02 {
> diff --git a/board/Marvell/octeon_ebb7304/board.c b/board/Marvell/octeon_ebb7304/board.c
> index 9aac5f0b09f5..e8e2d547c1ee 100644
> --- a/board/Marvell/octeon_ebb7304/board.c
> +++ b/board/Marvell/octeon_ebb7304/board.c
> @@ -339,7 +339,7 @@ void __fixup_fdt(void)
> case CVMX_QLM_MODE_XFI:
> case CVMX_QLM_MODE_RGMII_XFI:
> case CVMX_QLM_MODE_RGMII_XFI_1X1:
> - type_str = "xfi";
> + type_str = "10gbase-r";
> break;
> case CVMX_QLM_MODE_10G_KR:
> case CVMX_QLM_MODE_RGMII_10G_KR:
> @@ -393,7 +393,7 @@ void __fixup_fdt(void)
> if (pmd_control.s.train_en)
> type_str = "10G_KR";
> else
> - type_str = "xfi";
> + type_str = "10gbase-r";
> break;
> case 4:
> if (pmd_control.s.train_en)
> @@ -618,7 +618,7 @@ static void board_configure_qlms(void)
> speed[qlm] = 103125;
> }
> printf("QLM %d: XLAUI\n", qlm);
> - } else if (!strncmp(mode_str, "xfi", 3)) {
> + } else if (!strncmp(mode_str, "10gbase-r", 3)) {
> bool rgmii = false;
>
> speed[qlm] = 103125;
> diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README
> index 913537d45190..f5aa51da87eb 100644
> --- a/board/freescale/ls1043aqds/README
> +++ b/board/freescale/ls1043aqds/README
> @@ -18,7 +18,7 @@ SoC overview.
> - SGMII, SGMII 2.5
> - QSGMII
> - SATA 3.0
> - - XFI
> + - 10GBase-R
> - DDR Controller
> - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
> -IFC/Local Bus
> diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
> index c3efe8a0be64..81e18f6e82b5 100644
> --- a/board/freescale/ls1043aqds/eth.c
> +++ b/board/freescale/ls1043aqds/eth.c
> @@ -242,13 +242,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
> "qsgmii");
> } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
> port == FM1_10GEC1) {
> - /* XFI interface */
> + /* 10GBase-R interface */
> f_link.phy_id = cpu_to_fdt32(port);
> f_link.duplex = cpu_to_fdt32(1);
> f_link.link_speed = cpu_to_fdt32(10000);
> f_link.pause = 0;
> f_link.asym_pause = 0;
> - /* no PHY for XFI */
> + /* no PHY for 10GBase-R */
> fdt_delprop(fdt, offset, "phy-handle");
> fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
> fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
> diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README
> index 709ddbbef31a..66ee578e99d9 100644
> --- a/board/freescale/ls1043ardb/README
> +++ b/board/freescale/ls1043ardb/README
> @@ -17,7 +17,7 @@ SoC overview.
> - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
> standard PCIe card
> - QSGMII with x4 RJ45 connector
> - - XFI with x1 RJ45 connector
> + - 10GBase-R with x1 RJ45 connector
> - DDR Controller
> - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
> -IFC/Local Bus
> diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c
> index 1f01c1551656..fa59116ce57b 100644
> --- a/board/freescale/ls1043ardb/eth.c
> +++ b/board/freescale/ls1043ardb/eth.c
> @@ -65,7 +65,7 @@ int board_eth_init(struct bd_info *bis)
> for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
> fm_info_set_mdio(i, dev);
>
> - /* XFI on lane A, MAC 9 */
> + /* 10GBase-R on lane A, MAC 9 */
> fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
> dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
> fm_info_set_mdio(FM1_10GEC1, dev);
> diff --git a/board/freescale/ls1046aqds/README b/board/freescale/ls1046aqds/README
> index b8fa32652b0d..d6469019bd26 100644
> --- a/board/freescale/ls1046aqds/README
> +++ b/board/freescale/ls1046aqds/README
> @@ -18,7 +18,7 @@ SoC overview.
> - SGMII, SGMII 2.5
> - QSGMII
> - SATA 3.0
> - - XFI
> + - 10GBase-R
> - DDR Controller
> - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
> -IFC/Local Bus
> diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c
> index 33db552adb8a..23528324662e 100644
> --- a/board/freescale/ls1046aqds/eth.c
> +++ b/board/freescale/ls1046aqds/eth.c
> @@ -217,13 +217,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
> /* Backplane KR mode: skip fixups */
> printf("Interface %d in backplane KR mode\n", port);
> } else {
> - /* XFI interface */
> + /* 10GBase-R interface */
> f_link.phy_id = cpu_to_fdt32(port);
> f_link.duplex = cpu_to_fdt32(1);
> f_link.link_speed = cpu_to_fdt32(10000);
> f_link.pause = 0;
> f_link.asym_pause = 0;
> - /* no PHY for XFI */
> + /* no PHY for 10GBase-R */
> fdt_delprop(fdt, offset, "phy-handle");
> fdt_setprop(fdt, offset, "fixed-link", &f_link,
> sizeof(f_link));
> diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README
> index a38c9d48300e..1660f7c7cf90 100644
> --- a/board/freescale/ls1046ardb/README
> +++ b/board/freescale/ls1046ardb/README
> @@ -14,8 +14,8 @@ SoC overview.
> LS1046ARDB board Overview
> -----------------------
> - SERDES1 Connections, 4 lanes supporting:
> - - Lane0: XFI with x1 RJ45 connector
> - - Lane1: XFI Cage
> + - Lane0: 10GBase-R with x1 RJ45 connector
> + - Lane1: 10GBase-R Cage
> - Lane2: SGMII.5
> - Lane3: SGMII.6
> - SERDES2 Connections, 4 lanes supporting:
> diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c
> index 4905302d8cd9..a3e147a48b98 100644
> --- a/board/freescale/ls1046ardb/eth.c
> +++ b/board/freescale/ls1046ardb/eth.c
> @@ -67,7 +67,7 @@ int board_eth_init(struct bd_info *bis)
> for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
> fm_info_set_mdio(i, dev);
>
> - /* XFI on lane A, MAC 9 */
> + /* 10GBase-R on lane A, MAC 9 */
> dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
> fm_info_set_mdio(FM1_10GEC1, dev);
>
> diff --git a/board/freescale/ls1088a/README b/board/freescale/ls1088a/README
> index aa0fb6ac676f..5315909defc8 100644
> --- a/board/freescale/ls1088a/README
> +++ b/board/freescale/ls1088a/README
> @@ -42,7 +42,7 @@ Alternately you can use this command to switch from QSPI to SD
> - SERDES Connections, 16 lanes supporting:
> - PCI Express - 3.0
> - SATA 3.0
> - - XFI
> + - 10GBase-R
> - QSGMII
> - DDR Controller
> - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
> @@ -106,7 +106,7 @@ SW12 1111 1111
> - SERDES Connections, 16 lanes supporting:
> - PCI Express - 3.0
> - SATA 3.0
> - - 2 XFI
> + - 2 10GBase-R
> - QSGMII, SGMII with help for Riser card
> - 2 RGMII
> - 5 slot for Riser card or PCIe NIC
> diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c
> index a8e9ef15dc48..1ba5e94d0a0a 100644
> --- a/board/freescale/ls1088a/eth_ls1088ardb.c
> +++ b/board/freescale/ls1088a/eth_ls1088ardb.c
> @@ -52,9 +52,9 @@ int board_eth_init(struct bd_info *bis)
> switch (srds_s1) {
> case 0x1D:
> /*
> - * XFI does not need a PHY to work, but to avoid U-boot use
> - * default PHY address which is zero to a MAC when it found
> - * a MAC has no PHY address, we give a PHY address to XFI
> + * 10GBase-R does not need a PHY to work, but to avoid U-boot
> + * use default PHY address which is zero to a MAC when it found
> + * a MAC has no PHY address, we give a PHY address to 10GBase-R
> * MAC error.
> */
> wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a);
> diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
> index 8e31e9e41e3e..04c1941b056e 100644
> --- a/board/freescale/ls2080aqds/README
> +++ b/board/freescale/ls2080aqds/README
> @@ -19,7 +19,7 @@ LS2088A SoC overview.
> - QSGMII
> - SATA 3.0
> - XAUI
> - - XFI
> + - 10GBase-R
> - DDR Controller
> - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
> chip-selects and two DIMM connectors. Support is up to 2133MT/s.
> diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
> index 914cd0a9ab59..7db37898220a 100644
> --- a/board/freescale/ls2080aqds/eth.c
> +++ b/board/freescale/ls2080aqds/eth.c
> @@ -874,13 +874,12 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
> case 0x4B:
> case 0x4C:
> /*
> - * XFI does not need a PHY to work, but to avoid U-Boot use
> - * default PHY address which is zero to a MAC when it found
> - * a MAC has no PHY address, we give a PHY address to XFI
> - * MAC, and should not use a real XAUI PHY address, since
> - * MDIO can access it successfully, and then MDIO thinks
> - * the XAUI card is used for the XFI MAC, which will cause
> - * error.
> + * 10GBase-R does not need a PHY to work, but to avoid U-Boot
> + * use default PHY address which is zero to a MAC when it found
> + * a MAC has no PHY address, we give a PHY address to 10GBase-R
> + * MAC, and should not use a real XAUI PHY address, since MDIO
> + * can access it successfully, and then MDIO thinks the XAUI
> + * card is used for the 10GBase-R MAC, which will cause error.
> */
> wriop_set_phy_address(i, 0, i + 4);
> ls2080a_qds_enable_SFP_TX(SFP_TX);
> diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
> index 205c45cb2af3..75a633ccb4ef 100644
> --- a/board/freescale/ls2080ardb/README
> +++ b/board/freescale/ls2080ardb/README
> @@ -18,7 +18,7 @@ LS2081A, LS2088A SoC overview.
> - SERDES Connections, 16 lanes supporting:
> - PCI Express - 3.0
> - SATA 3.0
> - - XFI
> + - 10GBase-R
> - DDR Controller
> - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
> chip-selects and two DIMM connectors. Support is up to 2133MT/s.
> diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README
> index dde3f8ca37f6..84deb9562a14 100644
> --- a/board/freescale/t102xrdb/README
> +++ b/board/freescale/t102xrdb/README
> @@ -39,7 +39,7 @@ The T1024 SoC includes the following function and features:
> - One QSGMII interface
> - Four SGMII interface supporting 1000 Mbps
> - Three SGMII interfaces supporting up to 2500 Mbps
> - - 10GbE XFI or 10Base-KR interface
> + - 10GBase-R or 10Base-KR interface
> - Additional peripheral interfaces
> - Two USB 2.0 controllers with integrated PHY
> - SD/eSDHC/eMMC
> diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
> index 56e6109288f7..b28c5457d67e 100644
> --- a/board/freescale/t102xrdb/eth_t102xrdb.c
> +++ b/board/freescale/t102xrdb/eth_t102xrdb.c
> @@ -64,7 +64,7 @@ int board_eth_init(struct bd_info *bis)
> /* set the on-board RGMII2 PHY */
> fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
>
> - /* set 10G XFI with Aquantia AQR105 PHY */
> + /* set 10GBase-R with Aquantia AQR105 PHY */
> fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
> break;
> #endif
> diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README
> index d690857f2e28..b52d9610e981 100755
> --- a/board/freescale/t208xqds/README
> +++ b/board/freescale/t208xqds/README
> @@ -55,14 +55,14 @@ Memory:
> - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
> Ethernet interfaces:
> - Two 1Gbps RGMII on-board ports
> - - Four 10Gbps XFI on-board cages
> + - Four 10GBase-R on-board cages
> - 1Gbps/2.5Gbps SGMII Riser card
> - 10Gbps XAUI Riser card
> Accelerator:
> - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
> SerDes:
> - 16 lanes up to 10.3125GHz
> - - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
> + - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, 10GBase-R and XAUI
> IFC:
> - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
> eSPI:
> @@ -85,14 +85,14 @@ System Logic:
> - QIXIS-II FPGA system controll
> Debug Features:
> - Support Legacy, COP/JTAG, Aurora, Event and EVT
> -XFI:
> - - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
> +10GBase-R:
> + - 10GBase-R is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
> a on-board SFP+ cages, which to house optical module (fiber cable) or
> direct attach cable(copper), the copper cable is used to emulate
> 10GBASE-KR scenario.
> - So, for XFI usage, there are two scenarios, one will use fiber cable,
> + So, for 10GBase-R usage, there are two scenarios, one will use fiber cable,
> another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
> - introduced to indicate a XFI port will use copper cable, and U-Boot
> + introduced to indicate a 10GBase-R port will use copper cable, and U-Boot
> will fixup the dtb accordingly.
> It's used as: fsl_10gkr_copper:<10g_mac_name>
> The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
> @@ -100,10 +100,10 @@ XFI:
> "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
> will be used by default.
> for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
> - hwconfig, then both four XFI ports will use copper cable.
> + hwconfig, then both four 10GBase-R ports will use copper cable.
> set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
> - XFI ports will use copper cable, the other two XFI ports will use fiber
> - cable.
> + 10GBase-R ports will use copper cable, the other two 10GBase-R ports will use
> + fiber cable.
> 1000BASE-KX(1G-KX):
> - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
> runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
> diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
> index 705387af3c31..2d7fc8bdda2e 100644
> --- a/board/freescale/t208xqds/eth_t208xqds.c
> +++ b/board/freescale/t208xqds/eth_t208xqds.c
> @@ -310,16 +310,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
>
> } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
> switch (srds_s1) {
> - case 0x66: /* XFI interface */
> + case 0x66: /* 10GBase-R interface */
> case 0x6b:
> case 0x6c:
> case 0x6d:
> case 0x71:
> /*
> - * if the 10G is XFI, check hwconfig to see what is the
> - * media type, there are two types, fiber or copper,
> - * fix the dtb accordingly.
> - */
> + * Check hwconfig to see what is the media type, there
> + * are two types, fiber or copper, fix the dtb
> + * accordingly.
> + */
> switch (port) {
> case FM1_10GEC1:
> if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
> @@ -378,7 +378,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
> printf("Interface %d in backplane KR mode\n",
> port);
> } else {
> - /* fixed-link for XFI fiber cable */
> + /* fixed-link for 10GBase-R fiber cable */
> f_link.phy_id = port;
> f_link.duplex = 1;
> f_link.link_speed = 10000;
> @@ -538,12 +538,12 @@ int board_eth_init(struct bd_info *bis)
> case 0x66:
> case 0x67:
> /*
> - * XFI does not need a PHY to work, but to avoid U-Boot use
> - * default PHY address which is zero to a MAC when it found
> - * a MAC has no PHY address, we give a PHY address to XFI
> + * 10GBase-R does not need a PHY to work, but to avoid U-Boot
> + * use default PHY address which is zero to a MAC when it found
> + * a MAC has no PHY address, we give a PHY address to 10GBase-R
> * MAC, and should not use a real XAUI PHY address, since
> * MDIO can access it successfully, and then MDIO thinks
> - * the XAUI card is used for the XFI MAC, which will cause
> + * the XAUI card is used for the 10GBase-R MAC, which will cause
> * error.
> */
> fm_info_set_phy_address(FM1_10GEC1, 4);
> @@ -701,7 +701,7 @@ int board_eth_init(struct bd_info *bis)
> (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
> (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
> (srds_s1 == 0x71)) {
> - /* As XFI is in cage intead of a slot, so
> + /* As 10GBase-R is in cage intead of a slot, so
> * ensure doesn't disable the corresponding port
> */
> break;
> diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
> index 715de106d69b..e54672a80ba4 100644
> --- a/board/freescale/t208xqds/t208xqds.c
> +++ b/board/freescale/t208xqds/t208xqds.c
> @@ -136,14 +136,14 @@ int brd_mux_lane_to_slot(void)
> break;
> case 0x66:
> case 0x67:
> - /* SD1(A:D) => XFI cage
> + /* SD1(A:D) => 10GBase-R cage
> * SD1(E:H) => SLOT1 PCIe4
> */
> QIXIS_WRITE(brdcfg[12], 0xfe);
> break;
> case 0x6a:
> case 0x6b:
> - /* SD1(A:D) => XFI cage
> + /* SD1(A:D) => 10GBase-R cage
> * SD1(E) => SLOT1 PCIe4
> * SD1(F:H) => SLOT2 SGMII
> */
> @@ -151,14 +151,14 @@ int brd_mux_lane_to_slot(void)
> break;
> case 0x6c:
> case 0x6d:
> - /* SD1(A:B) => XFI cage
> + /* SD1(A:B) => 10GBase-R cage
> * SD1(C:D) => SLOT3 SGMII
> * SD1(E:H) => SLOT1 PCIe4
> */
> QIXIS_WRITE(brdcfg[12], 0xda);
> break;
> case 0x6e:
> - /* SD1(A:B) => SFP Module, XFI
> + /* SD1(A:B) => SFP Module, 10GBase-R
> * SD1(C:D) => SLOT3 SGMII
> * SD1(E:F) => SLOT1 PCIe4 x2
> * SD1(G:H) => SLOT2 SGMII
> diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README
> index ec47c96f2b1a..c4bfd3b466f4 100644
> --- a/board/freescale/t208xrdb/README
> +++ b/board/freescale/t208xrdb/README
> @@ -54,7 +54,7 @@ Differences between T2080 and T2081
> T2080PCIe-RDB board Overview
> ----------------------------
> - SERDES Configuration
> - - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
> + - SerDes-1 Lane A-B: to two 10GBase-R fiber (MAC9 & MAC10)
> - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
> - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
> - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
> @@ -62,7 +62,7 @@ T2080PCIe-RDB board Overview
> - SerDes-2 Lane G-H: to SATA1 & SATA2
> - Ethernet
> - Two on-board 10M/100M/1G RGMII ethernet ports
> - - Two on-board 10Gbps XFI fiber ports
> + - Two on-board 10GBase-R fiber ports
> - Two on-board 10Gbps Base-T copper ports
> - DDR Memory
> - Supports 72bit 4GB DDR3-LP SODIMM
> diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
> index c815a3a4fa52..34ffaa6aeb54 100644
> --- a/board/freescale/t4rdb/eth.c
> +++ b/board/freescale/t4rdb/eth.c
> @@ -106,7 +106,7 @@ int board_eth_init(struct bd_info *bis)
>
> #if (CONFIG_SYS_NUM_FMAN == 2)
> if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
> - /* SGMII && XFI */
> + /* SGMII && 10GBase-R */
> fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
> fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
> fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
> diff --git a/doc/device-tree-bindings/net/ethernet.txt b/doc/device-tree-bindings/net/ethernet.txt
> index cfc376bc977a..648a1aee694d 100644
> --- a/doc/device-tree-bindings/net/ethernet.txt
> +++ b/doc/device-tree-bindings/net/ethernet.txt
> @@ -41,7 +41,17 @@ Documentation/devicetree/bindings/phy/phy-bindings.txt.
> * "2500base-x",
> * "rxaui"
> * "xaui"
> - * "10gbase-kr" (10GBASE-KR, XFI, SFI)
> + * "10gbase-r" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol
> + used with various different mediums. Please refer to the IEEE standard for
> + a definition of this. Note: 10GBASE-R is just one protocol that can be used
> + with XFI and SFI. XFI and SFI permit multiple protocols over a single
> + SERDES lane, and also defines the electrical characteristics of the signals
> + with a host compliance board plugged into the host XFP/SFP connector.
> + Therefore, XFI and SFI are not PHY interface types in their own right.)
> + * "10gbase-kr" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R with
> + Clause 73 autonegotiation. Please refer to the IEEE standard for further
> + information. Note: due to legacy usage, some 10GBASE-R usage incorrectly
> + makes use of this definition).
> - phy-connection-type: the same as "phy-mode" property but described in the
> Devicetree Specification;
> - phy-handle: phandle, specifies a reference to a node representing a PHY
> diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
> index 5be0ad2ab3db..6e3d008199a5 100644
> --- a/drivers/net/fm/b4860.c
> +++ b/drivers/net/fm/b4860.c
> @@ -100,7 +100,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
> env_get_f("hwconfig", buffer, sizeof(buffer));
> buf = buffer;
>
> - /* check if XFI interface enable in hwconfig for 10g */
> + /* check if 10GBase-R interface enable in hwconfig for 10g */
> if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
> "sfp_amc", "sfp", buf)) {
> if ((port == FM1_10GEC1 ||
> diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
> index 36f50d27826e..e1f812b688b1 100644
> --- a/drivers/net/fm/memac.c
> +++ b/drivers/net/fm/memac.c
> @@ -98,7 +98,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
> if_mode &= ~IF_MODE_MASK;
> if_mode |= (IF_MODE_GMII);
> break;
> - case PHY_INTERFACE_MODE_XFI:
> + case PHY_INTERFACE_MODE_10GBASER:
> case PHY_INTERFACE_MODE_XGMII:
> if_mode &= ~IF_MODE_MASK;
> if_mode |= IF_MODE_XGMII;
> @@ -107,7 +107,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
> break;
> }
> /* Enable automatic speed selection for Non-XGMII */
> - if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_XFI)
> + if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_10GBASER)
> if_mode |= IF_MODE_EN_AUTO;
>
> if (type == PHY_INTERFACE_MODE_RGMII ||
> diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
> index 566cdc7e546a..12d9942b65d4 100644
> --- a/drivers/net/fsl_enetc.c
> +++ b/drivers/net/fsl_enetc.c
> @@ -228,7 +228,7 @@ static void enetc_setup_mac_iface(struct udevice *dev,
> break;
> case PHY_INTERFACE_MODE_XGMII:
> case PHY_INTERFACE_MODE_USXGMII:
> - case PHY_INTERFACE_MODE_XFI:
> + case PHY_INTERFACE_MODE_10GBASER:
> /* set ifmode to (US)XGMII */
> if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
> if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
> @@ -296,7 +296,7 @@ static void enetc_start_pcs(struct udevice *dev)
> break;
> case PHY_INTERFACE_MODE_XGMII:
> case PHY_INTERFACE_MODE_USXGMII:
> - case PHY_INTERFACE_MODE_XFI:
> + case PHY_INTERFACE_MODE_10GBASER:
> enetc_init_sxgmii(dev);
> break;
> };
> diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c
> index 6aa79784460d..67b2879e8585 100644
> --- a/drivers/net/mscc_eswitch/felix_switch.c
> +++ b/drivers/net/mscc_eswitch/felix_switch.c
> @@ -223,7 +223,7 @@ static void felix_start_pcs(struct udevice *dev, int port,
> felix_init_sgmii(imdio, port, autoneg);
> break;
> case PHY_INTERFACE_MODE_XGMII:
> - case PHY_INTERFACE_MODE_XFI:
> + case PHY_INTERFACE_MODE_10GBASER:
> case PHY_INTERFACE_MODE_USXGMII:
> if (felix_init_sxgmii(imdio, port))
> dev_err(dev, "PCS reset timeout on port %d\n", port);
> diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
> index d3d35a75d065..66d1d9856825 100644
> --- a/drivers/net/phy/aquantia.c
> +++ b/drivers/net/phy/aquantia.c
> @@ -310,7 +310,7 @@ struct {
> AQUANTIA_VND1_GSTART_RATE_1G},
> [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
> AQUANTIA_VND1_GSTART_RATE_2_5G},
> - [PHY_INTERFACE_MODE_XFI] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
> + [PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
> AQUANTIA_VND1_GSTART_RATE_10G},
> [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G,
> AQUANTIA_VND1_GSTART_RATE_10G},
> @@ -443,18 +443,18 @@ int aquantia_config(struct phy_device *phydev)
> return ret;
> }
> /*
> - * for backward compatibility convert XGMII into either XFI or USX based
> - * on FW config
> + * for backward compatibility convert XGMII into either 10GBase-R or
> + * USXGMII based on FW config
> */
> if (interface == PHY_INTERFACE_MODE_XGMII) {
> - debug("use XFI or USXGMII SI protos, XGMII is not valid\n");
> + debug("use 10GBase-R or USXGMII SI protos, XGMII is not valid\n");
>
> reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
> AQUANTIA_SYSTEM_INTERFACE_SR);
> if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
> interface = PHY_INTERFACE_MODE_USXGMII;
> else
> - interface = PHY_INTERFACE_MODE_XFI;
> + interface = PHY_INTERFACE_MODE_10GBASER;
> }
>
> /*
> @@ -494,7 +494,7 @@ int aquantia_config(struct phy_device *phydev)
> case PHY_INTERFACE_MODE_USXGMII:
> usx_an = 1;
> /* FALLTHROUGH */
> - case PHY_INTERFACE_MODE_XFI:
> + case PHY_INTERFACE_MODE_10GBASER:
> /* 10GBASE-T mode */
> phydev->advertising = SUPPORTED_10000baseT_Full;
> phydev->supported = phydev->advertising;
> @@ -515,7 +515,7 @@ int aquantia_config(struct phy_device *phydev)
> phydev->dev->name);
> } else {
> reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
> - debug("%s: system interface XFI\n",
> + debug("%s: system interface 10GBase-R\n",
> phydev->dev->name);
> }
>
> diff --git a/include/phy.h b/include/phy.h
> index 6b928636b6d7..b9d8dc3a61ed 100644
> --- a/include/phy.h
> +++ b/include/phy.h
> @@ -368,7 +368,7 @@ static inline int is_10g_interface(phy_interface_t interface)
> {
> return interface == PHY_INTERFACE_MODE_XGMII ||
> interface == PHY_INTERFACE_MODE_USXGMII ||
> - interface == PHY_INTERFACE_MODE_XFI;
> + interface == PHY_INTERFACE_MODE_10GBASER;
> }
>
> #endif
> diff --git a/include/phy_interface.h b/include/phy_interface.h
> index ebb18ecd40c0..f075abe9c9c0 100644
> --- a/include/phy_interface.h
> +++ b/include/phy_interface.h
> @@ -37,7 +37,7 @@ typedef enum {
> PHY_INTERFACE_MODE_CAUI2,
> PHY_INTERFACE_MODE_CAUI4,
> PHY_INTERFACE_MODE_NCSI,
> - PHY_INTERFACE_MODE_XFI,
> + PHY_INTERFACE_MODE_10GBASER,
> PHY_INTERFACE_MODE_USXGMII,
> PHY_INTERFACE_MODE_NONE, /* Must be last */
>
> @@ -69,7 +69,7 @@ static const char * const phy_interface_strings[] = {
> [PHY_INTERFACE_MODE_CAUI2] = "caui2",
> [PHY_INTERFACE_MODE_CAUI4] = "caui4",
> [PHY_INTERFACE_MODE_NCSI] = "NC-SI",
> - [PHY_INTERFACE_MODE_XFI] = "xfi",
> + [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r",
> [PHY_INTERFACE_MODE_USXGMII] = "usxgmii",
> [PHY_INTERFACE_MODE_NONE] = "",
> };
> --
> 2.25.1
>
Reviewed-by: Ramon Fried <rfried.dev at gmail.com>
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