[PATCH v2] mtd: spi-nor-core: Add fixups for s25fs512s

[Pratyush Yadav]

On 30/09/21 02:32PM, tkuw584924 at gmail.com wrote:
> From: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>
> 
> The current S25FS512S support has following issues that need to be fixed.
> 
>   - Non-uniform sectors by factory default. The setting needs to be
>     checked and assign erase hook as needed.
>   - Page size is wrongly advertised in SFDP.
>   - READ_1_1_2 (3Bh/3Ch), READ_1_1_4 (6Bh/6Ch), and PP_1_1_4 (32h/34h)
>     are not supported.
>   - Bank Address Register (BAR) is not supported.
> 
> In addtion, volatile version of Quad Enable is used for safety.
> 
> For future use, the fixups is assigned for S25FS-S family.
> 
> The datasheet can be found in the following link.
> https://www.cypress.com/file/216376/download
> 
> Tested on Xilinx Zynq-7000 FPGA board.
> 
> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>

Acked-by: Pratyush Yadav <p.yadav at ti.com>

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.