[PATCH v2 16/23] i2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2C

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:13 -0500
Samuel Holland <samuel at sholland.org> wrote:

> When the DM_I2C driver is loaded, the pin setup is done automatically
> from the device tree by the pinctrl driver.
> 
> Signed-off-by: Samuel Holland <samuel at sholland.org>

Reviewed-by: Andre Przywara <andre.przywara at arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  drivers/i2c/sun6i_p2wi.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c
> index c9e1b3fcd5..73b808b09b 100644
> --- a/drivers/i2c/sun6i_p2wi.c
> +++ b/drivers/i2c/sun6i_p2wi.c
> @@ -102,12 +102,6 @@ static int sun6i_p2wi_change_to_p2wi_mode(struct sunxi_p2wi_reg *base,
>  
>  static void sun6i_p2wi_init(struct sunxi_p2wi_reg *base)
>  {
> -	/* Enable p2wi and PIO clk, and de-assert their resets */
> -	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
> -
> -	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
> -	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
> -
>  	/* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
>  	writel(P2WI_CTRL_RESET, &base->ctrl);
>  	sdelay(0x100);
> @@ -142,6 +136,12 @@ void p2wi_init(void)
>  {
>  	struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
>  
> +	/* Enable p2wi and PIO clk, and de-assert their resets */
> +	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
> +
> +	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
> +	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
> +
>  	sun6i_p2wi_init(base);
>  }
>  #endif