[PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP
Tim Harvey
tharvey at gateworks.com
Mon Apr 4 22:15:26 CEST 2022
On Mon, Apr 4, 2022 at 12:11 PM Marek Vasut <marex at denx.de> wrote:
>
> On 4/4/22 20:51, Tim Harvey wrote:
> > On Fri, Apr 1, 2022 at 5:48 PM Marek Vasut <marex at denx.de> wrote:
> >>
> >> On 4/1/22 23:28, Tim Harvey wrote:
> >>> On Fri, Apr 1, 2022 at 7:32 AM Marek Vasut <marex at denx.de> wrote:
> >>>>
> >>>> The i.MX8MP glue needs to be configured based on a couple of DT
> >>>> properties, implement .glue_configure callback to parse those DT
> >>>> properties and configure the glue accordingly.
> >>>>
> >>>> Signed-off-by: Marek Vasut <marex at denx.de>
> >>>> Cc: Angus Ainslie <angus at akkea.ca>
> >>>> Cc: Bin Meng <bmeng.cn at gmail.com>
> >>>> Cc: Fabio Estevam <festevam at gmail.com>
> >>>> Cc: Kunihiko Hayashi <hayashi.kunihiko at socionext.com>
> >>>> Cc: Michal Simek <michal.simek at xilinx.com>
> >>>> Cc: Peng Fan <peng.fan at nxp.com>
> >>>> Cc: Stefano Babic <sbabic at denx.de>
> >>>> ---
> >>>> drivers/usb/dwc3/dwc3-generic.c | 52 +++++++++++++++++++++++++++++++++
> >>>> 1 file changed, 52 insertions(+)
> >>>>
> >>>> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
> >>>> index 7e3814207e4..6cf844cb483 100644
> >>>> --- a/drivers/usb/dwc3/dwc3-generic.c
> >>>> +++ b/drivers/usb/dwc3/dwc3-generic.c
> >>>> @@ -223,6 +223,57 @@ struct dwc3_glue_ops {
> >>>> enum usb_dr_mode mode);
> >>>> };
> >>>>
> >>>> +void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
> >>>> + enum usb_dr_mode mode)
> >>>> +{
> >>>> +/* USB glue registers */
> >>>> +#define USB_CTRL0 0x00
> >>>> +#define USB_CTRL1 0x04
> >>>> +
> >>>> +#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
> >>>> +#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
> >>>> +#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
> >>>> +
> >>>> +#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
> >>>> +#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
> >>>> + fdt_addr_t regs = dev_read_addr_index(dev, 1);
> >>>> + void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
> >>>> + u32 value;
> >>>> +
> >>>> + value = readl(base + USB_CTRL0);
> >>>> +
> >>>> + if (dev_read_bool(dev, "fsl,permanently-attached"))
> >>>> + value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> >>>> + else
> >>>> + value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> >>>> +
> >>>> + if (dev_read_bool(dev, "fsl,disable-port-power-control"))
> >>>> + value &= ~(USB_CTRL0_PORTPWR_EN);
> >>>> + else
> >>>> + value |= USB_CTRL0_PORTPWR_EN;
> >>>> +
> >>>> + writel(value, base + USB_CTRL0);
> >>>> +
> >>>> + value = readl(base + USB_CTRL1);
> >>>> + if (dev_read_bool(dev, "fsl,over-current-active-low"))
> >>>> + value |= USB_CTRL1_OC_POLARITY;
> >>>> + else
> >>>> + value &= ~USB_CTRL1_OC_POLARITY;
> >>>> +
> >>>> + if (dev_read_bool(dev, "fsl,power-active-low"))
> >>>> + value |= USB_CTRL1_PWR_POLARITY;
> >>>> + else
> >>>> + value &= ~USB_CTRL1_PWR_POLARITY;
> >>>> +
> >>>> + writel(value, base + USB_CTRL1);
> >>>> +
> >>>> + unmap_physmem(base, MAP_NOCACHE);
> >>>> +}
> >>>> +
> >>>> +struct dwc3_glue_ops imx8mp_ops = {
> >>>> + .glue_configure = dwc3_imx8mp_glue_configure,
> >>>> +};
> >>>> +
> >>>> void dwc3_ti_glue_configure(struct udevice *dev, int index,
> >>>> enum usb_dr_mode mode)
> >>>> {
> >>>> @@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
> >>>> { .compatible = "rockchip,rk3328-dwc3" },
> >>>> { .compatible = "rockchip,rk3399-dwc3" },
> >>>> { .compatible = "qcom,dwc3" },
> >>>> + { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
> >>>> { .compatible = "fsl,imx8mq-dwc3" },
> >>>> { .compatible = "intel,tangier-dwc3" },
> >>>> { }
> >>>> --
> >>>> 2.35.1
> >>>>
> >>>
> >>> Marek,
> >>>
> >>> Looks like your working on IMX8MP USB support - thanks for that!
> >>>
> >>> I'm working on bring-up of an IMX8MP board and can test your
> >>> power-domain and USB patches but I'm having trouble getting some of
> >>> your patches to apply - do you have a repo I can pull from?
> >>
> >> https://source.denx.de/u-boot/custodians/u-boot-usb/-/commits/imx-8mp
> >
> > Marek,
> >
> > Thanks. I've thrown my board patches on top but don't get very far
> > with regards to USB due to clk:
> > U-Boot 2022.04-rc5-00085-gce6842669a59-dirty (Apr 04 2022 - 11:32:45 -0700)
> >
> > CPU: Freescale i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)
> > CPU: Industrial temperature grade (-40C to 105C) at 38C
> > Reset cause: POR
> > Model: Gateworks Venice GW74xx i.MX8MP board
> > DRAM: 1 GiB
> > clk_register: failed to get osc_32k device (parent of usb_root_clk)
> > Core: 210 devices, 23 uclasses, devicetree: separate
> > WDT: Started watchdog at 30280000 with servicing (60s timeout)
> > MMC: FSL_SDHC: 0, FSL_SDHC: 2
> > Loading Environment from nowhere... OK
> > In: serial at 30890000
> > Out: serial at 30890000
> > Err: serial at 30890000
> >
> > u-boot=> usb start
> > starting USB...
> > Bus usb at 38100000: Port not available.
> > Bus usb at 38200000: Port not available.
> >
> > I see 'clk_register: failed to get osc_32k device (parent of
> > usb_root_clk)' above yet clock-osc-32k seems to be there:
>
> [...]
>
> > I've got the following in my config:
> > CONFIG_CLK_CCF=y
> > CONFIG_CLK_COMPOSITE_CCF=y
> > CONFIG_CLK_IMX8MP=y
> > ...
> > CONFIG_USB_XHCI_DWC3=y
> > CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
> > CONFIG_USB_DWC3=y
> > CONFIG_USB_DWC3_GENERIC=y
> > ...
> > CONFIG_POWER_DOMAIN=y
> > CONFIG_IMX8M_POWER_DOMAIN=y
> >
> > Any ideas?
>
> "Port not available" means device_probe() returns -ENODEV in usb uclass,
> maybe you're still missing some regulator driver or some such ? You'd
> have to dig into that.
Marek,
Thanks - I was missing CONFIG_IMX8MP_HSIOMIX_BLKCTRL. IMX8MP USB is
working now. I will respond to the individual patches you have.
Best Regards,
Tim
More information about the U-Boot
mailing list