[PATCH V2 10/26] imx: imx8ulp: enable MU0_B clk by default
Peng Fan (OSS)
peng.fan at oss.nxp.com
Wed Apr 6 08:30:15 CEST 2022
From: Peng Fan <peng.fan at nxp.com>
Enable MU0_B clk by default. When M33 image is loaded by Jlink,
the previous method not enable MU0_B clk and not able to communicate
with M33, so let's enable it by default.
And we not put it under kernel dts, because it conflicts with i.MX8QM
suspend/resume logic which requires large change.
Reviewed-by: Ye Li <ye.li at nxp.com>
Reviewed-by: Jacky Bai <ping.bai at nxp.com>
Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
arch/arm/mach-imx/imx8ulp/clock.c | 3 +++
arch/arm/mach-imx/imx8ulp/soc.c | 3 ---
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index 69cccafbcef..3e71a4f6c3b 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -214,6 +214,9 @@ void clock_init_late(void)
pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
}
+ /* enable MU0_MUB clock before access the register of MU0_MUB */
+ pcc_clock_enable(3, MU0_B_PCC3_SLOT, true);
+
/*
* Enable clock division
* TODO: may not needed after ROM ready.
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 85bf57b8e51..5f0a45b356a 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -156,9 +156,6 @@ int m33_image_handshake(ulong timeout_ms)
int ret;
ulong timeout_us = timeout_ms * 1000;
- /* enable MU0_MUB clock before access the register of MU0_MUB */
- pcc_clock_enable(3, MU0_B_PCC3_SLOT, true);
-
/* Notify m33 that it's ready to do init srtm(enable mu receive interrupt and so on) */
setbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0)); /* set FCR F0 flag of MU0_MUB */
--
2.35.1
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