[PATCH v1 0/2] imx6 ddr initialization fixes

[Francesco Dolcini]

Dear all,
the following series fixes a couple of issues on the i.MX6 DDR3 memory
initialization we discovered while debugging some rare boot failures on
apalis-imx6 [0]. This is a follow-up of this RFC series [1], with the
apalis-imx6 changes removed since we do plan doing additional validation before
merging.

[0] https://lore.kernel.org/all/20211202161428.GA104937@francesco-nb.int.toradex.com/
[1] https://lore.kernel.org/u-boot/20220404085119.97792-1-francesco.dolcini@toradex.com/

Changes in v1:

Add Reviewed-by: Marek Vasut marex at denx.de
Commit message and comments improvements, no code changes.

Francesco Dolcini (2):
  mx6: ddr: Restore ralat/walat in write level calibration
  mx6: ddr: Wait before issuing the first MRS cmd

 arch/arm/mach-imx/mx6/ddr.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

-- 
2.25.1